RU2302084C2 - Synchronization device - Google Patents

Abstract

FIELD: digital communications, namely engineering of devices for synchronizing digital information transfer systems with time compression of digital streams.

SUBSTANCE: synchronization device contains first and second random-access memory units, operation mode calibration block, frame synchronization combination decoder, information signals commutation block, first phasing block and generator equipment. Second phasing block, block for finding super-frame synchronization combination and block for finding super-frame synchronization are introduced into the device.

EFFECT: decreased time spent on searching for synchronism of digital transmissions with various types of modulation having super-frame structure.

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Description

The invention relates to digital communication technology, and in particular to devices for synchronizing digital information transmission systems with temporary compression of digital streams.

Digital transmissions are known, the structure of which consists of a supercycle containing N cycles. In each cycle, bits of cyclic and super-cycle sync are transmitted. The supercycle is organized to determine the moment of scrambling start, as well as to organize signal and service channels. An example of such a transfer is shown in figure 1. The supercycle length of these gears can reach several hundred thousand positions.

Known devices for cyclic synchronization [RF Patent No.2019046, class. H04L 7/08; RF patent No. 2136111, class H04L 7/08; Levin L.S., Plotkin M.A. Digital information transfer systems. - Radio and communications, 1982, pp. 102 and 103, Fig. 4.4.], Containing a shift register, a cyclic clock signal identifier, a sync signal analyzer, a synchronism hold and search unit, and generator equipment.

The disadvantage of these devices is:

- the inability by the same device to synchronize various information transfers with asynchronous integration of digital streams.

A device for cyclic synchronization [RF Patent No. 2187210, class. H04L 7/08], containing random access memory, a device for tuning and diagnostics, a device for storing the criteria for entering synchronism and out of synchronism, a synchronization decoder, a phasing device, and generator equipment. This device allows you to synchronize various digital information transmissions with temporary compaction and type of modulation FM-2.

The disadvantages of this device are:

- the inability to synchronize digital transmissions with the types of phase modulation FM-4, FM-8 and various types of quadrature-amplitude modulation;

- long time to search for synchronism with digital transmission super-cycle lengths of up to several hundred bits, because synchronism search is carried out by a sequential method.

A device for cyclic synchronization is known [RF Patent No. 2190304, class. H04L 7/08, H04J 3/06], comprising a random access memory, a memory register, a sync combination decoder, a distributor, a phasing device, generator equipment, AND, OR, NOT elements. This device allows to reduce the search time for synchronism with evenly distributed synchronization in a cycle (supercycle) due to the parallel search.

The disadvantages of this device are:

- the inability by the same device to synchronize digital transmissions with various types of modulation;

- the inability to synchronize with unevenly distributed positions of synchronization in the cycle (supercycle).

The closest in technical essence to the claimed invention is selected as a prototype device for cyclic synchronization [RF Patent No. 2237374, class. H04L 7/08] containing random access memory, a tuning and diagnostic device, a sync combination decoder, generator equipment, a phasing device, a signal tuner, a decoder, and a counter. This device provides a single device cyclic synchronization of a large class of digital transmissions with various types of modulation.

The disadvantage of this device is:

- a sufficiently long time to search for synchronism with the lengths of the super cycle of digital transmissions up to several hundred bits, because synchronism search is carried out by a sequential method.

An object of the invention is to reduce the search time for synchronism of digital transmissions with various types of modulation having a super-cycle structure.

This task is achieved by the fact that in the synchronization device containing the first and second random access memory (RAM), an operating mode setting unit (PP setting unit), a cyclic sync combination decoder (CSK decoder), an information signal switching unit (IC switching unit), the first phasing unit, generator equipment (GO), moreover, the clock inputs of the CSK decoder, the switching unit of the IS and GO are connected to each other and are the clock input of the device, the address outputs of the GO are connected to the corresponding inputs the first and second RAM are the address outputs of the device for synchronization, the read output, the write output and the first and second outputs of the selection of the PP tuner are connected to the corresponding inputs of the first and second RAM, the inputs / outputs of the end of the supercycle and the end of the cycle of the first RAM are connected to the corresponding inputs / the outputs of the PP tuner and are the outputs of the end of the supercycle and the end of the cycle of the device for synchronization, the input / output of the end of the sync combination of the first RAM is connected to the corresponding inputs of the decoder CSK, the switching unit And C, of the first phasing unit and the input / output of the PP tuner, the inputs / outputs of the positions and values of the clock sync combination of the first RAM are connected to the corresponding inputs / outputs of the PP tuner and the inputs of the CSK decoder, the response output of which is connected to the corresponding input of the first phasing block, the output is zero the state of which is connected to the corresponding inputs of the switching unit IS and GO, the inputs of the clock cycles and asynchronous zero setting of which are connected to the corresponding outputs of the PP tuner, the outputs of Or, determining the number of information inputs of the device for synchronization are connected to the corresponding inputs of the switching unit IC, the information inputs of which are information inputs of the device for synchronization, the information inputs of the decoder CSK are connected to the corresponding outputs of the switching unit IC, the output of the end of the switching of which is connected to the corresponding input of the IC, information inputs / outputs, inputs of mode selection, new address, zeroing, writing, reading, selecting the first or second settings of the RAM, the choice of the RAM setting or the registers of the PP tuning unit are the corresponding inputs of the device for synchronization, the input of the selection of the GO mode is connected to the corresponding input of the device for synchronization, according to the invention, a second phasing unit, a super-cycle sync search unit (SCSC search unit) and a super-cycle search unit are introduced synchronization (SSC search unit), and the inputs / outputs of the positions of the super-cycle sync combination of the second RAM are connected to the enabling inputs of the SSCS search unit and the inputs / outputs of the block n the PP settings, the outputs of the used bits of the registers and the values of the super-cycle sync combination of the PP tuning unit are connected to the corresponding inputs of the STSK search unit, the information outputs of the IC switching unit are connected to the information inputs of the STSK search unit, the output of which is connected to the response input of the second phasing unit, the input of the end of the sync combination of which is connected with the corresponding output of the SCS search unit, the output of the presence of synchronization of the first phasing unit is connected to the corresponding input of the SCS search unit, the output The synchronization of the second phasing unit is connected to the corresponding input of the SCC search unit, the output of which is the synchronization output of the device for synchronization, the zero state output of the second phasing unit is connected to the corresponding input of the CCC search unit, the inputs of the end of the cycle and the end of the supercycle of which are connected to the corresponding outputs of the first RAM , the output of the synchronous installation to zero the search block STsS is connected to the corresponding input of GO, the clock input of the search block STSS is the clock input of the device Twa.

The novelty of the technical solution lies in the presence of new circuit elements in the claimed device: a second phasing unit, a super-cycle sync-search unit, a super-cycle synchronization search unit.

Thus, the invention meets the criterion of "novelty."

Analysis of known technical solutions in the studied and related fields allows us to conclude that the introduced functional units are known. However, their introduction into the device for synchronization with the indicated relationships gives this device new properties. The introduced functional units interact in such a way that reduces the search time for synchronism of digital transmissions having a super-cycle structure.

Thus, the invention meets the criterion of "inventive step", because it does not explicitly follow from the prior art for a specialist.

The invention can be used in digital transmission systems with temporary compression of digital streams.

Thus, the invention meets the criterion of "industrial applicability".

Figure 1 presents an example of a digital transmission with a supercycle structure, figure 2 is a structural electrical diagram of a device for synchronization, figure 3 is a structural electrical diagram of a switching unit of information signals.

A device for synchronization (figure 2), contains a first random access memory (RAM) 1, a mode setting unit (PP setting unit) 2, a cyclic synchronization decoder (CSK decoder) 3, a information signal switching unit (IC switching unit) 4, the first phasing unit 5, generator equipment (GO) 6, the second RAM 7, the second phasing unit 8, the super-cycle synchronization search unit (SCSK search unit) 9, the super-cycle synchronization search unit (SCS search unit) 10, and the clock input (input T) devices for synchronization connected to the corresponding inputs of the decoder CSK 3, switching unit IS 4, GO 6, search block STSK 9, address outputs (outputs 0, ..., N) GO 6 are connected to the corresponding inputs of the first RAM 1 and second RAM 7 and are address outputs devices for synchronization, the read output (OE output) and the write output (WE output) of the PP 2 tuner are connected to the corresponding inputs of the first and second RAM, the first select output (CE1 output) and the second select output (CE2 output) of the PP 2 tuner respectively, with the inputs of the selection of the first and second RAM, inputs / you the strokes of the end of the supercycle (CCC input / output) and the end of the cycle (CC input / output) of the first RAM 1 are connected to the corresponding inputs / outputs of the PP 2 tuner and are outputs of the supercycle end and the cycle end of the device for synchronization, the input / output of the end of the sync combination (input input / output KSC) of the first RAM 1 is connected to the corresponding inputs of the decoder CSK 3, the switching unit IS 4, the first phasing unit 5 and the input / output of the tuner PP 2, the inputs / outputs of the positions (inputs / outputs of the PC ₁ , ..., PC _n ) and values (inputs / outputs of the PC ₁ , ..., PC _n ) cyclic sync and the first RAM 1 are connected to the corresponding inputs / outputs of the PP 2 tuner and the inputs of the CSK 3 decoder, the response output (SK output) of which is connected to the corresponding input of the first phasing unit 5, the zero state output (DS output “0”) of which is connected to the corresponding the inputs of the switching unit IS 4 and GO 6, the inputs of the tuning clock (input of the VT) and asynchronous zero (A.RES input) of which are connected to the corresponding outputs of the tuner PP 2, the outputs of which determine the number of information inputs of the device for synchronization downs (outputs A ₀ , ..., A _n ) are connected to the corresponding inputs of the switching unit IS 4, information inputs (inputs And ₁ , ..., And _n ) of which are information inputs of the device for synchronization, information inputs (inputs And ₁ , ..., And _n ) of the CSK 3 decoder are connected to the corresponding outputs of the switching unit IS 4, the output of the end of the switching (CP output) of which is connected to the corresponding input of GO 6, information inputs / outputs (inputs / outputs 1, ..., N ), mode selection inputs (MODE input), new address (ON input), zero (RES input), records (WE input) ), reading (OE input), selecting a custom RAM (input A), selecting a RAM setting or a register (RAM / RG input) of the PP 2 tuner are the corresponding inputs of the device for synchronization, the mode selection input (MODE input) GO 6 is connected to the corresponding the input of the device for synchronization, the inputs / outputs of the positions of the super-cycle synchronization (inputs / outputs of the PSC ₁ , ..., PSC _n ) of the second RAM 7 are connected to the enabling inputs (inputs CE ₁ ... CE _n ) of the search block SCSC 9 and the inputs / outputs tuner PP 2, the outputs of the used bits of the registers (outputs P1 ₁ , ..., P1 _k , .. ., PN ₁ , ..., PN _k ) and super-cycle sync values (outputs Z1 ₁ , ..., Z1 _k , ..., ZN ₁ , ..., ZN _k ) of the PP 2 tuner are connected to the corresponding inputs SCSK 9 search unit, information outputs (outputs AND ₁ , ..., AND _n ) of the IS 4 switching unit are connected to the corresponding inputs of the SCSK 9 search unit, the output of which (SC output) is connected to the corresponding input of the second phasing unit 8, the end of the sync input (input KSK) which is connected to the corresponding output of the search block SCS 10, the output of the presence of synchronization (output F) of the first phasing unit 5 s is single with the input F1 of the search block STsS 10, the output of the presence of synchronization (output Ф) of the second phasing unit 8 is connected to the input Ф2 of the search block STsS 10, the output of which is the output of the presence of synchronization (output Ф) of the device for synchronization, the output is zero state (output DS " 0 ") of the second phasing block 8 is connected to the corresponding input of the search block CCL 10, the outputs of the CC and CCC of the first RAM 1 are connected to the corresponding inputs of the search block CCC, the synchronous zero input (input iRES) GO 6 is connected to the corresponding output of the search block CCC 10 .

The information signal switching unit (IP switching unit) 4 (Fig. 3) contains triggers 11 ₂ , ..., 11 _n , a switch 12, a decoder 13, a counter 14, and the first input (input I1) of the current value of the information signal is connected to the corresponding the input of the switch 12, from the second to the n-th inputs (inputs And ₂ , ..., And _n ) of the current values of the information signals are connected to the corresponding inputs of the switch 12 and, respectively, with the information inputs (inputs D) of the triggers 11 ₂ , ..., 11 _n, whose outputs are connected respectively to the inputs of OF _2, ..., OUT _n switch 12, y ulation input (Y _1, ..., Y _n) the switch 12 are connected to the respective outputs of the decoder 13, data outputs (outputs ₁ and, ..., and _n) the switch 22 are the respective outputs of the IC 4. Input switching unit switching unit IC 4, determining the number of information inputs of the device for synchronization (inputs A ₀ , ..., A _n ) are connected to the corresponding inputs of the decoder 13, inputs B ₀ , ..., B _{n of} which are connected to the corresponding outputs of the bits of the counter 14, the end output switching (output KP) of the decoder 13 is connected to the counter input 14 and is the corresponding output of the switching unit IC 4, the input of the end of the synchronization (KSC input) of the switching unit IP 4 is connected to the corresponding input of the counter 14, the clock input (input T) of the switching unit IP 4 is connected to the clock inputs of the triggers 11 ₂ ,. .., 11 _n and counter 14, the input DS "0" of which is the corresponding input of the switching unit IC 4.

A device for synchronization works as follows. The device for synchronization has two modes of operation. The first is the setup and diagnostic mode, the second is the operation mode.

In the first mode, the inputs of the PP 2 tuner receive signals from a controller that works in conjunction with a personal electronic computer (PC). The setup and diagnostic mode is enabled by the Log. "0" signal, which is input to the mode selection input (MODE input) of the PP 2 tuner. The Log. "1" signal, which is input to the setup memory selection input or register (RAM / RG input) setting block PP 2, it is allowed to configure random access memory (RAM). The selection of the tunable RAM is carried out by the signal fed to the input A of the PP 2 tuning unit. When setting up the first RAM 1, its signal input (input CE1) receives the Log. "0" signal from the output CE1 of the PP 2 tuning block, allowing the operation of the first RAM 1. When recording information in the first RAM 1 from the read output (OE output) of the PP 2 tuner to the corresponding input of the first RAM 1, a Log. "1" signal is received. At the installation input to zero (A.RES input) of the PP 2 tuner, a pulse signal of positive polarity is received, which from the RES output of the PP 2 tuner, arriving at the corresponding input of GO 6, sets its counter to zero. Address 0, ..., N outputs of the counter GO 6 are connected to the corresponding address inputs of the first 1 and second 7 RAM. Then, according to the write signal coming from the write output (WE output) of the PP 2 tuner to the corresponding input of the first RAM 1, the last data is written to the last address at the zero address from the corresponding inputs / outputs of the PP 2 tuner. After that, the new address is input (input ON) of the PP 2 tuning unit, a signal is received which, coming from the output of the tuning clocks (VT output) of the PP 2 tuning unit to the corresponding input of GO 6, changes the address of its counter and, therefore, the address of the first RAM 1.

Further, data recording at the new address is carried out as described above.

To verify the correct configuration of the first RAM 1, the zero signal received from the A.RES output of the PP 2 tuner to the corresponding input of GO 6, its counter is set to zero. After that, with the Log. "1" signal received at the write input (WE input) of the PP 2 tuner and then from the output of the PP 2 tuner WE to the corresponding input of the first RAM 1, the latter is put into read mode. Then the signal Log. "0", received at the read input (input ОЕ) of the PP 2 tuning unit and then from the output ОЕ of this block to the corresponding input of the first RAM 1, information is read at the zero address of the first RAM 1. At the same time, the signals from the outputs of the last arrive at the corresponding inputs of the PP 2 tuner and then to the PC controller for comparison with the original ones. Then, at the signal of the new address, the address of the first RAM 1 is changed and the data is read at the new address in the same way as previously described.

Similarly, tuning is performed and the correctness of tuning of the second RAM is checked. 7. The number of the tunable RAM is set by the signal received at input A of the PP 2 tuner.

After setting and checking the correctness of the settings of the first 1 and second 7 RAMs, the memory registers of the PP 2 tuning unit are set up. The memory registers are configured with the Log. "0" signal received at the RAM / RG input of the PP 2 tuning unit. In this case, the procedure for setting and checking it correctness is the same as for RAM.

The device for synchronization is switched to the operating mode by the Log. "1" signal, which is input to the MODE of the PP 2 tuner. In this case, the selection signals from the CE1 and CE2 outputs of the PP 2 tuner allow the first 1 and second 7 RAM to work, and the signals Log. "0" and Log. "1", respectively, coming from the read outputs OE and the WE record of the PP 2 tuner to the corresponding inputs of the first 1 and second 7 RAM, the latter are transferred to the data reading mode. In the setup mode, the clock ticks of the counter of the position of the GO 6 receive tuning clocks from the output of the ТР 2 tuner, and in the operating mode, from the clock input Т of the device for synchronization.

The operation of the device for synchronization is as follows. The address inputs (inputs 0, ..., N) of the first RAM 1 and the second RAM 7 receive signals from the corresponding outputs of GO 6, while at the corresponding addresses at the outputs of the RAM 1 signals of the end of the supercycle (output of the CCC), the end of the cycle (output KC), the end of synchronization pattern (yield XK) position (HRC outputs _1, ..., PC _n) and the values (outputs ZTS _1, ..., ZTS _n) of frame synchronization pattern, and outputs PCC _1, ..., PSC _n RAM 7 the signals of the positions of the super-cycle sync are formed. Initially, cyclic synchronization is carried out, and then, after its finding, the super-cycle synchronization of the device. Loop synchronization is as follows. Signals of positions, values and the end of the clock cycle from the corresponding outputs of the first RAM 1, information signals from the corresponding information outputs (outputs AND ₁ , ..., AND _n ) of the switching unit IS 4, as well as clock signals from the clock input T of the device for synchronization are received to the corresponding inputs of the decoder CSK 3.

The CSK 3 decoder compares the values of information signals with those specified in the first RAM 1 at cyclic sync positions, also specified in the first RAM 1, and generates a comparison result at its response output (SK output). In the event of a positive response, the Log. "1" signal is generated at the SC output of the CSK 3 decoder, and in the case of a negative response, the Log. "0" signal is generated. The response signal from the SC output of the CSK 3 decoder and the end signal of the cyclic synchronization from the KSC output of the first RAM 1 are supplied to the corresponding inputs of the first phasing unit 5. Until the first positive response from the SK output of the decoder CSK 3, the first phase block 5 is in the zero state and the Log signal . "1", coming from its zero state output (DS output "0") to the corresponding inputs of the switching unit IS 4 and GO 6, the operation of the switching unit IS 4 and removal of clock cycles in GO 6 is allowed. In the absence of a positive response at the output SC signal of the end of the switching coming from the output (output KP) of the switching unit IS 4 to the corresponding input of GO 6, the removal (skipping) of one cycle. Thus, the phase of operation of the counter of positions of GO 6 changes with respect to the phase of digital transmission. In the described mode, the device for synchronization works until the first cyclic synchronization is found. After receipt of the corresponding inputs of the first phasing unit 5 of a positive response and the end of the cyclic synchronization, the reverse counter of this unit is set to positive mode and increases its state by one. In this case, the Log. "0" signal generated on the DS "0" output of the first phasing unit 5 prohibits the removal of a clock in GO 6 and the switching unit IC 4. Thus, if there is a positive response signal at the SC input of the first phasing unit 5, the reverse counter the latter increases its state by one, and in the absence of a positive response, it decreases by one. When the difference in the number of signals of positive and negative responses reaches the value specified in the first phasing unit 5, the device for synchronization switches to the cyclic synchronization mode. In this mode, the device for synchronization is located until the difference in the number of signals of negative and positive responses reaches the value specified in the first phasing unit 5. In this case, the first phasing unit 5 is set to zero, and the device for synchronization switches to the search mode of cyclic synchronization, as described previously.

The switching unit IP 4 (Fig. 3) is designed to convert information signals received at its inputs, so that the first information signal in the digital transmission supercycle is on the first information output of this block. The operation of the switching unit IP 4 will be described later.

Until cyclic synchronization is found, operation of the synchronization device for searching for super-cycle synchronization by the Log. "0" signal from the output Ф of the first phasing unit 5 to the input Ф1 of the CCS search unit is prohibited. At the same time, at the output of the KSK of the search module SCS 10, the formation of a signal arriving at the input of the KSK of the second phasing unit 8 is prohibited, and the latter is in the zero state. When searching for cyclic synchronization, synchronous zeroing of GO 6 is carried out by a signal from the output of the SCC RAM 1 coming through the input of the SCC and the i.RES output of the SCC search block to the input of i.RES GO 6.

After finding the cyclic synchronization, the search for super-cyclic synchronization is allowed. In this case, the signals Log. "1", coming from the output Ф of the first phasing unit 5 to the input Ф1 of the STS search unit and from the DS "0" output of the zero state of the second phasing unit 8 to the DS "0" input of the STS search unit 10, the signal is allowed to pass from the output of the CC RAM 1 through the input of the CC and the i.RES output of the search block CCS 10 to the i.RES input of the synchronous installation to zero GO 6.

The search for supercycle synchronization is carried out as follows. The signals from the outputs of the positions of the super-cyclic sync combination (outputs PSC ₁ , ..., PSC _n ) of the second RAM 7 are fed to the enable inputs (inputs CE ₁ , ..., CE _n ) of the search module CCSC 9. To the information inputs (inputs And ₁ , ..., And _n ) of the STSKK search block 9, signals from the corresponding information outputs (outputs And ₁ , ..., And _n ) of the switching unit IP 4. signals are received. The value of the super-cycle synchronization for each information input is set by the signals coming from the outputs Z1 ₁ , ..., _k P1, ..., ZN _1, ..., _k ZN PP tuner 2 to the corresponding inputs searcher STSSK 9. sve Length htsiklovoy sync pattern, at the positions for each data input is given the signals coming from the outputs P1 _{1, ..., P1 k, ...,} PN _1, ..., PN _k RR tuner 2 to respective inputs of the search block STSSK 9 .

Practice has shown that 16 positions are the optimal number of positions for super-cycle synchronization at one information input for different types of modulation. If the number of positions of super-cycle sync on one information input exceeds the number 16, then in the second RAM 7 the last sixteen positions of super-cycle sync are set. If the number of positions of the super-cycle synchronization is less than sixteen, then Log. "0" signals from the corresponding outputs of the PP 2 tuner are received for the missing positions.

When the super-cycle synchronization is found at the output of the SC of the search unit SCSK 9, a positive response signal is generated. After entering the second phasing unit 8 of the first positive response to the input of the SC phase 8 and to the input of the KSC signal, which is received in the presence of cyclic synchronization from the output of the CC RAM 1 through the input of the KC and the output of the KSC of the search block CCC 10, the reverse counter of the second phasing block is set to the positive counting mode and increases his condition by one. At the same time, the signal Log. "0" at the output DS "0" of the second phasing unit 8 prohibits the passage of the signal from the output of the CC RAM 1 to the output of the KSC of the search block CCS 10 and the passage of the signal to the output of the output of the CCC RAM 1 is allowed. the signal from the CC output to the input i.RES of the search block CCS 10 and then to the input i.RES GO 6. Now the input i.RES GO 6 receives a signal from the output of the CCC RAM 1 through the input of the CCC and the output i.RES of the search CCC 10.

The operation of the second phasing unit 8 is carried out in the same way as the operation of the first phasing unit 5.

When the device enters the super-cycle synchronization mode, the Log. "1" signal appears at the output Ф of the second phasing unit 8. This signal is fed to the input Ф2 of the CCS search unit 10. At the same time, the Log. "1" signal appears at the output Ф of this block. for the presence of cyclic and super-cycle synchronization of the device.

The switching unit IP 4 (figure 3) works as follows. The signals from the information inputs (inputs And ₁ , ..., And _n ) of the switching unit IP 4 are fed to the corresponding inputs of the switch 12, and from the inputs And ₂ , ..., And _n to the inputs of the triggers 11 ₂ , ..., 11 _n . From the outputs of the triggers 11 ₂ , ..., 11 _n information signals delayed by one clock are fed to the inputs FROM ₂ , ..., FROM _{n of the} switch 12. The signals from the inputs of the switching unit IS 4, which determine the number of information inputs (inputs A ₀ , ..., A _n ), are fed to the corresponding inputs of the decoder 13. The signals from the inputs of the KSK, DS "0" and T switching unit IP 4 are fed to the corresponding inputs of the counter 14. When searching for cyclic synchronization, the operation of the counter 14 is enabled by the signal Log. "1 "arriving at its input DS" 0 ". When signals are received at the inputs of KSK and T of counter 14, the latter changes its state by one. The counter 14 is reset to zero by the signal from the output of the end of the switching (output of the CP) of the decoder 13 to the input of the counter 14. The decoder 13 decrypts the states of the counter 14. In accordance with the status of the counter 14 at one of the control outputs (outputs U ₁ , ..., _n ) of the decoder, a Log signal appears. "1", which, arriving at the corresponding control input of the switch 12, determines the order of the rebuilding of the information signals. The counter 14 changes its state once per digital transmission supercycle. The full cycle of the operation of the switching unit IS 4 takes place in n supercycles, where n is the number of information inputs of the device for synchronization.

Re-switching of information signals is as follows. In the zero state of the counter 14, the Log. "1" signal arriving at the input U _{1 of the} switch 12, the current information signals are switched from the inputs And ₁ , ..., And _{n of the} switch 12 to its outputs And ₁ , ..., And _n . In the first state of the counter 14, the Log. "1" signal arriving at the input U _{2 of the} switch 12, the information signal is delayed by one clock cycle (previous value) from the input FROM _{n of the} switch 12 to its output AND ₁ , and the current information values from inputs And ₁ , ..., And _n-1, respectively, to the outputs And ₂ , ..., And _n . In the second state of the counter 14, the Log. "1" signal arriving at the input U _{3 of the} switch 12, the previous values of the information signals are switched from the inputs FROM _n-1 and FROM _{n of the} switch 12, respectively, to its inputs And ₁ and And ₂ , and the current values - from the inputs AND ₁ , ..., AND _n-2, respectively, to the outputs AND ₃ , ..., AND _n , etc. In the nth state of the counter 14, the Log. "1" signal arriving at the input U _{n of the} switch 12, the previous values of the information signals are switched from the inputs FROM ₂ , ..., FROM _{n of the} switch 12 respectively to its inputs AND ₁ , .. ., And _n-1 , and the current value - from the input And _1, respectively, to the output And _n .

If a cyclic synchronization is not detected during the reconnection cycle, then the signal of the end of the commutation received from the output of the switching unit of the IS 4 switching unit to the input of the GO 6 is skipped in the last one cycle and the operation cycle of the switching unit of the IP 4 is repeated, as described previously.

After finding the first cyclic synchronization signal Log. "0", arriving at DS "0" input of the switching unit IP 4, the further operation of the latter is prohibited.

For the technical implementation of the synchronization device, we used static random access memory (RAM) of the KM68257CJ-15 type imported by SEC and the user-programmable logic integrated circuit (FPGA) XC4020XLA by XILINX.

The present invention allows to reduce n ² times, compared with the prototype, the search time for synchronism of digital transmissions with various types of modulation having a super-cycle structure due to the implementation of the method of sequentially-parallel synchronization search, in which the search for cyclic synchronization is carried out by the sequential method, and the super-cycle - parallel method, where n is the number of cycles in a digital transmission supercycle.

Claims (1)

A synchronization device comprising first and second random access memory (RAM), an operating mode setting unit (PP), a cyclic sync combination decoder (CSK), an information signal switching unit (IC), a first phasing unit, generator equipment (GO), and clock the inputs of the CSK decoder, the switching unit IS and GO are interconnected and are the device’s clock input, the address outputs of the GO are connected to the corresponding inputs of the first and second RAM and are the address outputs of the device, read output, output d records and the first and second outputs of the selection of the PP tuner are connected to the corresponding inputs of the first and second RAM, the inputs / outputs of the end of the supercycle and the end of the cycle of the first RAM are connected to the corresponding inputs / outputs of the PP tuner and are outputs of the supercycle end and the end of the device cycle, input / the output of the end of the sync combination of the first RAM is connected to the corresponding inputs of the CSK decoder, the switching unit of the IC, the first phasing unit and the input / output of the PP adjustment unit, the inputs / outputs of the positions and values of the cyclic sync The sections of the first RAM are connected to the corresponding inputs / outputs of the PP tuner and the inputs of the CSK decoder, the response output of which is connected to the corresponding input of the first phasing block, the zero state output of which is connected to the corresponding inputs of the IS and GO switching block, the inputs of the tuning clock and asynchronous zero which are connected to the corresponding outputs of the PP tuner, whose outputs, which determine the number of information inputs of the device, are connected to the corresponding inputs of the switching unit and IC, the information inputs of which are information inputs of the device, the information inputs of the CSK decoder are connected to the corresponding outputs of the switching unit of the IC, the output of the end of the switching is connected to the corresponding input of the GO, information inputs / outputs, inputs of mode selection, new address, zeroing, recording , reading, selecting the settings of the first and second RAM, selecting the settings of the RAM or the registers of the PP tuning unit are the corresponding inputs of the device, the input of the selection of the GO mode is connected to the corresponding m device input, characterized in that a second phasing unit, a super-cycle synchronization search unit (SCSC) and a super-cycle synchronization search unit (SCC) are introduced, wherein the inputs / outputs of the second-cycle super-cycle synchronization positions are connected to the enabling inputs of the SCSC search block and the block inputs / outputs PP settings, outputs of the used bits of the registers and values of the super-cycle sync combination of the PP settings unit are connected to the corresponding inputs of the SCSK search unit, information outputs of the switching unit IC is connected are not connected to the information inputs of the SCSK search unit, the output of which is connected to the response input of the second phasing unit, the input of the end of the sync combination of which is connected to the corresponding output of the SCS search unit, the synchronization output of the first phasing unit is connected to the corresponding input of the SCS search unit, the output of the presence of synchronization of the second phasing unit connected to the corresponding input of the SCS search unit, the output of which is the output of the presence of device synchronization, the zero state output of the second phasing unit and connected to the corresponding input of the SCC search unit, the inputs of the end of the cycle and the end of the supercycle of which are connected to the corresponding outputs of the first RAM, the synchronous output of the SCC search unit zero is connected to the corresponding GO input, the clock input of the SCC search unit is the clock input of the device.

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