RU226732U1 - On-board digital computing device - Google Patents

Abstract

The utility model relates to an on-board digital computing device for a strapdown inertial navigation control system. The on-board digital computing device consists of two multilayer printed circuit boards of the processor and an interface module, which is made with the processor as a single unit. The interface module is a homogeneous computing system with a set of devices such as a control circuit with an input signal conditioner, two output signal conditioners, a two-port random access memory device, a quartz resonator, and a block of one-time commands. To exchange information with external subscribers, the interface module is additionally equipped with a redundant multiplex information exchange channel over two information transmission lines operating in terminal device mode, and a non-redundant multiplex information exchange channel over one information transmission line operating in bus controller mode. The processor includes an on-chip built-in self-monitoring circuit, a random access memory, an electrically erasable and programmable read-only memory, galvanic isolation, a one-time command block for receiving one-time input commands, a control circuit including a direct memory access controller, and a central digital signal processing unit. made on the basis of a microcircuit that includes an ultra-random access memory, a frequency divider and two interface blocks.

Description

The utility model relates to the field of measurement technology and instrumentation for military purposes, namely to an on-board digital computing device for a strapdown inertial navigation control system.

From the level of technology (A.V. Bazhenov, Fundamentals of on-board computers, Textbook, Stavropol: SVVAIU, 2008, pp. 138-139) it is known that an on-board digital computer (as a device) usually includes a random access memory device ( RAM), read-only memory (ROM), arithmetic-logical unit (ALU), control unit (CU), power supply (PSU), address, data and control buses (AS, SD, SHU).

RAM is designed to store information coming from sensors, as well as intermediate and final results. RAM is used to both write information and read information from it.

ROM is designed to store information that remains unchanged during operation. Such information includes the operating programs of the on-board digital computer and the constants used to implement the algorithms.

Processor is the main module of an on-board digital computer (as a device), designed to automatically perform sequential operations provided by the problem-solving program.

The processor of an on-board digital computer (as a device) functionally consists of an arithmetic-logical unit (ALU) and a control unit (CU). The ALU is designed to perform arithmetic and logical operations on binary numbers. The control unit serves to organize the computing process in accordance with a given program by forcing the coordination of the operation of all on-board computer devices.

The on-board digital computer (OND) may also include an input/output device for communication with the control object. Structurally, the input/output device can be designed separately from the onboard computer.

The closest analogue of the claimed device is an on-board computer, which is part of the on-board digital computing and control system of aircraft (RU 2414390, priority 04/21/2010).

An on-board digital computer is a device that includes modules of the main processor, peripheral processors, memory and input-output devices connected to the information exchange channel directly or through an input-output device.

The programmable part of the onboard computer includes system and functional software and algorithmic tools that interact in accordance with the intramachine computer-logical exchange highway.

System software and algorithmic tools ensure the general functioning of the onboard computer.

Functional software and algorithmic tools provide solutions to specific problems of navigation, control, control, guidance, group actions, receiving signal processing and issuing the necessary parameters in the on-board information exchange channel in real time.

The disadvantage of an on-board digital computer (as a device) of the closest analogue is that it does not solve the problems of ensuring speed.

The functioning of modern strapdown inertial control systems (BINSU) is based on the operation of on-board digital computing devices that perform the required calculations based on the results of current measurements coming from sensors and devices of the BINSU.

The quality of work of the entire BINSU as a whole depends on the speed of operation of the BTsVU.

The performance of the digital computer is characterized by the speed at which information is processed.

The objective of the claimed device is to increase the performance of the device, which consists in speed.

The declared on-board digital computing device BTsVU is part of the strapdown integrated navigation control system (BINSU) and is designed to solve all computing tasks and operations assigned to BINSU, according to the general algorithm, as well as for organizing exchanges with internal and external subscribers of BINSU, coordinating signal levels and temporary interaction.

The technical result is to increase the performance of the on-board digital computing device.

Achieving the technical result in the claimed device is ensured due to the fact that the processor module includes a processor and an interface unit, made as a single unit.

Also, the declared result in the complex is ensured due to the fact that the on-board digital computing device of the strapdown inertial navigation control system includes a processor, a programmable part consisting of system and functional software and algorithmic tools, memory and input-output devices and connected to the on-board information exchange channel directly or through an I/O device.

The difference from the closest analogue is that the on-board digital computing device consists of two multilayer printed circuit boards of the processor and an interface module, which is made with the processor as a single unit and is a homogeneous computing system with a set of devices such as a control circuit with an input signal conditioner, two output signal conditioner, two-port random access memory, quartz resonator, one-time command block for generating one-time output commands using one output signal conditioner, a byte-multiplex channel transmitter for transmitting control signals to external subscribers via a combined address and data highway using another output signal conditioner .

Moreover, to exchange information with external subscribers, the interface module is additionally equipped with a redundant multiplex channel for information exchange over two information transmission lines operating in terminal device mode and having a multiplex channel terminal with a frequency divider, a galvanic isolation transformer, as well as a receiving and transmitting device, and a non-redundant multiplex an information exchange channel over one information transmission line, operating in bus controller mode and having a multiplex channel terminal, a receiving and transmitting device and a galvanic isolation transformer.

Also, the achievement of a technical result in the claimed device is ensured due to the fact that the processor of the on-board digital computing device includes a control circuit, an operational built-in self-monitoring circuit, a random access memory device, an electrically erasable and programmable read-only memory device, galvanic isolation, a block of one-time commands that receives input one-time commands passing through galvanic isolation, and a central digital signal processing processor, made on the basis of a microcircuit that includes an ultra-random access memory, a frequency divider and two interface blocks, one of which is designed to organize the exchange of signals between the central processor and the interface module along parallel address highways and data, and the other interface block is designed to organize exchange between the central processor, random access memory and electrically erasable and programmable read-only memory along parallel address and data highways.

The processor also includes an interrupt controller that generates interrupt request signals for the central processor depending on the state of input interrupt requests and an external interrupt request, a one-time command controller that generates a control signal for reading input one-time commands, a system bus controller that generates control signals for subscribers of this buses and a signal for controlling the bus driver when exchanging information with system bus subscribers via a combined address and data highway, and an interface controller that generates control signals for the interface module.

The processor control circuit includes a direct memory access controller, which generates a CRAM control signal to the random access memory and a CROM control signal to the electrically erasable and programmable read-only memory, depending on the address value set on the address highway.

Thanks to the above essential features of the device, performance is ensured, which results in an increase in the performance of the BTsVU.

The BTsVU is designed to solve all computational tasks and operations assigned to the BINSU according to the general algorithm, as well as to organize exchanges with internal and external subscribers of the BINSU product, coordinate signal levels and time interaction.

A block diagram of an on-board digital computing device processor is shown in FIG. 1, indicating the following items:

1 - central processor;

2 - address highway for information exchange between the CPU and the interface module XA[12..0];

3 - super-random access memory (SRAM) (2K x 32);

4 - control signals from the processor control circuit to the interface module;

5 - random access memory device RAM [256K x 32];

6 - electrically erasable and programmable read-only memory EEPROM (128K x 32);

7 - address highway A[23..0] for exchange through the interface block between the CPU and RAM, EEPROM and interface module;

8 - data highway D[31..0] for exchanging information between the CPU and RAM or for supplying information from the EEPROM to the interface module;

9 - control diagram of the control system;

10 - CRAM signal for RAM control, supplied to the CPU from the control system;

11 - CROM signal for EEPROM control, supplied to the CPU from the control system;

12 - address highway A[23,20,19];

13 - address highway A[23,16..0];

14 - input interrupt request INTER0 to the control circuit from the interface module upon completion of receiving information coming from external subscribers via lines In.A (navigation parameters) and In.B (radio communication parameters) through the galvanic isolation transformer T4 and the input driver F3;

15 - INTER87 interrupt request from TMK2;

16 - request to interrupt the control circuit with external subscribers (gyroinertial unit) via a parallel K-bus to the control circuit;

17 - control signal CRKI for reading input one-time commands from the one-time command controller, supplied to the CPU from the control system;

18 - signals arriving to and from the K-bus;

19 - USK control signals from the control circuit for K-bus subscribers, arriving via the combined address and data highway AD[15..0];

20 - CKBUS signal for controlling the SF bus driver when exchanging information with K-bus subscribers, supplied to the CPU from the control system;

21 - bus driver ShF;

22 - signals to the interface module;

23 - interface block for organizing exchange between the central processor, RAM and EEPROM along parallel address and data highways;

24 - XD data highway [31..0] for mutual exchange between the CPU and the interface module via the parallel interface (TMS320 bus);

25 - address/data bus AD [15..0] for mutual exchange between the processor and the K-bus (at the beginning of the transaction the address is transmitted, in subsequent cycles the data);

26 - data highway XD [3..0] for mutual exchange between the CPU and the bus driver SF;

27 - XD data highway [15..0] from the CPU via the parallel interface (TMS320 bus) to the interface module;

28 - common bus for supplying signals from the CPU, RAM, EEPROM to the processor of the interface module and back;

29 - address highway A[16..0] for information exchange between the CPU and EEPROM;

30 - interface block for organizing exchange between the central processor and the interface module along parallel address and data highways and the control signal bus;

31 - XD data highway [14..0] for exchanging information from the block of one-time DBK commands via a parallel interface (TMS320 bus);

32 - block of one-time DBK commands;

33 - one-time input commands VRK8 to DBK;

34 - galvanic isolation;

35 - one-time input commands of the control valve [7..0] for galvanic isolation;

36 - one-time input commands of the NP “Suspension number”, with the help of which the address of the op-amp for the BCVA and the input one-time command of the LCA “Parity line of the address of the op-amp” are set;

37 - CPU frequency divider;

38 - frequency 12.5 MHz;

39 - quartz resonator of the central processor at 25 MHz;

40 - INT[3..0] interrupt request to the CPU from the SU interrupt controller.

The Processor (according to Fig. 1) includes:

The central processor of the CPU for digital signal processing, based on the 1867 VTs6F microcircuit, includes:

Super Random Access Memory (SRAM);

frequency divider ST2;

an interface block designed to organize the exchange of information between the CPU and the Interface Module via parallel highways of address XA[12..0] and data XD[15..0] and the bus of control signals DC from the control circuit to the interface module;

an interface block designed to organize the exchange of information between the CPU and RAM, EEPROM along parallel highways of address A[23..0] and data D[31..0];

control circuit of the control system based on a microcircuit, which also includes:

a direct memory access controller that generates control signals CRAM and CROM depending on the address value set on the address highway A[23,20,19].

The block diagram of the Processor includes:

operational built-in self-monitoring scheme;

interrupt controller that generates interrupt request signals INT[3..0] for the CPU depending on the state of the input interrupt requests INTERO, INTER87 and ZPR;

a one-time command controller that generates a control signal CRKI for reading input one-time commands;

K-bus controller, generating control signals USK for K-bus subscribers and a CKBUS signal for controlling the bus driver SF when exchanging information with K-bus subscribers via a combined address and data highway AD [15..0];

interface controller that generates control signals of the control unit to the Interface Module;

random access memory device, made on the basis of the 1637RU1 chip, which has 3 free outputs, 13 address inputs, 8 data inputs/outputs; low level enable input and high level enable input; high level output enable input; low (high) level write (read) permission input and power output from a voltage source. The microcircuit operates at a voltage of 5 V, with a permissible deviation of the voltage value from the nominal value ±10%;

an electrically erasable and programmable read-only memory device EEPROM, made on the basis of the 1638PP1 chip, which has 3 free outputs, 17 address inputs, 8 data inputs/outputs, an enable input and an output enable input, a write (read) enable input and a power output from a voltage source. The microcircuit operates at a voltage of +5 V, with a permissible deviation of the voltage value from the nominal value of ±10%;

block of one-time commands DBK, designed to receive input one-time commands VRK[7...0] through galvanic isolation of the GR, input one-time commands NP[5...1], LCHA and VRK8.

Information exchange between the Processor and the Interface Module is carried out via a parallel interface (TMS320 bus) with separate highways for XA addresses and XD data and a control bus for the control system, as well as using 2 INTER interrupt request inputs. The Interface Module is accessed by Processor commands designed to access memory. Each subscriber is represented by a corresponding number of cells in the general memory field of the on-board computer with fixed addresses.

External subscribers (for example, a gyroinertial unit) exchange information with the on-board computer via a parallel K-bus using an external interrupt request, serial MKIO channels in accordance with GOST R 52070-2003 via information transmission lines LPI serial code in accordance with GOST 18977-79, parallel-serial byte- multiplex channel BMK with one-time commands: input RKI, NP, LCA and output K2, K2_TM.

In addition to performing the main functions, the BTsVU is used to organize system control and operational self-monitoring.

After power is applied, the Processor conducts full self-test: an extended integrated control test (ETC) with a depth of about 95%, after which control is transferred to the working program.

When entering the working program, a control task is solved, during which the sensors are interrogated and their readings are compared, and the correct generation of control signals is also checked. During these checks, the external connections of the CBVU are checked (the resulting check depth then reaches 99%), the serviceability of the sensors and the correct operation of the main circuits of the control systems. If the test results are positive, a sign of serviceability is recorded and the implementation of standard control algorithms begins. The test results are recorded in specially allocated RAM indicator cells and sent to the telemetry system.

A block diagram of an on-board digital computing device is shown in FIG. 2, indicating the following items:

41 - interface module;

42 - processor;

43 - dual-port DRAM random access memory device;

44 - quartz resonator KR at 12 MHz;

45 - control signals CER, arriving at the DRAM after decoding the address XA[12,2..0], generated together with control signals УCQ, coming from the interface module;

46 - CEL control signals arriving at the DRAM after decoding the address XA[12,2..0], generated together with the processor control signals;

47 - control signals CEK arriving at the DBK after decoding the address XA[12,2..0], generated together with the control signals of the processor US;

48 - control signals CEB, arriving after decoding the address XA[12,2..0] on the BMK, generated together with the control signals of the processor CS;

49 - transmitter of the byte-multiplex channel BMK;

50 - interface module control circuit;

51 - first multiplex information exchange channel MKIO1;

52 - terminal of the multiplex channel TMK1 MKIO1;

53 - frequency divider of the terminal of the multiplex channel TMK1;

54 - transmitting and receiving device PPU1 MKIO1;

55 - first galvanic isolation transformer T1;

56 - second galvanic isolation transformer T2;

57 - information transmission line LPI1 through the first galvanic isolation transformer T1 for operation of MKIO1;

58 - information transmission line LPI2 through the second galvanic isolation transformer T2 for operation of MKIO1;

59 - second multiplex information exchange channel MKIO2;

60 - terminal of the multiplex channel TMK2 MKIO2;

61 - transmitting and receiving device PPU2 MKIO2;

62 - third galvanic isolation transformer T3;

63 - information transmission line LPI3 through the third galvanic isolation transformer T3 for operation of MKIO2;

64 - output generator F1 of output one-time commands from DBK;

65 - output generator F2 of output one-time commands from BMK;

66 - input driver F3, receiving information arriving via lines In.A and In.B through galvanic isolation transformer T4, and generating an INTER0 interrupt request upon completion of receiving information;

67 - fourth galvanic isolation transformer T4;

68 - 12 MHz voltage coming from a quartz resonator;

69 - output one-time commands K2 and K2_TM from F1 to external subscribers;

70 - control signals C1, C2, ZPBU along the combined address and data highway BMK[7..0] through the output driver F2 along the combined address and data highway BMK[7..0] to external subscribers;

71 - control signal YCQ, providing interaction between the interface module, MKIO1 and MKIO2;

72 - information arriving via incoming line A;

73 - information arriving via incoming line B;

74 - combined address and data highway ADQ [15..0] for transmitting signals between the control circuit of the control system of the interface module, MKIO1 and MKIO2;

75 - data highway XD[15..0] for transmitting signals from the bus between the control system of the interface module, the processor and the DRAM;

76 - data highway XD[3..0] for transmitting signals to the bus between the control system of the interface module, the processor and the DRAM;

77 - address highway XA[12,2..0] for supplying signals to the control system of the interface module via the control signal bus;

78 - data highway XD[11..0] for transmitting signals via the bus between the control system of the interface module and the BMK.

According to the block diagram in Fig. 2 BTsVU includes:

an address decoding block designed to receive an address via the address highway XA[12,2..0], decrypt it and generate control signals CER (together with control signals УCQ coming from the control circuit of the interface module) and signals CEL CEK and CEB (together with control signals US);

serial code receiver designed to receive information in accordance with GOST 18977-79 and RTM1495-75, arriving along the lines In.A and In.B through a galvanic isolation transformer T4 type BTI8-52 V (transformer unit for use in microelectronic equipment, with operating voltage up to 24 V, with an operating temperature range of 60 ° C + 100 ° C and an electrical insulation strength of 250 V) and an input driver FZ, as well as for generating an INTER0 interrupt request upon completion of receiving information;

a block of one-time commands DBK, designed to generate output one-time commands K2 and K2_TM using the output driver F1;

transmitter of the byte-multiplex channel BMK, designed for generating control signals C1, C2, ZPBU and transmitting information to external subscribers via the combined address and data highway BMK [7..0] through the output driver F2;

dual-port random access memory DRAM;

12 MHz quartz resonator;

redundant multiplex information exchange channel MKIO1, operating in the Terminal Device (OU) mode under the control of the multiplex channel terminal TMK1 on the information transmission line LPI1 and LPI2 in accordance with GOST R 52070-2003, and includes:

TMK1 with frequency divider ST2, made on the basis of the N1582VZh3V-0213 microcircuit (contains frequency divider ST2) and generating an INTER87 interrupt request;

transceiver device PPU1, made on microassembly 852IN1P, which is a two-channel transmitter with two transceivers that do not have common elements and are intended for building interface devices in accordance with GOST 26765.52-87 and GOST R 52070-2003. The basis of each channel of the microassembly is a CMOS (complementary metal-oxide-conductor) analog-digital core integrated system, including an input logic block, a pre-amplifier for the transmitter and limiter, a complex differential comparator and an input logic block for the receiver;

galvanic isolation transformers T1 and T2 type TIL3V;

non-redundant multiplex information exchange channel MKIO2, operating in Bus Controller (BC) mode under the control of the multiplex channel terminal TMK2 on the information transmission line LPI3 in accordance with GOST R 52070-2003, and includes:

TMK2, made on the basis of the N1582VZh3V-0213 microcircuit, generating an INTER87 interrupt request;

transmitting and receiving device PPU2, made by microassembly 852IN1P;

galvanic isolation transformer T3 type TIL3V.

A TIL3V type galvanic isolation transformer is a device that has two or more inductively coupled windings on each magnetic circuit and is designed to convert one or more voltages into one through electromagnetic induction, without changing the frequency.

The interface module includes:

The control circuit of the control system, made on the basis of the N1537ХМ1-228 microcircuit, includes:

an address register designed to receive an address via a combined address and data highway ADQ[15..0], together with control signals УCQ (5), and generate address signals RA[11..0] (6);

a data register designed to receive data via the combined address/data highway ADQ[15..0] (together with control signals УCQ) and generate data signals on the data highway XD[15..0];

a data register designed to receive data via the data highway XD[15..0] (8) (together with control signals CS) and generate address/data signals via the combined address and data highway ADQ[15..0] together with control signals УCQ, which are transmitted over a combined address and data highway;

ADQ[15..0] is a combined address and data highway that provides interaction between the control circuit of the interface module, MKIO1 and MKIO2.

The BTsVU is a high-speed computing small-sized device (height 41.5 and diameter 173 mm), in addition to its main tasks, it performs the function of a control unit and operates on the basis of special software (software) with the construction of a digital stabilization circuit and a digital method for implementing anti-bending and anti-torsion filters:

The basis of the BTsVU is the 1867VTs6F integrated circuit, which is a 32-bit digital signal processor designed to solve complex system-level problems;

all interface devices are shared and can be connected by software at any time and control the processor core;

To exchange information with external and internal subscribers, BINSU BTsVU has three multiplex information exchange channels (MKIO1, MKIO2, MKIO3) via lines LPI1, LPI2, LPI3 in accordance with GOST R 52070-2003 and GOST 18977-79. Channels MKIO1, MKIO2, MKIO3 operate simultaneously (without dividing work in time). On the LPI1, LPI2 lines the BTsVU operates in the “terminal device” mode, on the LPI3 line in the “bus controller” mode;

The BTsVU is connected to the main lines LPI1, LPI2, LPI3 through loops;

The BTsVU provides reception of one-time commands with galvanic isolation, has a register of one-time commands, a serial synchronous SPI interface for exchanging information with g and the ability to record and store data in a non-volatile PROM.

The 32-bit processor, which is the basis of the 1867 VTs6F chip, is designed to solve complex system-level problems that require a significant increase in dynamic range, high performance and the ability to process data in both fixed and floating point formats.

Thus, the BCVU includes, as a single whole, a processor module and an interface module (block).

The advantage of the digital signal processor included in the BTsVU is the presence of: two external interface ports, two serial ports and an extended interrupt system, which significantly simplifies the design of systems based on it, which contributes to the stable operation of the object during vibration under acceleration conditions and ensures the accuracy of measurement of motion parameters when vibrating under acceleration conditions.

The interface module includes:

1. The control circuit of the control system, made on the basis of the N1537ХМ1-228 microcircuit (basic matrix crystal with 3200 gate elements, voltage 5 V ±10%), includes:

an address register designed for receiving an address via a combined address and data line ADQ[15..0] (together with control signals УCQ of the interface module control circuit) and generating address signals RA[11..0];

a data register designed to receive data via the combined address and data highway ADQ[15..0] (together with control signals YCQ of the interface module control circuit) and generate data signals on the data highway XD[15..0];

a data register designed for receiving data via the XD[15..0] highway (together with the control signals of the control circuit of the processor) and generating address and data signals via the combined address and data highway ADQ[15..0] (together with the control signals УCQ interface module control circuit);

an address decoding block designed to receive an address via the address highway XA[12,2..0], decipher it and generate control signals CER (together with control signals УCQ of the control circuit of the interface module and signals CEL, CEK and CEB (together with control signals CS processor control circuit);

serial code receiver designed to receive information in accordance with GOST 18977-79 and RTM1495-75, arriving via lines In.A and In.B through galvanic isolation transformer T4 type BTI8-52 V and input driver FZ, as well as for generating a request INTERO interrupts upon completion of receiving information;

2. Block of one-time commands DBK, designed to generate output one-time commands K2 and K2_TM using the output driver F1;

3. Transmitter of the byte-multiplex channel BMK, designed to generate control signals C1, C2, ZPBU and transmit information to external subscribers via the combined address and data highway BMK [7..0] through the output driver F2;

4. Dual-port RAM DRAM;

5. Quartz resonator KR at 12 MHz;

6. Redundant multiplex information exchange channel MKIO1, operating in terminal device (OU) mode under the control of the multiplex channel terminal TMK1 on the information transmission line LPI1 and LPI2 in accordance with GOST R 52070-2003, and includes:

TMK1, made on the basis of the N1582VZh3V-0213 microcircuit (contains a frequency divider ST2) and generates an INTER87 interrupt request;

transmitting and receiving device PPU1, made on microassembly 852IN1P;

galvanic isolation transformers T1 AND T2 type TIL3V;

7. Non-redundant multiplex information exchange channel MKIO2, operating in bus controller (BC) mode under control of the terminal of the multiplex channel TMK2 to the information transmission line LPI3 in accordance with GOST R 52070-2003, and includes:

TMK2, made on the basis of the N1582VZh3V-0213 microcircuit and generating the INTER87 interrupt request;

transmitting and receiving device PPU2, made on microassembly 852IN1P;

galvanic isolation transformer T3 type TIL3V.

The integrated circuit N1582VZh3V-0213 contains a multiplex channel (TMK) and is designed to implement the functions of “controller”, “terminal device” of a multiplex information exchange channel (MKIO) in accordance with GOST 26765.52-87.

TMK implements all 10 message formats and processes all control commands.

TMK operates as part of microprocessor systems as a programmable input/output controller.

TMK is controlled using four registers, has two interrupt vectors and one direct memory access channel.

TMK consists of:

register part;

encoder;

decoder;

generation control timer;

control unit;

generator and divider block;

protocol controller;

Q-bus controller;

word counters and addresses.

Data exchange in the TMK (Integrated circuit N1582VZh3V-0213) occurs via a 16-bit bidirectional bus with 3 states, which is connected to an external system bus through buffer elements (Port).

The generation control timer ensures that the transmitter is turned off after detecting a continuous transmission lasting more than 800 μs.

The protocol controller includes a 12 µs timer, which controls the duration of the pause before issuing the OS (response word).

The Q-bus system bus controller generates a diagram of control signals in accordance with the requirements of the system bus of a microprocessor system based on the H1806VM2 microprocessor.

The microprocessor (chip) H1806VM2 is a single-chip 16-bit processor. The output clock signal CLCO has a frequency equal to the input clock frequency CLCL. The microprocessor, along with the synchronous address part of the exchange via the system bus, has the ability to operate asynchronously when transmitting addresses. System memory, in addition to special programs (start-up, resident test software, remote control terminal), allows you to expand the command system using software implementation of additional programs in it.

The Q-bus system bus controller ensures the implementation of a standard data exchange protocol on this bus. The peculiarity is the use of the AR signal, which is generated by the controller to all (“its own” and “foreign”) addresses on the system backbone. When recognizing “its own” address (addresses of all internal registers and RAM addresses), an active level is formed on AR immediately after receiving the signal. In the case of receiving a “foreign” address, the active level on the AR is formed with a delay of one period of the system bus frequency.

On the Q-bus highway, the address is transmitted synchronously (without confirmation of its receipt by the performer), and data is transmitted asynchronously, with mandatory confirmation of its issue or reception by the performer.

In addition to read and write cycles, the Q-bus also uses input-pause-output cycles.

The register portion contains an output buffer register, one shift register with input and output buffer registers, a status/response word register (RSAW), a control register (RCS), a command word register (RCM), and a diagnostic register (RDG).

All registers have access to an internal 3-state highway.

The encoder and decoder perform forward and reverse conversion of the binary sequence into a biphase code.

The processor includes:

1. Central processor CPU digital signal processing, based on the 1867VTs6F chip, which is a 32-bit processor designed to solve complex system-level problems that require a significant increase in dynamic range, high performance and the ability to process data in both fixed and fixed format. and with floating point.

Super Random Access Memory (SRAM);

frequency divider ST2;

an interface block designed to organize the exchange of information between the CPU and the interface module via parallel highways of the address XA[12..0] and data XD [15..0] and the control signal bus CS;

an interface block designed to organize the exchange of information between the CPU and RAM, EEPROM along parallel highways of address A[23..0] and data D[32..0];

2. The control circuit of the control system, made on the basis of the N1537ХМ1-227 microcircuit (a basic matrix crystal with a capacity of up to 3.2 thousand gates on KNOM structures having 62 functional pins, operates at a voltage of 4.5-5.5 V), includes :

direct memory access controller that generates control signals CRAM and CROM depending on the address value set on the address highway A[23,16..0] (from the CPU to RAM) and the address set on the address highway A[23,20, 19] (from CPU to EEPROM);

operational built-in self-monitoring scheme;

interrupt controller that generates interrupt request signals INT[3..0] for the CPU (central processor) depending on the state of the input interrupt requests INTERO, INTER87 and ZPR;

a one-time command controller that generates a control signal CRKI for reading input one-time commands;

K-bus controller (has a bidirectional 16-bit parallel interface) that generates USK control signals for K-bus subscribers and the CKRUB signal for controlling the SF bus driver when exchanging information with K-bus subscribers via a combined address and data highway AD[15.. 0];

an interface controller that generates control signals for the interface module;

3. RAM memory device, made on the basis of a 1637RU1 memory chip;

4. Electrically erasable and programmable read-only memory device EEPROM, based on the 1638PP1 chip;

5. Block of one-time commands DBK, designed to receive one-time input commands VRK [7...0] using galvanic isolation GR, input one-time commands NP (suspension code) [5...1], LCHA and VRK8.

The BTsVU as a high-speed digital computing device is small-sized (height 41.5 and diameter 173 mm) and performs the following functions:

information exchange between the processor and the interface module is carried out via a parallel interface (TMS320 bus) with separate highways for the XA and XD data addresses and the control bus US, as well as using 2 INTER interrupt request inputs;

the interface module is accessed by processor commands intended to access memory; each subscriber is represented by a corresponding number of cells in the general memory field of the on-board computer with fixed addresses;

external subscribers exchange with the BTsVU via a parallel K-bus using an external interrupt request ZPR, serial MKIO channels (multiplex information exchange channels) in accordance with GOST R 52070-2003 via information transmission lines LPI, serial code in accordance with GOST 18977-79, parallel-serial bytes - multiplex channel BMK, one-time commands: input RKI, NP, LCA and output K2, K2_TM;

in addition to performing basic functions, the BTsVU is used to organize system control and operational self-monitoring;

after power is applied, the processor conducts full self-monitoring: an extended integrated control test (ECT) with a depth of about 95%, after which control is transferred to the working program;

when entering the work program, a control task is solved, during which the sensors are interrogated and their readings are compared, and the correct generation of control signals is also checked; during these checks, the external connections of the central control unit are checked (the resulting check depth then reaches 99%), the serviceability of the sensors and the correct operation of the main circuits of the control systems; if the test results are positive, a sign of serviceability is recorded and the implementation of standard control algorithms begins; the test results are recorded in specially allocated RAM indicator cells and sent to the telemetry system.

The BTsVU is designed to exchange information with internal and external subscribers of the BINSU, as well as to receive, convert, generate, solve computational problems and issue real-time control signals and commands in accordance with specified algorithms.

List of abbreviations (with explanations) in alphabetical order:

BMK - byte multiplex channel;

DBK - block of one-time commands;

BTsVU - on-board digital computing device;

VRK - one-time input commands;

GIB - gyroinertial block;

GR - galvanic isolation;

DOSE - dual-port random access memory;

ZPR - interrupt request from GIB;

KR - quartz resonator;

KSh - bus controller;

K-bus - main parallel interface with combined address and data lines (Q-bus type) based on

GOST 26765.51-86;

LPI - information transmission line;

LFA - one-time input command “OA address parity line”;

MKIO - multiplex information exchange channel;

NP - one-time input commands “Suspension number”, with the help of which the address of the op-amp for the on-board computer is set;

RAM - random access memory;

OU - terminal device;

PPU - transceiver device;

SRAM - Super Random Access Memory;

СТ2 - frequency divider by 2;

SU - control circuit;

TMK - multiplex channel terminal;

TVK - built-in control test;

T - galvanic isolation transformer;

CS - control signals;

F - signal level shaper;

CPU - central processing unit;

EEPROM is an electrically erasable and programmable read-only memory device.

Claims (1)

An onboard digital computing device for a strapdown inertial navigation control system, including a processor, a programmable part consisting of system and functional software and algorithmic tools, a memory and input/output device, characterized in that the onboard digital computing device consists of two multilayer printed circuit boards of a processor and interface module, which is made with the processor as a single unit and is a homogeneous computing system with a set of devices such as a control circuit with an input signal conditioner, two output signal conditioners, a dual-port random access memory device, a quartz resonator, a block of one-time commands for generating output one-time commands with using one output signal conditioner, a byte-multiplex channel transmitter for transmitting control signals to external subscribers via a combined address and data highway using another output signal conditioner, and for exchanging information with external subscribers, the interface module is additionally equipped with a redundant multiplex information exchange channel over two transmission lines information, operating in terminal device mode and having a multiplex channel terminal with a frequency divider, a galvanic isolation transformer, a receiving-transmitting device and a non-redundant multiplex information exchange channel over one information transmission line, operating in bus controller mode and having a multiplex channel terminal, receiving and transmitting device and a galvanic isolation transformer, and the processor of the on-board digital computing device includes an operational built-in self-monitoring circuit, a random access memory device, an electrically erasable and programmable read-only memory device, galvanic isolation, a block of one-time commands for receiving input one-time commands, a control circuit including a direct controller memory access, which generates a control signal to the random access memory and a control signal to the electrically erasable and programmable read-only memory depending on the address value set on the address highway, and a central digital signal processing processor made on the basis of a microcircuit including a flash memory , a frequency divider and two interface blocks, one of which is designed to organize the exchange of signals along parallel address and data highways between the central processor and the interface module, and the other interface block is designed to organize the exchange of parallel address and data highways between the central processor and random access memory device and an electrically erasable and programmable read-only memory, in addition to this, the processor module includes an interrupt controller that generates interrupt request signals for the central processor depending on the state of the input interrupt requests and an external interrupt request, a one-time command controller that generates a control signal for reading input one-time commands, a system bus controller that generates control signals for subscribers of this bus and a signal for controlling the bus driver when exchanging information with system bus subscribers via a combined address and data bus, and an interface controller that generates control signals for the interface module.