RU2255416C1 - Operational amplifier - Google Patents

Abstract

FIELD: radio and communications engineering.

SUBSTANCE: proposed operational amplifier designed for amplifying broadband signals, including pulsed ones, in analog interface structures of various functional applications has input stage 1 made in the form of differential amplifiers whose output current is unlimited at input voltage fluctuations up to several volts; p-n-p transistors 8, 9; and n-p-n transistors 10, 11. Emitters of transistors 8 through 11 are connected to respective antiphase current outputs of stage 1; collectors of transistors 9, 11 are integrated and coupled with correcting capacitor 16 and with output buffer amplifier 17. Current followers 19, 18 are introduced between collectors of transistors 8, 9 and collectors of transistors 10, 11. Use of micron technologies with layout standards of 1.5 to 2 μm provides for speed growth at level of 4000 - 6000 V/μs.

EFFECT: enhanced speed.

8 cl, 11 dwg

Description

The invention relates to the field of radio engineering and communications and can be used as a device for amplifying broadband and pulse signals in the structure of analog interfaces for various functional purposes.

Known operational amplifiers (op amps) based on two parallel-connected parallel-balanced cascades, which became the basis for the construction of modern operational amplifiers, for example, AD8631, HA2539, NA5190 and others [1, 2, 4]. However, they do not have a high enough speed due to nonlinear operation modes with a large pulse signal [5, 6]. The problem of improving the performance of op-amps of this class, which are among the most broadband push-pull structures, is one of the urgent problems of modern analog microcircuitry.

The closest prototype of the claimed device is an operational amplifier [4], comprising an input stage having first and second antiphase current outputs matched to the buses of the positive power supply, first and second antiphase current outputs matched to the bus of the negative power source, first and second p-n -p transistors with integrated bases and a bias voltage E _c1 selected on them, the emitters of which are connected to the corresponding first and second current outputs of the input stage, matched with of a positive power source, the first and second n-p-n transistors with combined bases and a bias voltage E _c2 selected on them, the emitters of which are connected to the corresponding first and second antiphase current outputs of the input stage, matched to the bus of the negative power source, the second collectors pnp and npn transistors are combined and connected to a correction capacitor and an output buffer amplifier.

A significant drawback of the known op-amp is that its architecture does not allow to exclude nonlinear modes and thereby obtain the maximum values of the maximum slew rate of the output voltage (ϑ _out ) for a large signal. In addition, the known device is characterized due to asymmetry by high values of the emf zero bias and low attenuation of input common-mode signals.

The main objective of the invention is to increase performance - to obtain _output at the level of 4000-6000 V / μs using domestic micron technologies (with topological standards ≥ 1.5 ÷ 2 μm). An additional goal is to reduce the emf. zero bias and increasing the attenuation coefficient of the input common-mode signals.

This goal is achieved by the fact that in an operational amplifier containing an input stage having first and second antiphase current outputs matched with buses of a positive power source, first and second antiphase current outputs matched with a bus of a negative power source, the first and second p-n- p transistors with bases and combined them to selected bias voltage E _c1, whose emitters are connected to respective first and second current outputs of the input stage, consistent with positively bus the first power source, first and second n-p-n transistors with merged database and selected for their bias voltage E _c2 whose emitters are connected to respective first and second antiphase current outputs of the input stage outputs, matched to the bus of the negative power source, the collector of the second p -n-p and n-p-n transistors are combined and connected with a correction capacitor and an output buffer amplifier, new connections and elements are introduced - the input stage is made in the form of differential amplifiers that do not have limitations output current when the input voltage changes to several volts, between the collectors of the first and second rnp transistors, as well as the collectors of the first and second npn transistors, the first and second current repeaters are introduced, respectively, and the common node of the first current repeater is connected to the bus of the positive source power supply, and the common node of the second current follower is connected to the bus of the negative power source.

A diagram of the inventive device in accordance with claim 1 of the claims is shown in figure 1. Figure 2 shows a diagram of the op-amp, in which (claim 2, claim 3 of the claims) additional current repeaters with a dead zone of 20 and 21 are introduced, providing the transmission of large increments of the output currents of the input stage flowing through nodes 4 and 6, in the corrective capacitor 16.

Figure 3 shows a special case of the implementation of current repeaters with a deadband of 20 and 21 based on npn (20) and pnp (21) transistors located (with amplification of small signals) in the cutoff.

In the circuit of FIG. 4 (claim 6, claim 7 of the claims) new elements 22, 23, 24, 25 are introduced, which create an additional nonlinear channel for transmitting a large signal from outputs 5 and 7 to the correction capacitor 16. These communications are aimed at eliminating emerging dynamic asymmetry in the op-amp, which may occur due to uneven performance at outputs 4 and 5, as well as 6 and 7.

In the op amp circuit of Fig. 5, due to the use of common-mode current outputs 25, 26 in the input stage, the output currents of which are proportional only to the large input signal (u _{input 2.3} >> 50 mV), the transmission channels of large and small signals coincide only in the first 18 and second 19 current repeaters. Such an architecture makes it possible to create ultra-fast opamps that work equally well both in inverter mode and in pulse repeater mode.

Fig.6-Fig.8 and table 1 (Fig.10) shows specific circuits of functional units that were used in the construction of the opamp of Fig.5, and the results of their computer simulation in a Pspice environment using models of integrated transistors. In Fig.11 shows a diagram of the input stage 1, which was investigated in the proposed operational amplifier.

The operational amplifier of figure 1 contains an input stage 1, the inputs of which are nodes 2 and 3, the first (4) and second (5) antiphase current outputs of the input stage, matched with the buses of a positive power source, and the first (6) and second (7) the out-of-phase current outputs of the input stage are matched to the bus of the negative power source, i.e. may have a potential close to + E _p (-E _p ). Outputs 4 and 5 are connected to the emitters of the first 8 and second 9 pnp transistors with integrated bases and bias voltage E _c1 selected on them, and outputs 6 and 7 are connected to emitters of the first (10) and second (11) np -n transistors with integrated bases and a bias voltage E _c2 selected on them. The static mode of transistors 8-11 is set by two-terminal 12, 13, 14, 15. The collectors of the second npn (11) and pn-p (9) transistors are connected to each other and connected to a correction capacitor 16 and an output buffer amplifier 17. Between the collectors of the first 8 and the second 9 rn-n-r transistors, as well as between the collector of the first 10 and second 11 npn transistors, the first 18 and second 19 current repeaters are included, the common nodes of which are connected respectively to the buses of the positive and negative power sources. As the input stage 1, differential amplifiers are used that do not have a limitation of the output current when the input voltage changes to several volts [5, 6].

In the device of FIG. 2, corresponding to claim 2, between the emitter of the first pnp transistor 8 and the input of the first current follower 18, a first additional current follower 20 is connected with a dead zone, and between the emitter of the first npn transistor 10 and the input of the second follower current 19 included the second additional current repeater 21 with a dead zone. In the particular case, additional current repeaters 20 and 21 are made in the form of several series-connected pn junctions (diodes).

In the device of FIG. 3, corresponding to claim 4 and claim 5, the first and second additional current repeaters with a dead zone 20 and 21 are made in the form of nonlinear cascades with a common base on n-p-n (20) and p-n -r (21) transistors.

In the device of FIG. 4, corresponding to claim 6 and claim 7, the first 22 and second 23 auxiliary current repeaters are introduced, which are matched with the corresponding power buses, the emitter of the second pnp transistor 9 being connected to the input of the first auxiliary current repeater 22 through a third current repeater with a dead zone 24, the emitter of the second npn transistor 11 is connected to the input of the second 23 auxiliary current repeater through a fourth current repeater with a dead zone 25, and the output of the first auxiliary the current follower 22 is connected to the input of the second current follower 19, and the output of the second auxiliary current follower 23 is connected to the input of the first current follower 18.

In the device of FIG. 5, corresponding to claim 8, the input stage 1, in addition to low-signal outputs 4, 5 and 6, 7, has first 25 and second 26 in-phase outputs for a large signal, matched with positive (25) and negative ( 26) power sources and connected to the inputs of the first 18 and second 19 current repeater.

As an input stage 1, in accordance with the claims, cascades are used that do not have restrictions on the output current when the input voltage of the op-amp is changed to several volts [5, 6].

продолжают изменяться пропорционально u_вх.2.3, однако их значения не превышают статических уровней источников 12 и 14:

большой импульсный сигнал, когда выходные токи узлов 4 и 7

превышают статические уровни I₁₂, I₁₄:

Consider the operation of the device with a positive voltage pulse at the input Вх.1 ^(-) ОУ (Fig.1, 2) in the repeater mode with 100% feedback for the three most characteristic cases: a small pulse signal (pulse voltage between the inputs of the ОУ u _В2.3 <U _gr ≈ 50 mV), a large pulse signal (u _{input 2.3} ≥ U _gr · 50 mV, when the output currents at nodes 5 and 6 are limited, and the output currents at nodes 4 and 7

continue to vary in proportion to u in. _2.3 , however, their values do not exceed the static levels of sources 12 and 14:

large pulse signal when the output currents of nodes 4 and 7

exceed static levels I ₁₂ , I ₁₄ :

In static mode, when the voltage between nodes 2 and 3 is close to zero, the additional current followers 20 and 21 (in the particular case diodes) are closed. This state is ensured by the correct choice of voltages E _c1 and E _c2 at the bases of transistors.

и

под действием входного сигнала ОУ (напряжение между узлами 2 и 3 u_вх.2.3≤ U_гр) передаются в эмиттерные цепи транзисторов: 8 и 9, 10 и 11, и далее на выход промежуточного каскада - к корректирующему конденсатору 16, где U_гp - входное напряжение u_вx.2.3, при котором происходит ограничение выходных токов узлов 5 и 6. При этом осуществляется заряд (разряд) конденсатора 16 суммарным током, пропорциональным u_вх.2.3 (фиг.1, токи со значком “М”):Small changes in the output currents of the input stage

and

under the action of the input signal, the op-amp (voltage between nodes 2 and 3 u _{input 2.3} ≤ U _g ) is transmitted to the emitter circuit of the transistors: 8 and 9, 10 and 11, and then to the output of the intermediate stage to the correction capacitor 16, where U _gp - input voltage u _inx.2.3 , at which the output currents of nodes 5 and 6 are limited. In this case, the capacitor 16 is charged (discharged) with a total current proportional to u _in.2.3 (Fig. 1, currents with the “M” _mark ):

- крутизна преобразования малого входного напряжения u_вх.2.3 в i-й выходной ток входного каскада.Where

- the steepness of the conversion of a small input voltage u input _2.3 to the i-th output current of the input stage.

With a small signal (u _{input 2.3} <50 mV), the op-amp performance is greatest (depending on any linear system) on the amplitude of the op-amp output voltage [5, 6]. The small signal mode ends when the input voltage exceeds 50 mV (u _{input 2.3} > U _gp = 50 mV).

In the second case, when u _in.2.3 > U _gp = 50 mV, the input stage, made, for example, according to the circuit of Fig. 7 or Fig. 9, enters the current limiting mode at outputs 5 and 6 (their absolute values become close to zero) and the mode of further proportional (input signal) current increment at outputs 4 and 7:

,

- крутизны преобразования входного напряжения ОУ u_вх.2.3 в соответствующий ток.Where

,

- converting an input voltage transconductance OU u _vh.2.3 the corresponding current.

передаются в выходную цепь и заряжают корректирующий конденсатор 16 суммарным током большого сигналаThese are relatively large (compared with the static currents of outputs 4 and 7) current increments

are transferred to the output circuit and charge the correction capacitor 16 with the total current of a large signal

входного каскада 1 обеспечивается такая же пропорциональность тока заряда

что и на малом сигнале (1). Однако в этом режиме суммарный ток заряда корректирующего конденсатора 16

достигает первого ограничения при

что соответствует величине входного граничного напряжения подсхемы “входной каскад 1 - промежуточный каскад”:By selecting options

input stage 1 provides the same proportionality of the charge current

as on the small signal (1). However, in this mode, the total charge current of the correction capacitor 16

reaches the first limit when

which corresponds to the value of the input boundary voltage of the subcircuit “input stage 1 - intermediate stage”:

позволяют увеличить максимальную скорость нарастания выходного напряжения ОУ фиг.1 с величины ϑ _вых.1 до величины ϑ _вых.2>>ϑ _вых.1:Increased values

allow you to increase the maximum slew rate of the output voltage of the op-amp of Fig. 1 from the value ϑ output 1 to the value ϑ _{output 2} >> ϑ _{output 1} :

where f ₁ is the frequency of unity gain in the feedback loop of the op-amp;

U _gp - voltage limiting output currents _iout.5 , _iout.6 ;

- напряжение ограничения выходных токов

,

.

- output current limiting voltage

,

.

Moreover, in the circuit of FIG. 1, the symmetry of the charge and discharge currents of the correction capacitor 16 is preserved, which ensures the identity of transients at different polarities of the pulse input signals.

начинают превышать статические значения токов I₁₂, (I₁₄). Рассмотрим этот режим в схеме фиг.2.Amplifier structure, signal transmission channels change significantly when the output currents of the input stage

begin to exceed the static values of currents I ₁₂ , (I ₁₄ ). Consider this mode in the circuit of figure 2.

становится больше, чем ток I₁₂, то транзистор 8 запирается (потенциал эмиттера этого транзистора становится меньше, чем E_c1), открывается "диодный" повторитель тока 20, создавая новый путь прохождения большого сигнала - на вход повторителя тока 18, а затем на выход промежуточного каскада (в емкость 16). Таким образом, для этого уровня большого сигнала приращения тока

передаются в емкость 16 по каналу с минимальной "электрической длиной", включающему элементы 20 и 18. Аналогично работает и канал передачи большого сигнала на элементах 21, 19 для другой полярности u_вх.2.3. При выполнении данных условий быстродействие ОУ фиг.2 приближается к предельно возможному, характерному для линейного режима, а максимальная скорость нарастания выходного напряжения достигает значенийIf the output current of the DC

becomes larger than the current I ₁₂ , then the transistor 8 is locked (the emitter potential of this transistor becomes less than E _c1 ), the "diode" current repeater 20 opens, creating a new path for the large signal to pass through - to the input of the current repeater 18, and then to the output intermediate cascade (in tank 16). Thus, for this level of a large current increment signal

transmitted to the capacitance 16 through a channel with a minimum "electric length", including elements 20 and 18. The channel for transmitting a large signal on elements 21, 19 for a different polarity u _{input 2.3 works in the same way} . When these conditions are met, the speed of the op-amp of FIG. 2 approaches the maximum possible characteristic of the linear mode, and the maximum slew rate of the output voltage reaches values

- напряжение ограничения выходного тока

входного каскада для большого сигнала.Where

- output current limiting voltage

input stage for a large signal.

In the circuit of FIG. 3, restrictions on the magnitude of the voltage at the bases of transistors 8 and 9 are reduced, since for small signals the transistor 20 is closed. However, if the emitter potential of the transistor 8 becomes less than the potential + E _c1 , the transistor 20 enters the active mode and transmits the current difference to the input of the repeater 18

The op amp of FIG. 4 also works in a similar way, in which channels for transmitting “excess” currents from all outputs 4–7 to the output of the intermediate stage are simultaneously created.

A feature of the op-amp circuit of Fig. 5 is that the input stage (except for low-signal outputs 4, 5, 6, 7) has two outputs 25 and 26 for a large signal. An example of the construction of such input stages is given in Fig.7. In this case, a "large" signal can be fed directly to the input of current repeaters 18 and 19.

Thus, depending on the options for constructing the input stage 1, it is possible to change the composition of the functional nodes of the OS and the relationships between them, which is reflected in the multi-link claims.

The results of computer simulation in the Pspice environment of FIGS. 1 to 5 show that the inventive device has high values of the maximum slew rate of the output voltage ϑ _o ≥ 4000 V / μs and in terms of the aggregate of generalized quality indicators exceeds the best foreign analogues.

Sources of information

1. Matavkin V.V. High-speed operational amplifiers. - M .: Radio and communications, 1989. - Fig. 6.11.

2. Push-pull operational amplifier. RF patent No. 2193273 H 03 f 3/45.

3. Differential amplifier. U.S. Patent No. 4,649,352, cl. 330-261.

4. Operational amplifier circuit. US patent No. 4463319, CL. 330-261.

5. Operational amplifiers with direct connection of cascades / V.I. Anisimov, M.V. Kapitonov, N.N. Prokopenko, Yu.M. Sokolov. - L., 1979.

6. Polonnikov D.E. Operational amplifiers: principles of construction, theory, circuitry. - M., 1983. - 216 p.

Claims (8)

1. An operational amplifier comprising an input stage having first and second antiphase current outputs matched to the buses of the positive power supply, first and second antiphase current outputs matched to the bus of the negative power source, the first and second pnp transistors with combined bases and the bias voltage E _c1 selected on them, the emitters of which are connected to the corresponding first and second current outputs of the input stage, matched to the bus of the positive power supply, the first and second n- p-n-transistors with integrated bases and bias voltage E _c2 selected on them, the emitters of which are connected to the corresponding first and second antiphase current outputs of the input stage, matched to the bus of the negative power source, and the collectors of the second p-n-p- and n- pn-transistors are combined and connected with a correction capacitor and an output buffer amplifier, characterized in that the input stage is made in the form of differential amplifiers that do not have restrictions on the output current when the input voltage changes up to several volts, between the collectors of the first and second pnp transistors, as well as the collectors of the first and second npn transistors, the first and second current repeaters are introduced respectively, the common node of the first current repeater connected to the bus of the positive source power supply, and the common node of the second current follower is connected to the bus of the negative power source. 2. The device according to claim 1, characterized in that the first and second antiphase current outputs of the input stage, matched with the bus of the negative power supply, the first and second antiphase current outputs of the input stage, matched with the bus of the positive power source, provide amplification of both small and large input signal, and between the emitter of the first pnp transistor and the input of the first current repeater, the first additional current repeater with a dead zone is turned on, the emitter of the first npn transistor is connected to home repeater second additional current through the second current repeater with additional dead zone. 3. The device according to claim 2, characterized in that the first and second additional current followers with a dead zone are made in the form of pn junctions connected in series. 4. The device according to claim 2, characterized in that the first additional current follower with a dead zone is made in the form of a cascade with a common base on an n-pn transistor, the emitter of which is its input, and the collector is its output. 5. The device according to claim 2, characterized in that the second additional current follower with a dead zone is made in the form of a cascade with a common base on a pnp transistor, the emitter of which is its input, and the collector is its output. 6. The device according to claim 1, characterized in that the first auxiliary current repeater is inserted into the circuit, which is aligned with the bus of a positive power supply, the emitter of the second pnp transistor of the input stage being connected to the input of the first auxiliary current repeater through a third current repeater with a dead zone, and the output of the first auxiliary current repeater is connected to the input of the second current repeater, consistent with the bus of the negative power source. 7. The device according to claim 1, characterized in that a second auxiliary current repeater is introduced into the circuit, consistent with the bus of the negative power source, the emitter of the second npn transistor of the input stage being connected to the input of the second auxiliary current repeater through the fourth current repeater with a dead zone, and the output of the second auxiliary current repeater is connected to the input of the first current repeater, consistent with the bus of the positive power source. 8. The device according to claim 1, characterized in that the first and second antiphase current outputs of the input stage, matched with the bus of the positive power supply, the first and second antiphase current outputs of the input stage, matched with the bus of the negative power source, provide amplification of only small signals, and the input stage has first and second auxiliary common-mode current outputs for a large signal, matched with the bus of the positive and negative power supply, which are connected to respectively with the inputs of the first and second current repeaters.

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