RU2253129C2 - Target fluctuating signal generator - Google Patents

Abstract

FIELD: check-up of functioning of the devices for processing of radar information, as well as instruction and training of operators of these means in the conditions of a great number of targets moving in complex trajectories.

SUBSTANCE: the device having a control panel, storage unit, synchrosignal generator, first, second and third on-line memories, unit for formation of target relative coordinates, unit for formation of the maximum target signal intensity, first, second, third and fourth synchronizers, unit for formation of the current intensity of the target signal, digital-to-analog converter, noise generator, adder uses also a correlator, first and second detectors, first and second multiplier units, first and second random number generators, which provides for formation of amicably fluctuating and quickly fluctuating bursts of pulses reflected from the radar targets, internal noise of the receiver and synchronizing signals at the output of the radar receiver in the rate of radar functioning and with due account made for motion of the ship-carrier.

EFFECT: simulation on the screen of the radar station of the target situation corresponding to the real conditions of receiving of the bursts of radar signals reflected from the moving targets with slow and quick fluctuation of the amplitude.

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Description

The invention relates to the field of radar, and in particular to devices that generate simulated synchronization signals and signals at the input of the receiver of a surveillance radar station, containing signals from moving targets, taking into account the fluctuations of their effective reflective surfaces (EOP), as well as the noise of a receiver of a simulated radar, and is intended to test the operation of radar information processing devices, as well as training and training of operators of these tools in conditions of a large number of targets moving along complex trajectories her.

Widely known are devices that form trajectories of moving objects by known initial coordinates, start time and maneuver parameters, as well as devices for generating current polar coordinates of targets relative to the radar [1]. Also known are devices that form a packet of reflected signals from the target, taking into account its average value of the image intensifier, the distance to the target and its angular position relative to the surveillance radar, as well as the formation of the radiation pattern of a simulated radar [2].

Of the known target signal generators used to test radar information processing devices, the closest to the claimed by most essential features and achieved technical effect is the target signal generator containing a control panel, a memory unit, a unit for generating relative target coordinates (FOCC), a unit for generating the maximum signal intensity of the target (PMISC), the first, second and third random access memory (RAM), a unit for generating the current signal intensity and (FTISTS), clock generator, the first, second, third and fourth sync blocks, a digital to analog converter, an adder and a noise generator [3]. The generator selected as a prototype provides the generation of target pulses with a fixed average value of the image intensifier tube, as well as the verification of the functioning algorithms of the target detection and tracking devices, the possibility of generating signals supplied to the indicators of the radar information processing devices, but does not provide the formation of bundles of amicably fluctuating and rapidly fluctuating pulses due to a change in the instantaneous value of the target’s image tube due to its displacements relative to the center of mass and core vibration whisker, applied to LEDs radar information processing devices, it is necessary to check the operation algorithms of these devices, as well as for training operators of these agents under conditions as close to reality.

The objective of the invention is to expand the functionality of the target signal generator, which improves the quality of diagnosis of radar devices and checks the algorithms for processing radar information from the moment of detection of packets reflected from the targets of the pulses to the issuance of the current coordinates of the targets to consumers, as well as the effectiveness of training and training of radar operators, taking into account the change in the instantaneous value of the image intensifier of moving targets in the process of their movement in space relative to the overview Second radar.

The technical result consists in modeling on the screen of the radar station the target situation corresponding to the actual conditions for receiving packets reflected from moving targets of radar signals with slow and fast amplitude fluctuations.

The task is achieved by introducing into the prototype circuit blocks with their connections that ensure for a given number of goals the formation of amicably fluctuating (slow fluctuations) and rapidly fluctuating packs of reflected pulses, depending on the type and angle of goals, as well as on the interval of correlation of fluctuations.

The possibility of achieving a technical result is due to the fact that, based on theoretical premises [4], random changes in the pulse amplitude of a friendly fluctuating packet occur in accordance with the exponential distribution of the probability density (1) simultaneously for all pulses within the packet, and random changes in the pulse amplitude of a rapidly fluctuating packet occur also in accordance with the exponential law of the probability density distribution, but independently for all pulses within the burst.

- мощность центрального импульса пачки, соответствующая среднему значению эффективной площади рассеяния (ЭПР) цели.Where

- the power of the central pulse of the packet, corresponding to the average value of the effective scattering area (EPR) of the target.

Figure 1 shows the structural electrical diagram of the inventive device.

Figure 2-8 shows a timing diagram explaining the work of the GFSC.

The generator of fluctuating target signals (GFSC) contains (Fig. 1) a control panel 1 (PU), a memory unit 2, a unit 3 for generating relative coordinates of the target (FOCC), a correlator 4, a unit 5 for generating the maximum intensity of the target signal (PMISC), a first detector 6, a first multiplication unit 7, a first random number generator 8, a first random access memory 9 (first RAM), a generator, clock signals 10, a first synchronization block 11, a second synchronization block 12, a noise generator 13, a second random access memory 14 (second RAM ), block 15 forms the current signal intensity of the target (FTISC block), the second detector 16, the second multiplication block 17, the second random number generator 18, the third random access memory 19 (third RAM), the adder 20, the digital-to-analog converter 21 (DAC), the third synchronization block 22, fourth block 23 synchronization. The output of the control panel 1 is connected by an information bus to the input of the clock generator 10 and with the first input of the memory unit 2, the first output of which is connected by an information bus to the first input of the PMIS block 5 and to the input of the FOCC block 3, and the second output is connected by the information bus to the correlator input 4, the output of which is connected by the information bus to the third input of the first RAM 8 and the input of the first detector 6, the output of which is connected to the input of the first random number generator 8, the output of which is connected by the information bus to the second input th first multiplication unit 7, whose output is connected to data line to a first input of the first memory 9 and the first input data line is connected to the output unit 5 FMISTS. The output of the FOCC block 3 is connected by the information bus to the second input of the PMISC block 5 and to the second input of the first RAM 9. The first output of the first synchronization block 11 is connected by the address bus to the second input of the memory block 2 and the fifth input of the first RAM 9, and the second output is connected to the synchronization bus with the third input of memory unit 2 and with the fourth input of the first RAM 9, the third output is connected to the first input of the second synchronization unit 12, the first output of which is connected by an address bus with the sixth input of the first RAM 9 and the third input of the second RAM 14, the second output is connected on the synchronization bus with the seventh input of the first RAM 9 and with the second input of the second RAM 14. The output of the first RAM 9 is connected by the information bus to the first input of the second RAM 14, the first output of which is connected by the information bus to the first input of the FTISC block 15, the third output is connected by the address bus with the second input of the third RAM 19, and the second output is connected by an information bus to the input of the second detector 16, the output of which is connected to the input of the second random number generator 18, the output of which is connected by the information bus to the first input of the second block 17 multiplication, the output of which is connected to data line to a first input of the third RAM 19 as a first input data line is connected to the output unit 15 FTISTS. The first output of the clock generator 10 is connected to the second input of the second synchronization block 12 and to the input of the fourth synchronization block 23 and is the third output of the device, the third output of the clock generator 10 is connected by the information bus to the second input of the FTISC block and is the first output of the device, and the second output is connected to the input of the third synchronization unit 22, the first output of which is connected by the address bus to the fourth input of the second RAM 14, and the second output is connected by the synchronization bus to the fifth input of the second RAM 14 and with the third input of the third RAM 19, the fourth input of which is connected by the address bus to the first output of the fourth synchronization block 23, and the output is connected by the information bus to the input of the DAC 21, the output of which is connected to the second input of the adder 20, the first input of which is connected to the output of the noise generator 13, output which is the second output of the device.

The device as a whole can be implemented by using computer technology, together with digital-to-analog circuits based on well-known radio elements. Control panel 1, memory block 2, block 3 FOCC, block 5 PMISC, clock generator 10, first synchronization block 11, second synchronization block 12, block FTISC 14, third RAM 19, noise generator 13, adder 20, DAC 21, third block 22 synchronization, the fourth block 23 synchronization, similar to the blocks of the prototype. The first RAM 9 and the second RAM 14 differ from the prototype in the ability to write the index value and then read it.

The introduction of a correlator, a first and second detector, a first and second random number generator, a first and a second multiplier into the composition of the HFCS makes it possible to form together fluctuating and rapidly fluctuating bursts of reflected pulses from targets at the output of the radar at the output of the radar receiver.

The device operates as follows. Preparation for the work of the SSCF consists in the fact that from the control panel 1, which can be implemented using the control panel of the surveillance radar and the computer keyboard, its number, type of target, initial coordinates of the moments of start and parameters of maneuvers, as well as initial coordinates are set for each target the moments of the beginning and the maneuver parameters of the carrier ship of the simulated radar. This information is entered from the computer keyboard both before the start and during the work of the GFSC. Also, in the process of working with the control panel of the survey radar, information is entered on the operating modes of the simulated radar and on changing the operating mode. All this information is transmitted via the information bus to the memory unit 2 in the form of a binary code. The recording address of this information for each purpose is its number. In block 2 of the memory, which is a long-term storage device, in addition to the information specified in the prototype information is stored data on the correlation intervals for each type of simulated target, depending on their angles. It can be implemented, for example, on the basis of a computer's hard drive and memory registers.

Timing diagrams of the work of GFSC are presented in figure 2.

The clock generator 10 generates on the first output (Fig.2A) pulses of the forward sweep (IIN), on the second output (Fig.2b) - pulses of the reverse sweep (INOX), and on the third output - the codes of the current bearing and elevation angle MDNA radar station. The period of the IINR and INOX (T _and ), their temporal arrangement (t _pc is the forward travel time and t _ox is the reverse travel time), as well as the sequence of changing the bearing codes and the elevation angle of the maximum antenna radiation pattern (MDNA) is determined by the mode of operation of the simulated radar station (radar), set from the remote control 1. To implement block 10, in terms of modeling bearing codes and antenna elevation angle (maximum radiation pattern), separate devices of the corresponding antenna post can be used. Blocks of radar synchronizers or circuits assembled and operating according to the same principles and in their parameters corresponding to the simulated radar can be used as an IINR and INOX generator.

The first synchronization unit 11, independently of the clock generator 10, generates a sequence of instructions for the calculation and recording cycle of information in the first RAM 9 (Fig. 2c), which ends, during the time t _j1 on the address bus (first output) and the synchronization bus (second output) the formation at the third output of the pulse of the end of the recording in the first RAM 9 (Fig.2g), supplied to the first input of the second block 11 synchronization. Timing diagrams of the cycle of calculation and recording information in the first RAM 9 are shown in figure 3. The repetition period of this cycle - the calculation period T _p is determined by the time the target moves, moving at maximum speed V _max by the magnitude of the resolving power of the simulated radar station in range Δ d in accordance with expression (2):

The duration of the cycle of calculation and recording information in the first RAM 9 is determined by the ratio:

The second block 12 the synchronization of the first INPH (second input) after the arrival of a pulse in the first memory 9 (the first entry) end of the record forms for a time t _tsz2 on the address bus (first output) and bus synchronization (second output), the sequence instruction loop information rewriting of the first RAM 9 to the second RAM 14 (fig.2d). Timing diagrams of this cycle are shown in figure 4. The duration t _ts2 is determined by the ratio:

The third synchronization unit 22 for each input-output I / O converter generates a sequence of instructions for the cycle of rewriting information from the second RAM 14 to the third RAM 19 (Fig. 2e) over the address bus (first output) and the synchronization bus (second output) for a time t _u3 . Timing diagrams of this cycle are shown in Fig.6. The duration t _ts3 is determined by the ratio:

The fourth synchronization block 23 for each SIP input at its input generates a sequence of instructions for the cycle of reading information from the third RAM 19 (Fig. 2g) on the address bus (first output) and the synchronization bus (second output) during time t _cc3 . Timing diagrams of this cycle are shown in figure 5. The duration t _cs3 is determined by the ratio:

Block 11, the first synchronization block is a conventional oscillator, which can be implemented on well-known schemes. Blocks 12, 22 and 23, respectively, the second, third and fourth synchronization blocks, are ordinary waiting blocking generators, which can also be implemented on well-known circuits.

The use of three RAMs in the device is due to the need to synchronize two independent and different processes: calculating the relative coordinates of the targets and the values of the maximum intensity of the fluctuating reflected signals from these targets at the receiver output at the rate of operation of the simulated radar of the carrier ship. After the calculation of the data is completed, they are immediately written to the first RAM 9, and the calculation of data and writing to RAM may take several cycles of the forward sweep. The second RAM 14 solves the problem of storing data between calculations and providing data to the FTISC block 15 and the second detector block 16, and the information in the second RAM 14 is updated only during the forward sweep period, when the simulation of the signals reflected from the targets at the output of the ship’s radar receiver the carrier is carried out according to the third RAM 19. The third RAM 19 solves the problem of modeling the signals reflected from the targets at the rate of operation of the radar of the carrier vessel, and the information in the third RAM 19 is updated during the processing the same sweep course when no signals reflected from targets are simulated.

The cycle of calculation and recording of information in the first RAM 9 (see diagrams of Fig. 3) consists of the calculation intervals in the block 3 FOCC relative coordinates, the comparison operation in the correlator 4, in block 5 of the PMISC maximum signal intensity, the operation of the first detector 6 at the assigned index for synchronization of the first random number generator 8, execution of the multiplication operation in the first block 7, the multiplication operations are performed at the output of the PMISC block 5 and the coefficient at the output of the first random number generator 8, for each of the N simulated signals th, writing the obtained values and index values to the first RAM 9. In correlator 4, the operation compares the correlation interval (τ ₀ ) received from the memory unit for the irradiated target, depending on its angle with the values: pulse repetition period (T _and ), time target exposure (τ _reg ) and the period of the radar survey (T ₀ ). After comparison, the output of correlator 4 gives a decision on whether the input quantity belongs to the interval τ _reg <τ ₀ <T ₀ or τ ₀ ≈ T _and in the form of an index that allows the detectors (blocks 6 and 16) to respond to the threshold index value set in them. Correlator 4 can be implemented, for example, on a chip type 1533SP1 and matching circuits (circuit I).

Block 3 FOCC real-time calculates the current coordinates of the targets relative to the carrier ship of the surveillance radar, which we simulate. At the preparation stage, from the memory block 2, the initial coordinates of the target (bearing, distance, elevation angle) and its motion elements (course, speed), as well as the motion parameters of the carrier of the simulated radar (course and speed), which at Necessities can be changed directly during operation. The functions of block 3 FOCC can be performed by a special processor or computer. The address of the selection of the source data from the memory unit 2 for calculation and recording in the first RAM 9 of the calculated values of the relative coordinates, the maximum signal intensity and the correlation interval is the number of the simulated target.

The relative coordinates of the targets - range, bearing, elevation angle, calculated in block 3 of the FOCC based on the incoming data, to its input via the information bus from block 2 of the data on the initial coordinates, start time and characteristics of the target maneuver and the maneuver carrier of the modulated radar station and are received the second input of the first RAM 9. Moreover, if the current time is less than the start time of the maneuver, then the calculations use the course and speed of the target, or entered from the control panel 1, and if the current time is equal to the start time of the maneuver Vera purpose or carrier, for the calculation of the next target location using course and speed of maneuver. The maximum intensity of the target signal corresponding to the amplitude of the video signal of the central pulse of the burst of signals reflected from this target is calculated in block 5 of the Federal Center for Physics and Technology on the basis of the data received on its first input via the information bus from memory block 2 on the technical characteristics of the simulated radar (operation and transmitter power) and the type of target, as well as the calculated values of the ranges to the target and the radio horizon D _rg , determined by the formula, arriving at its second input via the information bus from block 3 FOCC:

where n _a is the height of the antenna of the simulated radar on the carrier vessel;

H _u - height of the aircraft or the target height add-surface target.

The calculated value from the output of the 5th Physical and Information Center on the information bus goes to the first input of the first block 7 of multiplication, where it is multiplied by the coefficient received at its second input from the output of the first generator 8 random numbers, the value of which if the established correlation of the index with the index matches the input of the first detector 6, varies from zero to unity according to the exponential law of the probability distribution (1). This allows you to change the maximum intensity of the target in the interests of the subsequent formation of a harmoniously fluctuating burst of pulses reflected from the targets. If the established correlation of the index does not coincide with the index value at the input of the first detector 6, the coefficient value at the output of the first random number generator 8 will be constantly equal to unity, which allows us not to interfere in the formation of a rapidly fluctuating packet of signals reflected from targets. The obtained value from the output of the first block 7 multiplication via the information bus goes to the first input of the first RAM 9. The first block 7 multiplication just like the second block 16 multiplication can be implemented on the basis of the chip K556PT7A.

The calculated values of the range, bearing, elevation angle and maximum signal intensity, as well as the values of the correlation interval of the target are recorded in the first RAM 9 with the arrival of the synchronization signal from the first synchronization unit 11 to its fourth input, at the address corresponding to the target number and received at the fifth input of the first RAM 9. Upon completion of recording the calculated data for the last of N simulated targets, the first synchronization unit 11 generates at the third output a pulse of the write end to the first RAM 9, which is fed to the first input of the second block 12 synchronization and puts it in standby mode for the formation of the commands of the cycle of rewriting information from the first RAM 9 to the second RAM 14.

The cycle of overwriting information from the first RAM 9 to the second RAM 14 starts when the second IINR synchronizes to the second input of the second synchronization block 12, after this block is alerted by the start pulse from the third output of the first synchronization block 11, and consists of intervals (see diagrams of FIG. 4) reading information from the first RAM 9 and writing information to the second RAM 14 for each of the N simulated target signals. The address of reading and writing information of the first RAM 9 and the second RAM 14 is the number of the simulated target.

The cycle of rewriting information from the second RAM 14 to the third RAM 19 begins with the arrival of the input of the third synchronization block 22 of each INOX and consists of the intervals (see diagrams of Fig. 6) of calculation in block 15 FTISC for each of the N simulated signals of targets of current intensity, response of the second detector 16 by the set value of the correlation index of the correlator 4 for synchronizing the operation of the second random number generator 18, as well as performing the multiplication operation in the second multiplication block 17 of the value obtained from the output of the FTISC block 15 by ffitsient generated second random number generator 18 and writing the calculated values into the third RAM 19. Blocks 9, 14 and 19, respectively, the first RAM, the second RAM and the third memory may be implemented on the well-known elements of the large-capacity SRAM and performance, e.g., K556RU17. A feature of these RAMs is that the same microcircuit pins in different modes perform different functions, for example, in the recording mode the information pins are the input, and in the read mode the output.

The current intensity of the target signal corresponding to the amplitude of the video signal of the next pulse of the burst reflected from the target signal is calculated in block 15 FTISC on the basis of incoming to the first RAM from the second RAM 14 bearing codes, elevation angle and maximum intensity of the target signal, and on the second input from the generator 10 clock signals codes bearing and elevation angle MDNA. Thus, in block 15 FTISC modulation of the packet of signals reflected from the target by the shape of the antenna pattern takes into account the attenuation coefficients introduced by the deviation of the target location from the maximum of the main lobe of the bottom of the bottom. In the second block 17 of multiplication, when the second detector 16 is activated by the set value of the correlation index, each pulse of a packet of pulses reflected from the target is modulated by coefficients calculated by the second random number generator 18 according to the exponential law of probability distribution (1), which allows you to simulate a rapidly fluctuating packet of reflected from the target signals. The second detector 16 as well as the first detector 6 can be implemented on the basis of well-known circuits of amplifier-limiters, built, for example, on a chip type KR140UD1208 and analog-to-digital Converter. In the case of a mismatch between the index at the input of the detector 16 with the set value, the coefficient value equal to unity is constantly supplied to the second input of the second multiplication block 16 from the second random number generator 18, which allows not to influence the formation of a friendly fluctuating packet reflected from the target signals.

The first random number generator 8 and the second random number generator 18 can be constructed, for example, on the basis of a normally distributed random number generator and an analog-to-digital converter.

The address of the selection from the second RAM 14 of the source data for the calculation is the number of the simulated target. The write address in the third RAM 19 of the calculated values of the current intensity of the target signal is the distance to this target, read from the third output of the second RAM 14 and supplied via the address bus to the second input of the third RAM 19.

The cycle of reading information of the third RAM 19 begins with the arrival at the input of the fourth synchronization block 23 of each IINP and consists of the intervals (see diagrams of FIG. 5) for reading information from the third RAM 19 and zeroing the corresponding cell of the third RAM 19 for each range sample. The size of each range discrete is equal to the range resolution of the simulated radar. The address for reading and zeroing the cells of the third RAM 19 is the range discrete number, selected sequentially from the interval from 1 to m, where m is the total number of range discrete, determined by the ratio:

where D _max - the maximum size of the radar field of view in range;

t _px — time of the forward sweep;

C is the speed of propagation of electromagnetic waves in air.

When reading information about the amplitude of the video signals, with a delay relative to the IINR, corresponding to the number of the selected range discrete, it comes from the output of the third RAM 19 via the information bus to the input of the DAC 21, where it is converted into an analog signal. Zeroing the cells of the third RAM 19 is carried out to prepare it for the next cycle of rewriting information from the second RAM 14.

Clearly the formation of packs of amicably fluctuating and rapidly fluctuating pulses when writing and reading the third RAM 19 is shown in Figs. 7 and 8, respectively.

The device provides the formation of the number of target signals, determined by the ratio of the speed of its blocks and time t _px , t _ox , T _and , T _p , which for modern survey radar stations, computer equipment and radio elements is from tens to several hundred microseconds.

The synchronization of the process of calculating the relative coordinates of a large number of targets, the maximum intensity of the target signals with the formation of signals reflected from the targets at the output of the simulated radar receiver is achieved by the presence of the first synchronization block 11, the second synchronization block 12, the first RAM 9 and the second RAM 14 as a part of the HFCS.

The possibility of generating fluctuating signals reflected from the target at the pace of operation of the simulated radar station, including from targets located in one direction, is ensured by the presence of the third synchronization block 22, the fourth synchronization block 23 and the third RAM 19 as part of the GFSC information is read from the second RAM 14 at the address corresponding to the target number, and information is recorded in the third RAM 19 at the address corresponding to the range to the target. DAC 21 in the case of a digital sequence appearing at its input, for example: 039, converts it into an analog signal with a certain duration and amplitude, which will correspond to this number.

An analog signal from the output of the DAC 21, corresponding to the video signals of the pulses reflected from the targets, received and processed by the receiving path of the simulated radar station, is fed to the second input of the adder 18, where it is added to the signal of the noise generator 13 fed to the first input of the adder. The noise generator generates a video signal similar to the noise of the receiver of a simulated radar.

As a result of the addition at the output of the adder 20, which is the second output of the HFCS, a video signal is obtained that is similar to the video signal of a simulated radar when targets are detected within the visibility range. The first output to the SSCF receives signals of the angular position of the MDNA, and the third output receives the IITX. When signals are sent from the outputs of the GFSC to the inputs of radar information processing devices, a complete imitation of the functioning of the survey radar station is provided, which allows checking these devices and their operation algorithms, as well as training and training for operators operating these radar tools.

Sources of information

1. Kuzmin S.Z. Basics of designing digital processing systems. - M.: Radio and Communications, 1986, p.133-136.

2. US patent No. 5870055, cl. G 01 S 7/40, 1999, Tracking radar signal generator.

3. RF certificate for utility model No. 11348, IPC 6 G 01 S 7/40, 1999. Target signal generator (prototype).

4. V.E. Dulevich. Theoretical foundations of radar. Moscow: “Soviet Radio”, 1978

Claims (1)

A fluctuating signal generator comprising a control panel, a memory unit, a clock generator, a relative target coordinate generating unit (FOCC unit), a maximum target signal generating unit (PMISC unit), a first synchronization unit, a second synchronization unit, a first random access memory (first RAM ), a second random access memory (second RAM), a unit for generating the current signal strength of the target (FTISC block), a third synchronization block, a fourth synchronization block, and a third but a storage device (third RAM), a digital-to-analog converter (DAC), a noise generator, an adder, characterized in that a correlator, a first detector, a first random number generator, a first multiplication block, a second detector, a second random number generator, a second block are introduced multiplication, and the control panel is connected by an information bus to the input of the clock generator and with the first input of the memory block, the first output of which is connected by the information bus to the input of the FOCC unit and to the first input of the PMISC unit, and the second output to a single information bus with a correlator input, the output of which is connected by a data bus to the third input of the first RAM and the input of the first detector, the output of which is connected to the input of the first random number generator, the output of which is connected by the information bus to the second input of the first multiplication block, the first input of which is connected by the information bus to the output of the FPIC unit, and the output is connected by an information bus to the first input of the first RAM, the output of the FOCC unit is connected by an information bus to the second input of the FPIC unit and to the second input the house of the first RAM, the first output of the first synchronization block is connected by an address bus with the second input of the memory block and the fifth input of the first RAM, the second output is connected by the synchronization bus with the third input of the memory block and with the fourth input of the first RAM, and the third output is connected with the first input of the second synchronization block the first output of which is connected by an address bus with the sixth input of the first RAM and the third input of the second RAM, the second output is connected by a synchronization bus with the seventh input of the first RAM and with the second input of the second RAM, the output of the first RAM is connected inen information bus with the first input of the second RAM, the first output of which is connected by the information bus to the first input of the FTISC block, the output of which is connected by the information bus to the first input of the second multiplication block, the third output of the second RAM is connected by the address bus to the second input of the third RAM, and the second output is connected the information bus with the input of the second detector, the output of which is connected to the input of the second random number generator, the output of which is connected by the information bus with the second input of the second multiplication block, the output is It is connected by an information bus to the first input of the third RAM, the first output of the clock generator is connected to the second input of the second synchronization block and to the input of the fourth synchronization block and is the third output of the device, the third output of the clock generator is connected by the information bus to the second input of the FTISC block and is the first output of the device and the second output is connected to the input of the third synchronization unit, the first output of which is connected by the address bus to the fourth input of the second RAM, the second output is connected synchronization bus with the fifth input of the second RAM and with the third input of the third RAM, the output of which is connected by an information bus to the input of the DAC, the output of which is connected to the second input of the adder, the first output of the fourth synchronization unit is connected by the address bus to the fourth input of the third RAM, and the second output is connected by a bus synchronization with the fifth input of the third RAM, the output of the noise generator is connected to the first input of the adder, the output of which is the second output of the device.

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