RU11348U1 - TARGET SIGNAL GENERATOR - Google Patents

Abstract

A target signal generator comprising a control panel and a clock generator connected in series, the output of which is the first output of the device, a unit for generating relative coordinates of the integer (FOCC block), a unit for generating the maximum intensity of the target signals (block FMISC), a unit for generating the current intensity of the target signals (block FTISC ) and a noise generator and an adder connected in series, the output of which is the second output of the device, characterized in that a memory unit, three operational laminating devices (RAM), four synchronization units and a digital-to-analog converter (DAC), while the first input of the memory unit is connected by the information bus to the output of the control panel, the output of the memory unit is connected by the information bus to the first input of the FMISC unit and to the input of the FOCC unit, the output of which is connected the information bus with the second input of the block PMISC and with the second input of the first RAM, the first input of which is connected to the output of the block PMISC, the first output of the first synchronization block is connected by the address bus to the second input of the memory block and the fourth input of the first RAM, the second output is connected to the third input of the first RAM by the synchronization bus with the third input of the memory block, and the third output is connected to the first input of the second synchronization block, the first output of which is connected by the address bus to the fifth input of the first RAM and to the third input of the second RAM, the second output is connected by a synchronization bus with the sixth input of the first RAM and with the second input of the second RAM, the output of the first RAM is connected by an information bus to the first input of the second RAM, the first output of which is connected by the information bus from the first

Description

Target Signal Generator

The utility model relates to the field of radar, and in particular to signal generation devices that simulate synchronization signals and signals at the output of the receiver of a surveillance radar station (radar), containing signals reflected from moving targets, and the receiver noise, and is intended to provide verification of the operation of radar processing devices information, as well as training and training of operators of these tools in the face of a large number of goals moving along complex trajectories.

Widely known are devices for forming trajectories of moving targets and a radar carrier by known initial coordinates, start time and maneuver parameters, as well as generating the current polar coordinates of targets relative to radar 1. Also known are devices for generating a packet of reflected target signals that take into account the effective reflective surface ( Image intensifier) of the target, the distance to the target, its angular position and the shape of the radiation pattern of the radar 2.

Of the known target signal generators used to verify radar information processing devices, the target generator including the control panel, clock generator, noise generator and adder 3 is the closest to the claimed for most essential features and achieved technical effect device. The device selected as a prototype provides verification of only algorithms and target tracking devices, but does not provide verification of algorithms and signal detection devices, selection of marks A drawstring trajectories in the gates of the detection and selection markers for the continuation of support trajectories in the gates, and does not provide the opportunity for training operators of these funds. This is due to the fact that this device does not allow

generate signals of a large number of targets at the pace of operation of a simulated radar.

The objective of the utility model is to expand the functionality of the target signal generator, which provides a complete check of devices and algorithms for processing radar information from detecting bursts of pulses reflected from targets to outputting current coordinates of targets to consumers, as well as training and training of operators of these tools.

This problem is solved in that a target signal generator comprising a control panel, a clock generator, a relative target coordinate generation unit, a target signal maximum intensity generating unit, a target signal intensity generating unit, a noise generator and an adder, a memory unit, three operational memories are introduced devices, four synchronization units and a digital-to-analog converter. The introduction of these blocks with their connections ensures the formation at the pace of operation of the simulated radar synchronization signals and the angular position of the maximum antenna radiation pattern (MDNA), as well as video signals reflected from the targets of the pulse trains, modulated in amplitude by the shape of the antenna radiation pattern, against the background of noisy noise. This ensures the formation of video signals reflected from a given number of targets moving along specified arbitrary paths, including those located in the same direction.

In FIG. 1 shows a structural electrical diagram of the inventive device. In FIG. 2 shows timing diagrams of the functioning of the device as a whole, in FIG. 3,4, 5 and 6 are timing diagrams of the operation of the device in separate cycles.

The target signal generator comprises a control panel 1, a memory unit 2, a unit 3 for generating relative coordinates of the target (FOCC unit 3), a unit 4 for generating maximum intensity of the target signals (unit 4 of the FMISC), the first operational

a storage device 5 (first RAM 5), a clock generator 6, a first synchronization unit 7, a second synchronization unit 8, a noise generator 9, a second random access memory 10 (second RAM 10), a unit 11 for generating a current target signal intensity (FTISC unit 11) , a third random access memory 12 (third RAM 12), an adder 13, a digital-to-analog converter 14 (DAC 14), a third synchronization block 15, a fourth synchronization block 16, while the output of the control panel 1 is connected to the input of the sync generator 6 by the information bus and with the first input of the memory block 2, the output of which is connected by the information bus to the first input of the FPIC block 4 and with the input of the FOCC block 3, the output of which is connected by the information bus with the second input of the PMIS block 4 and with the second input of the first RAM 5, the first input of which is connected to the output of block 4 of the PMISC. The first output of the first synchronization unit 7 is connected by the address bus with the second input of the memory unit 2 and with the fourth input of the first RAM 5, and the second output is connected by the synchronization bus with the third input of the memory unit 2 and with the third input of the first RAM 5, the third output is connected with the first input of the second block 8 synchronization, the first output of which is connected by an address bus with the fifth input of the first RAM 5 and with the third input of the second RAM 10, the second output is connected by a synchronization bus with the sixth input of the first RAM 5 and with the second input of the second RAM 10. The output of the first RAM 5 is connected An information bus is connected to the first input of the second RAM 10, the first output of which is connected by the information bus to the first input of the FTISC block 11, and the second output is connected by the address bus to the third input of the third RAM 12. The second input of the FTISC block 11 is connected by the information bus to the third output of the clock generator 6 , which is the third output of the device, and the output is connected by an information bus to the first input of the third RAM 12. The first output of the clock generator 6 is connected to the second input of the second synchronization unit 8, with the input of the quad about block 16 synchronization is the first output of the device, and the second output is connected to the input of the third block 15

synchronization, the first output of which is connected by the address bus with the fourth input of the second RAM 10, and the second output is connected by the synchronization bus with the fifth input of the second RAM 10 and with the second input of the third RAM 12, the fourth input of which is connected by the address bus to the first output of the fourth synchronization block 16, the fifth the input is connected by a synchronization bus to the second output of the fourth synchronization block 16, and the output is connected by an information panel to the input of the DAC 14, the output of which is connected to the second input of the adder 13, the first input of which is connected to the output noise generator 9, and the output is the second output of the device.

The device as a whole can be implemented on the basis of computer technology in conjunction with the well-known digital-to-analog microcircuits. The noise generator 9 and the adder 13 are similar to the blocks of the prototype. Remote control 1 differs from the corresponding block of the prototype the ability to enter additional information about the coordinates and characteristics of targets and carrier radar. The clock generator 6 differs from the corresponding prototype unit by the presence of the second and third additional outputs. At the second output, an impulse of the beginning of the reverse course of the sweep (INOX) of the simulated radar is formed. The temporary location of the sky-signal generated at the first output and which is the pulse of the beginning of the forward sweep (IIN), and INOCH are shown in Fig. 2, pos. a, b. At the third output, the bearing and elevation angle codes of the MDNA are generated in accordance with the scanning program adopted in the simulated radar. Block 3 FOCC operates on the basis of well-known algorithms 1, and block 4 of the Center for Physics and Technology and block 11 of the FTISC operates on the basis of well-known algorithms 2.

The device operates as follows. Preparation for work consists in assigning, from the control panel 1, for each target its number, the value of the average image intensifier, the initial coordinates, the moments of start and parameters of maneuvers, as well as the initial coordinates, the moments of beginning and parameters of maneuvers of the carrier of the simulated radar. This information is entered both before and during the operation of the device. also in

the process of entering information about the mode of operation of the simulated radar and about changing the mode of operation.

In block 2 of the memory, in addition to the specified information, data is stored on the technical characteristics of the simulated radar, which determine the detection range of targets in various operating modes.

Timing diagrams of the operation of the device are shown in FIG. 2.

The clock generator 6 generates the IINR (first output) (Fig. 2, pos. A), INOCH (second output) (Fig. 2, pos. B), as well as the codes of the current bearing and elevation angle of the radar detector (third output). The period of repetition of IINR and INOCH (Ti), their temporal arrangement (tnx is the forward travel time and tox is the reverse travel time), as well as the sequence of changing the bearing codes and the elevation angle of the MDNA, are determined by the mode of operation of the simulated radar set from the control panel 1.

The first synchronization unit 7, regardless of the clock generator 6, generates a sequence of commands of the cycle of calculation and data writing to the first RAM 5 (Fig. 2, item c) for the time ti on the address bus (first output) and the synchronization bus (second output) , which ends with the formation at the third output of the pulse of the end of the recording in the first RAM (Fig. 2, pos. g) supplied to the first input of the second synchronization unit 8. Timing diagrams of the cycle of computing and writing data to the first RAM 5 are shown in Fig.Z. The repetition period of this cycle - the calculation period Tp, is determined by the time of moving the target moving at maximum speed Ux, by the value of the resolving ability of the simulated radar in range Ad in accordance with the expression

The duration of the cycle of computing and writing data to the first RAM 5 is determined by the ratio

Tp Ad / Vn, ax.

The second synchronization unit 8 according to the first IINR (second input) after the arrival of the write end pulse to the first RAM 5 (first input) generates a sequence of instructions for overwriting the data from the first one on the address bus (first output) and the synchronization bus (second output) during 1vd2 time RAM 5 to the second RAM 10 (Fig. 2, pos. E). Timing diagrams of this cycle are shown in figure 4. The duration of 1sz2 is determined by the ratio

The third synchronization block 15 for each INOX coming to its input generates a sequence of instructions for the data rewrite cycle from the second RAM 10 to the third RAM 12 (Fig. 2, pos. e). Timing diagrams of this cycle are shown in FIG. 5. The duration is determined by the ratio

The fourth synchronization block 16 for each PfflTIX incoming to its input generates a sequence of instructions for a cycle of reading data from the third RAM 12 (Fig. 2, pos. G) on the address bus (first output) and the synchronization bus (second output) during 1 time. Timing diagrams of this cycle are shown in FIG. 6. The duration of 1cc is determined by the ratio

The cycle of calculating and writing data to the first RAM 5 (see diagrams in FIG. 3) consists of the calculation intervals in block 3 of the FSLF of the values of the relative coordinates and in block 4 of the FMISC of the values of the maximum signal intensity for each of the N simulated targets and writing the calculated values to the first RAM 5. The address of the selection of the source data for calculating from the memory unit 2 and recording the calculated values of the relative coordinates and the maximum signal intensity in the first RAM 5 is the number of the simulated target. The relative coordinates of the targets - range, bearing, elevation angle, are calculated in block 3 FOCC based on arriving at its input via the information bus from block 2 memory

1sz2 1pkh

1szz tox

1cc s tnx

data on the initial coordinates, the start time and the characteristics of the maneuvers of the target and the carrier of the simulated radar and are fed to the second input of the first RAM 5. The value of the maximum signal intensity of the target, corresponding to the amplitude of the video signal of the central pulse of the packet reflected from the target, is calculated in block 4 of the FMISC based on its first input on the information bus from block 2 of the data memory on the technical characteristics of the simulated radar, the value of the average target intensifier tube and arriving at its second input on the information from the block 3 FOCC range to the target. When forming the value of the maximum intensity of the target signal, the nature of the fluctuation of the target image intensifier and the radio horizon are taken into account. The calculated value from the output of block 4 of the Federal Center for Physics and Information Technology via the information bus goes to the first input of the first RAM 5. The values of the range, bearing, elevation angle and maximum intensity of the target signal are written to the first RAM 5 by the synchronization signals received at its third input, at the address corresponding to the number the target arriving at the fourth input of the first RAM 5. Upon completion of data recording for the last of N simulated targets, the first synchronization unit 7 generates at the third output a pulse of the end of recording in the first RAM, which is fed to the first input 8 g of the second block synchronization and converts it to the ready mode to the formation instruction data from the first cycle rewriting the RAM 5 into the second RAM 10.

The cycle of overwriting data from the first RAM 5 to the second RAM 10 begins with the arrival of the second IINR synchronization block 8 at the second input after alerting this block and consists of the intervals (see diagrams of Fig. 4) for reading data from the first RAM 5 and writing data in the second RAM 10 for each of the N simulated targets. The address of reading and writing data of the first RAM 5 and the second RAM 10 is the number of the simulated target.

The cycle of overwriting data from the second RAM 10 to the third RAM 12 begins with the arrival of the third block 15 of each INOX at the input of the third block 15 and consists of the intervals (see the diagram of Fig. 5) of the calculation in block 11 of the FTISC for each of the N modeled

goals, the values of the current signal intensity of the target and their recording in the third RAM 12. The value of the current signal intensity of the target, corresponding to the amplitude of the video signal of the next pulse of a packet of signals reflected from the target, is calculated in block 11 FTISC on the basis of the data received at its first input from the second RAM 10 values of the maximum intensity of the signal, bearing and elevation angle of the target, and received on its second input via the information bus from the generator 6 clock signals of the bearing and elevation angle MDNA. In block 11 FTISC, thus, modulation is carried out by the amplitude of the packet of signals reflected from the target by the shape of the antenna pattern. The address of the selection from the second RAM 10 of the source data is the number of the simulated target. The write address in the third RAM 12 of the values of the current signal intensity of the target is the distance to this target, read from the second output of the second RAM 10 and supplied via the address bus to the third input of the third RAM 12.

The data reading cycle of the third RAM 12 begins with the arrival of the fourth synchronization block 16 of each IINC at the input and consists of the intervals (see the diagram of Fig. 6) for reading information from the third RAM 12 and zeroing the corresponding cell of the third RAM 12 for each range discret. The sizes of each range discrete are equal to the range resolution of the simulated radar. The address for reading and zeroing the cells of the third RAM 12 is the number of the range discrete, selected sequentially from the interval from 1 to t, where m is the total number of range discreet, determined by the ratio

where Dmax is the size of the radar field of view in range;

j max ph

Ad 2ad

When reading data on the amplitude of the video signals with a delay relative to the IINR corresponding to the number of the selected range discrete, they come from the output of the third RAM 12 via the information bus to the input of the DAC 14, where they are converted into an analog signal. Zeroing the cells of the third RAM 12 is carried out to prepare it for the next cycle of overwriting data from the second RAM 10.

The device provides the formation of the number of targets, determined by the ratio of the speed of its blocks and time tnx, W, TH, Tr, which for modern surveillance radars, computer equipment and radio elements ranges from tens to several hundred.

The synchronization of the process of calculating the values of the relative coordinates of a large number of targets and the values of the maximum intensity of the target signals with the process of generating signals reflected from the targets at the receiver output of the simulated radar is achieved by the presence of a memory unit 2, a first synchronization block 7, a second synchronization block 8, a first RAM 5 and second RAM 10.

The ability to generate reflected signals at the pace of operation of the simulated radar, including from targets located in one direction, is provided by the presence of a third synchronization block 15, a fourth synchronization block 16, and a third RAM 12 as part of the device, as well as the fact that data is read from the second RAM 10 is carried out at the address corresponding to the target number, and data is recorded in the third RAM 12 at the address corresponding to the range to the target.

The analog signal from the output of the DAC 14, corresponding to the video signals of the pulses of the simulated radar reflected from the targets, is fed to the second input of the adder 13, where it is added to the signal of the generator 9 of the noise input to the first input of the adder. The noise generator generates a video signal similar to the noise of the receiver of a simulated radar. As a result of addition at the output of the adder

13, which is the second output of the device, a video signal is obtained that is similar to the video signal of a simulated radar when targets are detected within the visibility range. At the first output of the device, the IIT is supplied, and the third output signals the angular position of the MDNA. When signals are sent from the outputs of the target signal generator to the inputs of the processing radar information devices, a complete simulation of the functioning of the surveillance radar is provided, which allows testing of these devices and their operating algorithms, as well as training and training of operators.

Sources of information

1.Kuzmin S.Z. Basics of designing digital processing systems. - M .: Radio and communications, 1986, p. 133 - 136.

2. Tverskoy G.N., Terentyev G.K., Kharchenko I.P. Echo simulators for shipborne radar. - L .: Shipbuilding, 1973, p. 206 - 211.

3.US Patent () Q55, CL O018 7 / 40.1999 (prototype).

Claims (1)

A target signal generator comprising a control panel and a clock generator connected in series, the output of which is the first output of the device, a unit for generating relative coordinates of the integer (FOCC block), a unit for generating the maximum intensity of the target signals (block FMISC), a unit for generating the current intensity of the target signals (block FTISC ) and a noise generator and an adder connected in series, the output of which is the second output of the device, characterized in that a memory unit, three operational omitting devices (RAM), four synchronization units and a digital-to-analog converter (DAC), while the first input of the memory unit is connected by the information bus to the output of the control panel, the output of the memory unit is connected by the information bus to the first input of the FMISC unit and to the input of the FOCC unit, the output of which is connected the information bus with the second input of the block PMISC and with the second input of the first RAM, the first input of which is connected to the output of the block PMISC, the first output of the first synchronization block is connected by the address bus to the second input of the memory block and the fourth input of the first RAM, the second output is connected to the third input of the first RAM by the synchronization bus with the third input of the memory block, and the third output is connected to the first input of the second synchronization block, the first output of which is connected by the address bus to the fifth input of the first RAM and to the third input of the second RAM, the second output is connected by a synchronization bus with the sixth input of the first RAM and with the second input of the second RAM, the output of the first RAM is connected by an information bus to the first input of the second RAM, the first output of which is connected by the information bus from the first m is the input of the FTISC unit, and the second output is connected by the address bus to the third input of the third RAM, the second input of the FTISC unit is connected by the information bus to the second additional output of the clock generator, which is the third output of the device, and the output is connected by the information bus to the first input of the third RAM, the first output the clock generator is connected to the second input of the second synchronization unit and to the input of the fourth synchronization unit, the first additional output is connected to the input of the third synchronization unit, the first the output of which is connected by an address bus to the fourth input of the second RAM, and the second output is connected by a synchronization bus to the fifth input of the second RAM and to the second input of the third RAM, the fourth input of which is connected by the address bus to the first output of the fourth synchronization unit, the fifth input is connected by the synchronization bus to the second output the fourth synchronization unit, and the output is connected by an information bus to the input of the DAC, the output of which is connected to the second input of the adder.