RU2250501C2 - Neuro-net discontinuous operation device - Google Patents

Abstract

FIELD: computer science.

SUBSTANCE: device has local pools of command packets, consisting of Ram blocks and data readiness memory with logical readiness circuits, parallel memory buses, first coordinate commutator, vector registers, vector commands buffer memory blocks, vector operation block, scalar operation blocks, input blocks, data output blocks, second coordinate commutator, input and output stacks according to number of local pools of command packets.

EFFECT: higher efficiency.

1 dwg

Description

The invention relates to computer technology and can be used in the construction of information processing systems in a neural network logical basis.

Known operating device for parallel processing of numerical information, containing the memory of command cells for implementing control of data flows, a waiting matrix for finished command cells with command keys, scalar processors, a memory processor for controlling the exchange of data between the main memory and the memory of command cells, a vector processor for processing vector commands, a block processor for controlling the loading of commands from the main memory into the memory of command cells, as well as data input and output blocks [1].

The disadvantage of this device is the architectural orientation to the representation of commands, characteristic of von Neumann machines: codes of the source operands and calculation results are stored in memory, which does not exclude the possibility of unauthorized access; the operand field in the command cell format contains codes of pointers to command cells - input data sources, and the command cell data field contains the result code of the operation and the result ready flag, which complicates the procedure for determining the readiness of the command cell for processing and, as a result, increases the time it takes to solve the problem .

A multiprocessor device is known that contains a coordinate switch connected via a cache memory of scalar commands and a cache of data memory with pipelined scalar processors, through vector registers - with pipelined vector modules, through memory ports - with RAM blocks, and through input / output buses - with blocks data input / output [2].

As a disadvantage of the device, it should be noted the sequential nature of the software control of calculations, which, along with a limited number of operating units, does not allow to fully realize the potential for parallelizing the computing process and, therefore, reduce the time it takes to solve the problem. The structure of this device lacks the hardware necessary to solve unformalizable tasks inherent in a neural network logical basis.

The closest technical solution to the proposed invention is a device for processing discrete information, containing local pools of command packets, consisting of blocks of RAM and memory blocks of data readiness with logic circuits of data readiness, combined by the corresponding parallel memory buses, which are interconnected with the first coordinate switch connected by means of vector registers and a buffer memory block of vector commands with a vector operation block, as well as scalar e operating units, input units and data output units [3].

A drawback of the latter technical solution is the use of a structurally complex coordinate switch that switches oncoming information flows between bidirectional parallel memory buses and unidirectional operating unit buses, which eliminates the simultaneous execution of write and read operations from the same local pool of command packets and, therefore , reduces the overall performance of the device.

The objective of the present invention is to accelerate the computational process by spacing in the space of operations for switching oncoming information flows between local pools of command packets and operational blocks, as well as buffering the information presented in the form of packets in the input and output chains of local pools of command packets.

The task is achieved in that the neural network discrete operating device contains a second coordinate switch, input and output stacks according to the number of local pools of command packets, and the input buses of the second coordinate switch are connected to the output buses of the data input blocks, scalar and vector operational blocks, and the output buses of the second coordinate switchboard - with input buses of data output blocks and input stacks, output buses of which are connected via parallel buses with input buses corresponding output stacks, the output buses of which, in turn, are connected to the input buses of the first coordinate commutator, interconnected with the input buses of scalar operating units.

The drawing shows a structural diagram of the proposed neural network discrete operating device.

The discrete neural network operating device contains local pools of command packets (СРР) 1, consisting of random access memory (M) 2 and data ready memory (DRM) 3 blocks with data ready logical circuits (RS) 4, combined by corresponding parallel memory buses (RV) 5, which are interconnected with the first coordinate switch (MCS1) 6, connected via vector registers (VR) 7 and a vector instruction buffer unit (VIQ) 8 with a vector operation unit (VPU) 9, scalar operation units (SPU) 10, input units (In) 11 and b data output (Out) 12, as well as the second coordinate switch (MCS2) 13, input (IS) 14 and output (OS) 15 stacks according to the number of local pools of command packets.

The proposed neural network discrete operating device operates as follows.

When entering data packets generated by the input blocks (In-Input) 11,

Ready Address of local CPM CP address Opend address Value

enter the second coordinate switch (MCS2 - Memory Crossbar Switch) 13, through which, in accordance with the field code "Address of local CPM" of each data packet, the fields "CP address", "Operand address" and The "Value" of the data packet and further into the input stack (IS - Input Stack) 14 of the local pool of CPP command packets of the same name. Field "Value" from the output bus of the input stack IS is entered in the cell of the block of random access memory data (M - Memory) 2, addressed by the fields "CP address" and "Operand address". In the same address section of the data readiness memory block (DRM) 3, the readiness bit is set to zero. The zeroing of all the readiness bits in a certain address section of the DRM data readiness memory block is controlled by the data readiness scheme (RS - Readiness Scheme) 4, which in this case initiates the writing of units to all bits of the indicated address section of the DRM data readiness memory block, formation and selection of a packet from this address section of the memory blocks M to the corresponding parallel memory bus (PB - Parallel Bus) 5 of the device and then to the output stack (OS - Output Stack) 15 in the following format:

Operation and Addresses of CP Values of data Values of Functional Parameters

The process of processing a scalar command packet starts from the moment it is transferred from the parallel memory bus RV to the OS output stack of the corresponding local pool of CPP command packets. The presence of a command package in the OS stack initiates its transfer through the first coordinate switch MCS1 to a free scalar operating unit (SPU - Scalar Processor Unit) 10. Moreover, the Values of Data and Values of Functional Parameters fields of the scalar command package contain the values of the vector input data and values of the vector of weights. The processing of a vector command packet is similarly organized, with the only difference being that the command packet transmitted through the first coordinate switch MCS1 6 is recorded in vector registers (VR - Vector Registers) 7 (fields "Values of Data" and "Values of Functional Parameters") and a block buffer memory of vector commands (VIQ - Vector Instructions Queue) 8 (fields "Operation and Addresses of CP"). Moreover, the fields "Values of Data" and "Values of Functional Parameters" of the vector command package contain the values of the input data vector and the values of the weight matrix, respectively. In the process of processing through the parallel bus memory RV, output stacks OS, the first coordinate switch MCS1, vector registers VR and the buffer memory block of vector commands VIQ can be organized conveyor to combine the processing of the command package in a vector operation unit (VPU - Vector Processor Unit) 9 (multiplying the input data vector by the weight matrix) and the procedures for exchanging vector command packets and data packets with memory blocks M. As soon as ready, vector command packs accumulate s in vector registers VR and the buffer memory unit vector VIQ teams.

When outputting, the calculation results are issued in the form of data packets, the address field of each of which corresponds to one of the addresses of the data output blocks (Out - Output) 12. Data packets from the outputs of the scalar operating units SPU and the vector operational unit VPU are received as described above via the second coordinate switch MCS2 on its output bus connected to the corresponding of the output blocks Out, and are fixed in the input circuits of the data output blocks 12.

In the programming mode of the neural network discrete operating device, the topology of the neural network is formed by indicating the connections between its individual components. For this, it is necessary to enter the address codes of the command cells, the result receivers, in each command cell in the corresponding address section of the RAM block M. The necessary information (field "Value") of the data packet generated in the data input block In, through the corresponding input bus of the second coordinate switch MCS2, is entered into the address section (fields "CP address", "Operand address") of the given RAM block M (field " Address of local CPM "). The programming of the device is carried out before its use in the above modes of operation.

The setting mode of the functional parameters of the discrete neural network operating device is similar to the considered programming sequence, with the only difference being that the “Value” field of the data packet is placed in the random access memory block M corresponding to the storage location of the functional parameters in this address section. Functional parameters are configured after programming the inventive device, but before its operation. Performing the setup procedure after programming the device is essential when solving problems in a neural network logical basis, because The programming process defines the connections between the elements of the neural network, and the functional parameters are selected in the learning process of the already formed network. If the functional parameters are known in advance (the network is trained), then the programming and configuration of a discrete operating device can be arbitrary.

The introduction of the second coordinate switchboard MCS2, input IS and output OS stacks by the number of local pools of command packets into the structure of a discrete operating device of a neural network operating system allows you to speed up the process of parallelization of calculations by promptly transferring scalar and vector command packets from local pools of CPP command packets to scalar SPUs and vector VPU to operating units by means of the first coordinate switch MCS1 and simultaneously - data packets with the processing results in the opposite direction from the operating units SPU and VPU through the second coordinate switch MCS2 in the local pools of command packages CPP. The presence of input and output stacks in local pools of command packets makes it possible to coordinate the asynchronous order of arrival / retrieval of packets from the corresponding pools of command packets with the cycles of write / read operations from the memory blocks M and further accelerate the process of transmitting information flows.

Thus, the presence of a second coordinate switch, input and output stacks allows you to distribute within the device and carry out the simultaneous transmission of oncoming flows of information, which significantly increases the performance of the neural network discrete operating device.

Sources of information

1. Computers on VLSI: In 2 books. Book 2: Trans. with japan. / Motooka T., Horikoshi X., Sakauti M. et al. - M.: Mir, 1988 .-- 336 p., Pp. 78-81.

2. Patterson D., Anderson T., Cadwell N., Fromm R., Keaton K., Kozyarakis K., Thomas R, Elik K. Arguments in favor of IRAM. - Computers, No. 15, 1998, Appendix, p.3-14.

3. Patent 2176815 of the Russian Federation, IPC G 06 F 15/00. Device for processing discrete information. / G.F. Nesteruk, F.G. Nesteruk. - No.2000111364 / 09; Claimed on May 6, 2000; Publ. 12/10/2001. Bull. No. 34, Priority from 05/06/2000 - prototype.

Claims (1)

A discrete neural network operating device containing local pools of command packets, consisting of random access memory blocks and data ready memory blocks with data ready logic circuits connected by corresponding parallel memory buses, which are interconnected with the first coordinate switch connected via vector registers and a buffer block of vector commands with a vector operating unit, as well as scalar operating units, input units and data output units, characterized in that о it contains a second coordinate switch, input and output stacks according to the number of local pools of command packets, and the input buses of the second coordinate switch are connected to the output buses of data input blocks, scalar and vector operational blocks, and the output buses of the second coordinate switch are connected to the input buses of output blocks data and input stacks, the output buses of which through parallel buses are interconnected with the input buses of the corresponding output stacks, the output buses of which, in turn, are connected to the input bubbled tires first crosspoint switch interconnected with input buses operating scalar units.