JP4347352B2 - Vector data processing device - Google Patents

Description

  The present invention relates to a vector data processing apparatus used in a computer.

  A vector data processing apparatus used for a computer is known. FIG. 1 shows the configuration of a conventional vector data processing apparatus. The conventional vector data processing apparatus includes crossbar input registers 101-1, 101-2, crossbar 102, crossbar output registers 103-1, 103-2, write data registers 104-1, 104-2, and vector registers. 105-1 and 105-2, read data registers 106-1 and 106-2, arithmetic input registers 107-1 and 107-2, an arithmetic unit 108, and an arithmetic output register 109 are provided. These operate according to the clock.

  The crossbar input registers 101-1 and 101-2 are connected to the crossbar 102. The crossbar input register 101-2 is connected to other resources. The crossbar 102 is connected to the crossbar output registers 103-1 and 103-2. The crossbar output registers 103-1 and 103-2 are connected to the write data registers 104-1 and 104-2, respectively. The write data registers 104-1 and 104-2 are connected to the vector registers 105-1 and 105-2, respectively. Vector registers 105-1 and 105-2 are connected to read data registers 106-1 and 106-2, respectively. The read data registers 106-1 and 106-2 are connected to the operation input registers 107-1 and 107-2, respectively. The arithmetic input registers 107-1 and 107-2 are connected to the arithmetic unit 108. The computing unit 108 is connected to the computation output register 109. The arithmetic output register 109 is connected to the crossbar input register 101-1.

  The vector register 105-1 stores n vector data A = {a1, a2, a3,..., An} from the first to the nth (n is an integer of 3 or more).

  The vector register 105-1 is constituted by a RAM, for example. The vector register 105-1 stores n vector data A = {a1, a2, a3,..., An} in each element position according to the write address WA1, and stores them in accordance with the read address RA1. The data is output to the arithmetic unit 108 via the read data register 106-1 and the arithmetic input register 107-1.

  The vector register 5-2 stores n vector data B {b1, b2, b3,..., Bn} from the first to the nth.

  The vector register 105-2 is constituted by a RAM, for example. The vector register 105-2 stores n vector data B = {b1, b2, b3,..., Bn} in each element position according to the write address WA2, and stores them in accordance with the read address RA2. The data is output to the arithmetic unit 108 via the read data register 106-2 and the arithmetic input register 107-2.

  The computing unit 108 uses a pipeline configuration and requires several machine cycles from the input to the output of vector data. However, vector data A = {a1, a2, a3,... , B = {b 1, b 2, b 3,..., Bn} and after several machine cycles, the operation result (vector data of the operation result) C = {c 1, c 2, c 3,. cn} is generated and output. That is, a plurality of calculation units are provided so that different calculations can be executed in parallel.

  This computing unit 108 inputs the output of the computation input register 107-1 (n vector data {a1, a2, a3,..., An}) as the first operand, and outputs the computation input register 107-2. (N vector data {b1, b2, b3,..., Bn}) are input as the second operand. The computing unit 108 sequentially calculates each of the n vector data {a1, a2, a3,..., An} and the n vector data {b1, b2, b3,. To generate n operation results {c 1, c 2, c 3,..., Cn}, and sequentially output them to the operation output register 109.

  Here, it is assumed that n operation results {c1, c2, c3,..., Cn} are designated by an instruction to be stored in the vector register 105-2. In this case, the operation output register 109 outputs n operation results {c1, c2, c3,..., Cn} to the crossbar 102 via the crossbar input register 101-1.

  The crossbar 102 applies the n operation results {c1, c2, c3,..., Cn} to the vector register 105-2 designated by the instruction among the vector registers 105-1 and 105-2. Routing is performed for storage, and n operation results {c1, c2, c3,..., Cn} are sequentially transmitted through the crossbar output register 103-2 and the write data register 104-2 to the vector register 105-2. To store.

  As described above, the conventional vector data processing apparatus prepares a plurality of vector registers 105-1 and 105-2 that can store (hold) a large amount of vector data at a time, and can execute different operations in parallel. In order to do this, the computing unit 108 is provided with a plurality of computing units as computing resources. In order to store the outputs of these arithmetic units 108 in the vector register (vector register 105-2) designated by the instruction, it corresponds to a plurality of vector registers 105-1 and 105-2 and a plurality of arithmetic units, The crossbar 102 for routing the vector data is required.

  However, the conventional vector data processing apparatus has the following problems.

  First, the first problem will be described. When the number of vector elements (number of vector data) to be processed at a time is large, the time required for routing in the crossbar 102 is not a problem. On the other hand, when the number of vector elements to be processed is small, the routing time in the crossbar 102 also becomes a performance problem as overhead.

  Next, the second problem will be described. Vector registers The vector registers 105-1 and 105-2 store many elements. For this reason, if the write port for writing is increased or the read port for reading is increased with the conventional RAM maintaining a large capacity, the area of the RAM itself increases. As a result, the crossbar 102 itself becomes larger accordingly, and the routing time further increases.

  It is desired to perform the current processing for a large amount of vector data and to process a small amount of vector data at a higher speed.

  Introduces technologies related to vector data.

  Japanese Patent Laid-Open No. 9-282308 (Patent Document 1) describes a “vector instruction control method”. The vector instruction control method drives and controls a vector unit built in an LSI (Large Scale Integration) chip that constructs a vector type information processing apparatus. This vector instruction control method is included in an LSI chip incorporating a vector unit, a vector unit that executes a vector instruction with a short vector length, a scalar unit that executes a scalar instruction, and both the vector unit and the scalar unit. And an arithmetic unit shared with each other.

  Japanese Patent Laid-Open No. 9-198374 (Patent Document 2) describes a “vector processing device”. The vector processing apparatus includes a plurality of vector arithmetic processing units each including a plurality of vector registers, at least one vector arithmetic unit, and at least one data transfer circuit, and processes one vector instruction divided by the vector arithmetic processing unit. . The vector processing apparatus includes a determination unit that determines whether parallel processing of a plurality of different vector instruction sequences is possible, and divides the plurality of vector arithmetic processing units into a plurality of divided vector arithmetic processing units. Are assigned one of the different vector instruction sequences, and a plurality of different vector instruction sequences are processed in parallel.

  Japanese Patent Laid-Open No. 2001-273277 (Patent Document 3) describes an “arithmetic processing system”. An arithmetic processing system processes operations that use data vectors that each include a plurality of data elements. The processing system includes a vector data file including a plurality of storage elements for storing data elements of a data vector, and a pointer array coupled to the vector data file by a bus, At least one storage for storing at least one data element of said data vector, including an entry, each entry comprising a pointer array adapted to identify at least one storage element in the vector data file An element, for at least one specific entry of the pointer array, at least one storage element identified by the specific entry has an arbitrary starting address of the vector data file.

  Japanese Patent Application Laid-Open No. 5-233279 (Patent Document 4) describes “Information Processing Device. The information processing device uses a plurality of groups of scalar registers respectively defined corresponding to a plurality of register windows. One type of program and a second type of program using a plurality of vector registers are executed, and the information processing apparatus includes a plurality of groups of scalar registers and a predetermined number of units for realizing the plurality of vector registers. A register including a plurality of registers each used as one of the plurality of groups of scalar registers and used as one of a plurality of groups of element registers constituting each of the plurality of vector registers; Means for holding the register window number designated by the first type program being executed, and connected to the holding means; In response to an instruction using the at least one register issued by the first type program at the time of execution of the program, the instruction is executed in the register window of the stored register window number among the predetermined number of registers. A first determination circuit for determining one register to be used as a scalar register of a specified register number, and at least one register issued by the second type program when executing the second type program; In response to an instruction to be used, a second determination circuit for determining a group of registers to be used as a group of element registers constituting a vector register having a register number designated by the instruction among the predetermined number of registers And the one register connected to the first and second decision circuits and decided by the first decision circuit, and the second decision circuit And a access circuit for accessing the set of registers which are determined by the circuit.

  Japanese Patent Laid-Open No. 1-191265 (Patent Document 5) describes a “vector operation instruction starting method”. In the vector operation instruction activation method, the vector unit starts its operation based on the activation information from the scalar unit. In this vector operation instruction activation method, the activation time from the scalar unit to the vector unit is sent in a pipeline before the execution stage of the vector operation instruction. In the vector unit, the vector operation instruction is sent based on the activation time. Before the execution stage of the arithmetic instruction, the decoding of the operation code and the reading of the first element from the vector register are completed, and when the start command sent in the execution stage of the vector instruction from the scalar unit is received, The vector operation is started.

JP-A-9-282308 Japanese Patent Laid-Open No. 9-198374 JP 2001-273277 A JP-A-5-233279 JP-A-1-191265

  An object of the present invention is to provide a vector data processing apparatus that can perform the current processing for a large amount of vector data and can process a small amount of vector data at a higher speed.

  In the following, means for solving the problems will be described using the reference numerals used in the best modes and embodiments for carrying out the invention in parentheses. This reference numeral is added to clarify the correspondence between the description of the claims and the description of the best mode for carrying out the invention / example, and is described in the claims. It should not be used to interpret the technical scope of the invention.

The vector data processing apparatus of the present invention
Of the first vector data ({a1, a2, a3,..., An}) from the first to the nth (n is an integer of 3 or more), the first to jth (j is a first young number storage unit (address “0”, “1”) in which j first vector data ({a1, a2}) up to j <(n−j) satisfying an integer) are stored; Of the n second vector data ({b1, b2, b3,..., Bn}) from the first to the nth, j second vector data ({b1) from the first to the jth , B2}) is stored in a register file (11) having a second number storage section (addresses “2”, “3”);
A first vector register (5-) that stores (n−j) first vector data ({a3,..., An}) other than the j first vector data ({a1, a2}). 1) and
A second vector register (5-) that stores (n−j) second vector data ({b3,..., Bn}) other than the j second vector data ({b1, b2}). 2) and
Each of the n first vector data ({a1, a2, a3,..., An}) and the n second vector data ({b1, b2, b3,..., Bn}) An arithmetic unit (8) that sequentially performs operations on the result to generate n operation results ({c1, c2, c3,..., Cn});
Among the n operation results ({c1, c2, c3,..., Cn}), j operation results ({c1, c2}) from the first to the jth are sequentially stored in the register file. The young write data register (10-2) stored in (11),
The (n−j) operation results ({c3,..., Cn}) other than the j operation results ({c1, c2}) are sequentially added to the first and second vector registers (5-1). 5-2) and a crossbar (2) stored in the designated vector register (5-2).

The vector data processing apparatus of the present invention
The j pieces of first vector data ({a1, a2}) stored in the first young number storage section (addresses “0”, “1”) of the register file (11) are sequentially added to the computing unit. (8) and then sequentially output the (n−j) pieces of first vector data ({a3,..., An}) stored in the first vector register (5-1). A first selection circuit (12-1) for outputting to the computing unit (8);
The j pieces of second vector data ({b1, b2}) stored in the second young number storage unit (addresses “2”, “3”) of the register file (11) are sequentially added to the computing unit. (8), and then sequentially output the (n−j) second vector data ({b3,..., Bn}) stored in the second vector register (5-2). And a second selection circuit (12-2) for outputting to the computing unit (8).

The vector data processing apparatus of the present invention
A first calculation input register (7-1) connected between the first selection circuit (12-1) and the calculator (8);
A second calculation input register (7-2) connected between the second selection circuit (12-2) and the calculator (8);
An arithmetic output register (9) connected between the arithmetic unit (8) and the crossbar (2) is further provided.

The vector data processing apparatus of the present invention
First and second crossbar input registers (5) connected in correspondence with the first and second vector registers (5-1, 5-2) between the arithmetic output register (9) and the crossbar (2). 1-1, 1-2),
First and second crossbar output registers (3-1, 3-2) connected between the crossbar (2) and the first and second vector registers (5-1, 5-2);
First and second write data connected between the first and second crossbar output registers (3-1 and 3-2) and the first and second vector registers (5-1 and 5-2). And registers (4-1, 4-2).

  In the vector data processing device of the present invention, the result storage register (calculation result {c1, c2}) is not passed through the crossbar (2) for routing in a short time by making the configuration so that the young elements (calculation results {c1, c2}) are not passed. The register file (11) and the vector register (5-2)) can be confirmed.

  In the present invention, a small amount of multi-port configuration register file (11) is prepared for young elements (vector data {a1, a2}, {b1, b2}), and a large capacity (vector data {a3-an }, {B3 to bn}), the vector register (5-1, 5-2) is configured using a RAM with a small number of ports, thereby reducing the amount of hardware and increasing the vector data processing device. Can be configured.

  As described above, the vector data processing apparatus of the present invention can perform the current processing for a large amount of vector data and can process a small amount of vector data at a higher speed.

  The vector data processing apparatus of the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 2 shows the configuration of the vector data processing apparatus of the present invention. The vector data processing apparatus of the present invention includes crossbar input registers 1-1 and 1-2, a crossbar 2, crossbar output registers 3-1 and 3-2, write data registers 4-1 and 4-2, and a vector. Registers 5-1, 5-2, read data registers 6-1, 6-2, operation input registers 7-1, 7-2, operation unit 8, operation output register 9, and young write data Registers 10-1 and 10-2 (hereinafter, write data registers 10-1 and 10-2), a register file 11, and selection circuits 12-1 and 12-2 are provided. These operate according to the clock.

The crossbar input registers 1-1 and 1-2 are connected to the crossbar 2. The crossbar input register 1-2 is connected to other resources (for example, a main storage device). The crossbar 2 is connected to the crossbar output registers 3-1, 3-2. The crossbar output registers 3-1 and 3-2 are connected to the write data registers 4-1 and 4-2, respectively. The write data registers 4-1 and 4-2 are connected to the vector registers 5-1 and 5-2, respectively. The vector registers 5-1 and 5-2 are connected to the read data registers 6-1 and 6-2, respectively. The read data registers 6-1 and 6-2 are connected to the selection circuits 12-1 and 12-2, respectively.
The write data registers 10-1 and 10-2 are connected to the register file 11. The write data register 10-1 is connected to other resources. The register file 11 is connected to the selection circuits 12-1 and 12-2.
The selection circuits 12-1 and 12-2 are connected to the operation input registers 7-1 and 7-2, respectively. The arithmetic input registers 7-1 and 7-2 are connected to the arithmetic unit 8. The computing unit 8 is connected to the computation output register 9. The arithmetic output register 9 is connected to the crossbar input register 1-1 and the write data register 10-2.

The register file 11 has a first young number storage unit and a second young number storage unit.
The first young number storage unit includes n first vector data A = {a1, a2, a3,..., An} from the first to the nth (n is an integer of 3 or more). The j first vector data from the first to the jth (j is an integer satisfying j <(n−j)) are stored.
The second young number storage unit includes j pieces from the first to the j-th of n pieces of second vector data B {b1, b2, b3,..., Bn} from the first to the n-th. The second vector data is stored.
Here, j is set to 2, j pieces of first vector data are set as vector data {a1, a2}, and j pieces of second vector data are set as vector data {b1, b2}. In this case, the first young number storage unit is set to the addresses “0” and “1” of the register file 11, and the second young number storage unit is set to the addresses “2” and “3” of the register file 11.

The register file 11 has a 2-read / 2-write configuration.
Regarding writing, the register file 11 stores the register data of the write data register 10-1 or the write data register 10-2 according to the write address W1 or the write address W2 for a small amount of vector data {a1, a2}. 11 is stored in addresses “0” and “1”, and a small amount of vector data {b1, b2} is stored in the write data register 10-1 or the write data register 10-2 according to the write address W1 or the write address W2. Data is stored at addresses “2” and “3” of the register file 11. Here, the vector data in the write data register 10-1 is controlled by the write address W1, and the vector data in the write data register 10-2 is controlled by the write address W2.
Regarding the reading, the register file 11 sequentially reads the vector data stored in the addresses “0” and “1” according to the read address R1 and supplies the vector data to the selection circuit 12-1, and according to the read address R2. The vector data stored in the addresses “2” and “3” are sequentially read and supplied to the selection circuit 12-2.

  The vector register 5-1 stores (n-2) vector data {a3,..., An} other than the two vector data {a1, a2}.

The vector register 5-1 is composed of a 1-read / 1-write RAM.
For writing, the vector register 5-1 addresses (n-2) pieces of vector data {a3, a4,..., An} according to the write address WA1, and addresses the vector data in the write data register 4-1. Store sequentially in “0” to “n−2”.
For reading, the vector register 5-1 reads a large amount of vector data {a3, a4,..., An} stored in the addresses “0” to “n-2” according to the read address RA1. To the read data register 6-1.

  The vector register 5-2 stores (n−2) vector data {b3,..., Bn} other than the two vector data {b1, b2}.

The vector register 5-2 is composed of a 1-read / 1-write RAM.
For writing, the vector register 5-2 addresses (n-2) vector data {b3, b4,..., Bn} according to the write address WA2, and addresses the vector data in the write data register 4-2. Store sequentially in “0” to “n−2”.
For reading, the vector register 5-2 reads a large amount of vector data {b3, b4,..., Bn} stored in the addresses “0” to “n-2” according to the read address RA2. To the read data register 6-2.

  The selection circuit 12-1 gives priority to the output of the register file 11 out of the output of the first storage unit (address “0”, “1”) of the register file 11 and the output of the read data register 6-1. To choose. That is, the selection circuit 12-1 sequentially calculates the two vector data {a1, a2} stored in the first young number storage unit (addresses “0”, “1”) of the register file 11 to the operation input register. 7-1 to the computing unit 8 and then the (n-2) vector data {a3,..., An} stored in the read data register 6-1 are sequentially inputted to the arithmetic input register. The result is output to the computing unit 8 via 7-1.

  The selection circuit 12-2 prioritizes the output of the register file 11 out of the output of the second young number storage unit (address "2", "3") of the register file 11 and the output of the read data register 6-2. To choose. That is, the selection circuit 12-2 sequentially calculates the two vector data {b1, b2} stored in the second young number storage unit (addresses “2”, “3”) of the register file 11 in the operation input register. 7-2 is output to the arithmetic unit 8 and then (n-2) vector data {b3,..., Bn} stored in the read data register 6-2 are sequentially applied to the arithmetic unit 8. Output to.

  In this embodiment, the computing unit 8 uses a pipeline configuration and requires three machine cycles from the input to the output of vector data. However, vector data A = {a1, a2, a3, .., An}, B = {b1, b2, b3,..., Bn}, and after 3 machine cycles, the computation results (vector data of computation results) C = {c1, c2, c3,..., cn} are generated and output. That is, a plurality of calculation units are provided so that different calculations can be executed in parallel.

  The calculator 8 inputs the output of the calculation input register 7-1 (n vector data {a1, a2, a3,..., An}) as the first operand, and outputs the calculation input register 7-2. (N vector data {b1, b2, b3,..., Bn}) are input as the second operand. The arithmetic unit 8 sequentially calculates n vector data {a1, a2, a3,..., An} and n vector data {b1, b2, b3,. To generate n calculation results {c 1, c 2, c 3,..., Cn} and sequentially output them to the operation output register 9.

  Here, of the n calculation results {c1, c2, c3,..., Cn}, the two calculation results {c1, c2} from the first to the second are stored in the register file 11. (N-2) operation results {c3,..., Cn} other than the two operation results {c1, c2} are specified by the instruction to be stored in the vector register 5-2. It shall be. In this case, the operation output register 9 stores the two operation results {c1, c2} in the register file 11 via the write data register 10-2, and (n-2) operation results {c3,. .., Cn} are output to the crossbar 2 via the crossbar input register 1-1.

  For the (n−2) operation results {c3,..., Cn}, the crossbar 2 applies to the vector register 5-2 specified by the instruction in the vector registers 5-1 and 5-2. Routing is performed for storage, and (n−2) operation results {c3,..., Cn} are sequentially transferred to the vector register 5-2 via the crossbar output register 3-2 and the write data register 4-2. To store.

In the vector data processing apparatus of the present invention, the result storage register (register file) can be obtained in a short time by adopting a configuration in which the young element of the operation result (operation result {c1, c2}) is not passed through the crossbar 2 for routing. 11 and the vector register 5-2).
In the present invention, a small amount of multiport configuration register file 11 is prepared for the young elements (vector data {a1, a2}, {b1, b2}), and a large capacity (vector data {a3 to an}, For {b3 to bn}), a vector data processor can be configured with a small increase in hardware by configuring the vector registers 5-1 and 5-2 using a RAM with a small number of ports.
This will be described in detail below.

  FIG. 3 is a timing chart showing the operation of the vector data processing apparatus of the present invention.

  In this embodiment, 9 vector data A = {a1, a2, a3,..., A9} and B = {b1, b2, b3,. A case where the calculation result C = {c1, c2, c3,..., C9} is calculated will be described. Prior to the calculation, for each vector data, for vector data A, vector data a1 and a2 are stored at addresses “0” and “1” of register file 11, respectively, and seven vector data which are vector data a3 to a9. Are stored at addresses “0” to “6” of the vector register 5-1, respectively, and for the vector data B, vector data b1 and b2 are stored at addresses “2” and “3” of the register file 11, respectively. It is assumed that seven vector data as vector data b3 to b9 are stored at addresses “0” to “6” of the vector register 5-2. In addition, it is assumed that the operation results c1 and c2 are specified by an instruction to be stored in the register file 11, and the operation results c3 to c9 are specified by an instruction to be stored in the vector register 5-2.

(In clock cycle “1”)
First, the register file 11 sets the address “0” in the address register R1 corresponding to the first read port, and sets the address “2” in the address register R2 corresponding to the second read port. The register file 11 simultaneously reads the vector data a1 and b1 stored in its own addresses “0” and “2” according to the read addresses R1 and R2, respectively, and sends them to the selection circuits 12-1 and 12-2. Output.
The selection circuits 12-1 and 12-2 select the first and second read ports (vector data a1 and b1) of the register file 11, respectively, and the vector data in the clock cycle “2” that is the next clock cycle. a1 and b1 are stored in the arithmetic input registers 7-1 and 7-2.

(In clock cycle “2”)
The arithmetic unit 8 inputs the output (that is, vector data a1) of the arithmetic input register 7-1 whose value is fixed at this time as a first operand, and outputs the output (that is, vector data b1) of the arithmetic input register 7-2. Is input as the second operand to start the operation. As described above, the arithmetic unit 8 in this embodiment has a pipeline configuration in which the arithmetic processing is divided into three stages, and three clock cycles are required until the arithmetic result is determined in the arithmetic output register 9. It is said. Therefore, the arithmetic unit 8 performs an operation on the vector data a1 and b1 stored in the operation input registers 7-1 and 7-2, respectively, and outputs the operation result c1 to a clock cycle “5 after three clock cycles. "Is stored in the operation output register 9.
The register file 11 sets the address “1” in the address register R1 corresponding to the first read port, and sets the address “3” in the address register R2 corresponding to the second read port. The register file 11 simultaneously reads the vector data a2 and b2 stored in its own addresses “1” and “3” according to the read addresses R1 and R2, respectively, and sends them to the selection circuits 12-1 and 12-2. Output.
The selection circuits 12-1 and 12-2 select the first and second read ports (vector data a2 and b2) of the register file 11, respectively, and the vector data in the clock cycle “3” that is the next clock cycle. a2 and b2 are stored in the arithmetic input registers 7-1 and 7-2.
Further, the vector register 5-1 sets the address “0” in the address register RA1 that controls the read, and the vector register 5-2 sets the address “0” in the address register RA2 that controls the read. The vector registers 5-1 and 5-2 read the vector data a 3 and b 3 stored in their own addresses “0” in accordance with the read addresses RA 1 and RA 2, respectively, and the clock cycle “ 3 ", the data is output to the read data registers 6-1 and 6-2, respectively.

(In clock cycle “3”)
The arithmetic unit 8 performs an operation on the vector data a2 and b2 stored in the operation input registers 7-1 and 7-2, respectively, and outputs the operation result c2 in the clock cycle “6” after 3 clock cycles. Store in the arithmetic output register 9.
The selection circuits 12-1 and 12-2 select the read data registers 6-1 and 6-2 (vector data a3 and b3), respectively, and the vector data a3 in the clock cycle “4” that is the next clock cycle. , B3 are stored in the operation input registers 7-1 and 7-2.
The vector registers 5-1 and 5-2 respectively set the address “1” in the address registers RA 1 and RA 2 that control the reading. The vector registers 5-1 and 5-2 read the vector data a 4 and b 4 stored in their own addresses “1” according to the read addresses RA 1 and RA 2, respectively, and the next clock cycle, which is the clock cycle “ At 4 ″, the data is output to the read data registers 6-1 and 6-2.

(At clock cycle “4”)
The arithmetic unit 8 performs an operation on the vector data a3 and b3 stored in the operation input registers 7-1 and 7-2, respectively, and outputs the operation result c3 in the clock cycle “7” after 3 clock cycles. Store in the arithmetic output register 9.
The selection circuits 12-1 and 12-2 select the read data registers 6-1 and 6-2 (vector data a4 and b4), respectively, and the vector data a4 in the clock cycle “5” that is the next clock cycle. , B4 are stored in the operation input registers 7-1 and 7-2.
The vector registers 5-1 and 5-2 set the address “2” in the address registers RA 1 and RA 2 that control the reading. The vector registers 5-1 and 5-2 read the vector data a 5 and b 5 stored in their own address “2” according to the read addresses RA 1 and RA 2, respectively, and the next clock cycle is the clock cycle “ At 5 ″, the data is output to the read data registers 6-1 and 6-2.

(At clock cycle “5”)
The arithmetic unit 8 performs an operation on the vector data a4 and b4 stored in the operation input registers 7-1 and 7-2, respectively, and outputs the operation result c4 in the clock cycle “8” after 3 clock cycles. Store in the arithmetic output register 9.
The selection circuits 12-1 and 12-2 select the read data registers 6-1 and 6-2 (vector data a5 and b5), respectively, and the vector data a5 in the clock cycle “6” that is the next clock cycle. , B5 are stored in the operation input registers 7-1 and 7-2.
The vector registers 5-1 and 5-2 set the address “3” in the address registers RA 1 and RA 2 that control the reading. The vector registers 5-1 and 5-2 read the vector data a 6 and b 6 stored in their own address “3” in accordance with the read addresses RA 1 and RA 2, respectively, and the clock cycle “ At 6 ″, the data is output to the read data registers 6-1 and 6-2.
The operation output register 9 stores the operation result c1 stored in the operation output register 9 in the write data register 10-2 in the clock cycle “6” which is the next clock cycle.

(At clock cycle “6”)
The arithmetic unit 8 performs an operation on the vector data a5 and b5 stored in the operation input registers 7-1 and 7-2, respectively, and outputs the operation result c5 in the clock cycle “9” after 3 clock cycles. Store in the arithmetic output register 9.
The selection circuits 12-1 and 12-2 select the read data registers 6-1 and 6-2 (vector data a6 and b6), respectively, and the vector data a6 in the clock cycle “7” that is the next clock cycle. , B6 are stored in the operation input registers 7-1 and 7-2.
The vector registers 5-1 and 5-2 set the address “4” in the address registers RA 1 and RA 2 that control the reading. The vector registers 5-1 and 5-2 read the vector data a 7 and b 7 stored in their own address “4” according to the read addresses RA 1 and RA 2, respectively, and the next clock cycle, which is the clock cycle “ 7 ", the data is output to the read data registers 6-1 and 6-2.
The operation output register 9 stores the operation result c2 stored in the operation output register 9 in the write data register 10-2 in the clock cycle “7” which is the next clock cycle.
The register file 11 sets the address “3” in the write address register W2 that controls the writing. The register file 11 stores the calculation result c1 stored in the write data register 10-2 in its address “3” in the next clock cycle “7” according to the write address W2.

(At clock cycle “7”)
The arithmetic unit 8 performs an operation on the vector data a6 and b6 stored in the operation input registers 7-1 and 7-2, respectively, and outputs the operation result c6 in the clock cycle “10” after 3 clock cycles. Store in the arithmetic output register 9.
The selection circuits 12-1 and 12-2 select the read data registers 6-1 and 6-2 (vector data a7 and b7), respectively, and the vector data a7 in the clock cycle “8” that is the next clock cycle. , B7 are stored in the arithmetic input registers 7-1 and 7-2.
The vector registers 5-1 and 5-2 set the address “5” in the address registers RA 1 and RA 2 that control the reading. The vector registers 5-1 and 5-2 read the vector data a 8 and b 8 stored in their own addresses “5” in accordance with the read addresses RA 1 and RA 2, respectively, and the clock cycle “ At 8 ″, the data is output to the read data registers 6-1 and 6-2.
The calculation output register 9 stores the calculation result c3 stored in the calculation output register 9 in the crossbar input register 1-1 at the clock cycle “8” which is the next clock cycle.
The register file 11 sets the address “4” in the write address register W2 that controls its writing. The register file 11 stores the calculation result c2 stored in the write data register 10-2 at its address “4” in the next clock cycle “8” according to the write address W2.

(At clock cycle “8”)
The arithmetic unit 8 performs an operation on the vector data a7 and b7 stored in the operation input registers 7-1 and 7-2, respectively, and outputs the operation result c7 in the clock cycle “11” after 3 clock cycles. Store in the arithmetic output register 9.
The selection circuits 12-1 and 12-2 select the read data registers 6-1 and 6-2 (vector data a8 and b8), respectively, and the vector data a8 in the clock cycle “9” that is the next clock cycle. , B8 are stored in the operation input registers 7-1 and 7-2.
The vector registers 5-1 and 5-2 set the address “6” in the address registers RA 1 and RA 2 that control the reading. The vector registers 5-1 and 5-2 read the vector data a 9 and b 9 stored in their own addresses “6” in accordance with the read addresses RA 1 and RA 2, respectively, and the clock cycle “ At 9 ″, the data is output to the read data registers 6-1 and 6-2.
The crossbar 2 routes the operation result c3 stored in the crossbar input register 1-1, and stores it in the crossbar output register 3-2 at the clock cycle "9" which is the next clock cycle.
The operation output register 9 stores the operation result c4 stored in the operation output register 9 in the crossbar input register 1-1 at the clock cycle “9” which is the next clock cycle.

(At clock cycle “9”)
The arithmetic unit 8 performs an operation on the vector data a8 and b8 stored in the operation input registers 7-1 and 7-2, respectively, and outputs the operation result c8 in the clock cycle “12” after 3 clock cycles. Store in the arithmetic output register 9.
The selection circuits 12-1 and 12-2 select the read data registers 6-1 and 6-2 (vector data a9 and b9), respectively, and the vector data a9 in the clock cycle “10” that is the next clock cycle. , B9 are stored in the operation input registers 7-1 and 7-2.
The crossbar output register 3-2 stores the calculation result c3 stored in the crossbar output register 3-2 in the write data register 4-2 in the clock cycle “10” which is the next clock cycle.
The crossbar 2 routes the operation result c4 stored in the crossbar input register 1-1, and stores it in the crossbar output register 3-2 at the clock cycle "10" which is the next clock cycle.
The calculation output register 9 stores the calculation result c5 stored in the calculation output register 9 in the crossbar input register 1-1 in the clock cycle “10” which is the next clock cycle.

(At clock cycle “10”)
The arithmetic unit 8 performs an operation on the vector data a9 and b9 stored in the operation input registers 7-1 and 7-2, respectively, and outputs the operation result c9 in the clock cycle “13” after 3 clock cycles. Store in the arithmetic output register 9.
The vector register 5-2 sets the address “0” in the address register WA2 that controls the writing. The vector register 5-2 stores the operation result c1 stored in the write data register 4-2 at its address “0” in the next clock cycle “11” according to the write address WA2. To do.
The crossbar output register 3-2 stores the operation result c4 stored in the crossbar output register 3-2 in the write data register 4-2 in the clock cycle “11” which is the next clock cycle.
The crossbar 2 routes to the operation result c5 stored in the crossbar input register 1-1, and stores it in the crossbar output register 3-2 at the clock cycle "11" which is the next clock cycle.
The operation output register 9 stores the operation result c6 stored in the operation output register 9 in the crossbar input register 1-1 in the clock cycle “11” which is the next clock cycle.

(At clock cycle “11”)
The vector register 5-2 sets the address “1” in the address register WA2 that controls the writing. The vector register 5-2 stores the operation result c2 stored in the write data register 4-2 at its address “1” in the next clock cycle “12” according to the write address WA2. To do.
The crossbar output register 3-2 stores the operation result c5 stored in the crossbar output register 3-2 in the write data register 4-2 in the clock cycle “12” which is the next clock cycle.
The crossbar 2 routes the operation result c6 stored in the crossbar input register 1-1, and stores it in the crossbar output register 3-2 at the clock cycle "12" which is the next clock cycle.
The operation output register 9 stores the operation result c7 stored in the operation output register 9 in the crossbar input register 1-1 in the clock cycle “12” which is the next clock cycle.

(At clock cycle “12”)
The vector register 5-2 sets the address “2” in the address register WA2 that controls the writing. The vector register 5-2 stores the operation result c3 stored in the write data register 4-2 at its address “2” in the next clock cycle “13” according to the write address WA2. To do.
The crossbar output register 3-2 stores the operation result c6 stored in the crossbar output register 3-2 in the write data register 4-2 in the clock cycle “13” which is the next clock cycle.
The crossbar 2 routes the operation result c7 stored in the crossbar input register 1-1, and stores it in the crossbar output register 3-2 at the clock cycle "13" which is the next clock cycle.
The calculation output register 9 stores the calculation result c8 stored in the calculation output register 9 in the crossbar input register 1-1 in the clock cycle “13” which is the next clock cycle.

(At clock cycle “13”)
The vector register 5-2 sets the address “3” in the address register WA2 that controls the writing. The vector register 5-2 stores the calculation result c4 stored in the write data register 4-2 at its address “3” in the next clock cycle “14” according to the write address WA2. To do.
The crossbar output register 3-2 stores the operation result c7 stored in the crossbar output register 3-2 in the write data register 4-2 in the clock cycle “14” which is the next clock cycle.
The crossbar 2 routes the operation result c8 stored in the crossbar input register 1-1, and stores it in the crossbar output register 3-2 at clock cycle "14" which is the next clock cycle.
The operation output register 9 stores the operation result c9 stored in the operation output register 9 in the crossbar input register 1-1 in the clock cycle “14” which is the next clock cycle.

(At clock cycle “14”)
The vector register 5-2 sets the address “4” in the address register WA2 that controls the writing. The vector register 5-2 stores the operation result c5 stored in the write data register 4-2 at its address “4” in the clock cycle “15” which is the next clock cycle in accordance with the write address WA2. To do.
The crossbar output register 3-2 stores the operation result c8 stored in the crossbar output register 3-2 in the write data register 4-2 in the clock cycle “15” which is the next clock cycle.
The crossbar 2 routes the operation result c9 stored in the crossbar input register 1-1, and stores it in the crossbar output register 3-2 at the clock cycle "15" which is the next clock cycle.

(At clock cycle “15”)
The vector register 5-2 sets the address “5” in the address register WA2 that controls the writing. The vector register 5-2 stores the calculation result c6 stored in the write data register 4-2 at its address “5” in the next clock cycle “16” in accordance with the write address WA2. To do.
The crossbar output register 3-2 stores the operation result c9 stored in the crossbar output register 3-2 in the write data register 4-2 in the clock cycle “16” which is the next clock cycle.

(At clock cycle “16”)
The vector register 5-2 sets the address “6” in the address register WA2 that controls the writing. The vector register 5-2 stores the calculation result c7 stored in the write data register 4-2 at its address “6” in the next clock cycle “17” according to the write address WA2. To do.

  As described above, the vector data processing apparatus of the present invention has the following effects.

  First, the first effect will be described. According to the vector data processing device of the present invention, the young element (calculation result {c1, c2}) of the calculation result is not passed through the crossbar 2 for routing. Therefore, the result storage register (register file 11, vector register 5-2) can be determined in a short time.

  Next, the second effect will be described. According to the present invention, a small amount of multiport configuration register file 11 is prepared for the young elements (vector data {a1, a2}, {b1, b2}), and a large capacity (vector data {a3 to a9}, For {b3 to b9}), vector registers 5-1 and 5-2 are configured by using a RAM with a small number of ports. Therefore, the vector data processing apparatus can be configured with a small increase in hardware amount.

  As described above, the vector data processing apparatus of the present invention can perform the current processing for a large amount of vector data and can process a small amount of vector data at a higher speed.

FIG. 1 shows the configuration of a conventional vector data processing apparatus. FIG. 2 shows the configuration of the vector data processing apparatus of the present invention. FIG. 3 is a timing chart showing the operation of the vector data processing apparatus of the present invention.

Explanation of symbols

1-1, 1-2 Crossbar input register,
2 Crossbar,
3-1, 3-2 Crossbar output register,
4-1, 4-2 Write data register,
5-1, 5-2 Vector register,
6-1, 6-2 Read data register,
7-1, 7-2 Operation input register,
8 arithmetic units,
9 Operation output register,
10-1, 10-2 Write data register (write data register for young number),
11 Register file,
12-1, 12-2 selection circuit,
RA1, RA2 read address,
WA1, WA2 Write address,
R1, R2 read address,
W1, W2 Write address,
101-1, 101-2 crossbar input register,
102 Crossbar,
103-1, 103-2 Crossbar output register,
104-1, 104-2 write data register,
105-1 and 105-2 vector registers,
106-1, 106-2 read data register,
107-1, 107-2 arithmetic input register,
108 computing units,
109 arithmetic output register,

Claims (4)

Of the 1st to nth (n is an integer of 3 or more) n first vector data, the 1st to jth (j is an integer satisfying j <(n−j)) Of the first young number storage section storing the first vector data and the j second vector data from the first to the jth out of the n second vector data from the first to the nth. A register file having a second young number storage unit storing
A first vector register storing (n−j) first vector data other than the j first vector data;
A second vector register storing (n−j) second vector data other than the j second vector data;
An arithmetic unit that sequentially performs an operation on each of the n first vector data and the n second vector data to generate n operation results;
A young write data register for sequentially storing j operation results from the first to jth out of the n operation results in the register file;
A vector data processing apparatus comprising: a crossbar that sequentially stores (n−j) operation results other than the j operation results in a designated vector register of the first and second vector registers. The vector data processing apparatus according to claim 1,
The j first vector data stored in the first young number storage unit of the register file are sequentially output to the computing unit, and then the (n−) stored in the first vector register. j) a first selection circuit for sequentially outputting the first vector data to the computing unit;
The j second vector data stored in the second young number storage unit of the register file are sequentially output to the computing unit, and then the (n−) stored in the second vector register. j) A vector data processing apparatus further comprising a second selection circuit that sequentially outputs the second vector data to the computing unit. The vector data processing apparatus according to claim 2, wherein
A first calculation input register connected between the first selection circuit and the calculator;
A second calculation input register connected between the second selection circuit and the calculator;
A vector data processing apparatus further comprising an arithmetic output register connected between the arithmetic unit and the crossbar. The vector data processing apparatus according to claim 3,
First and second crossbar input registers connected in correspondence with the first and second vector registers between the arithmetic output register and the crossbar;
First and second crossbar output registers connected between the crossbar and the first and second vector registers;
A vector data processing apparatus further comprising first and second write data registers connected between the first and second crossbar output registers and the first and second vector registers.

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