RU2249845C1 - Multiplier based on neurons - Google Patents

Abstract

FIELD: computers.

SUBSTANCE: device has data input block, multiplied part register, multiplying part register, adder block, block for analyzing multiplying part digit, storage block, control block, threshold elements, neurons. Multiplication operation is performed by analyzing higher digits of multiplying part with displacement of multiplied part to the right. Combination blocks provide for parallel, digit-wise production of multiplication result digits.

EFFECT: simplified construction and operation.

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Description

The invention relates to technical means of computer science and computer technology and can be used for the synthesis of arithmetic-logic devices, to create high-speed and economical digital devices for multiplying numbers in direct codes.

It is known "Device for multiplication in finite fields" (patent No. 5064139/09), allowing to perform multiplication of polynomials.

It is also known "Multiplier device" (patent No. 93031693/09), which allows you to multiply binary numbers.

In addition, the "Associative Number Multiplier" (patent No. 95104047/09) is known, which allows the multiplication of arbitrary numbers.

As a prototype, "Device for multiplying numbers in a positional code" (patent No. 94001646/09), which performs the operation of multiplying binary numbers in direct codes, is selected.

The challenge is as follows:

1) reduce the hardware costs of the device,

2) simplify the control unit algorithm,

3) increase the speed of the operation of summation-subtraction of numbers in direct codes,

4) increase the reliability of the multiplier.

In the presented multiplier, binary numbers are multiplied in direct codes. The proposed multiplier will significantly reduce the hardware, which leads to a simplification of the combinational circuit, as well as greatly simplify the algorithm of the device.

The solution to the problem is that the multiplier on neurons containing the register of the multiplier and the register of the multiplier, characterized in that it is additionally entered: data input unit, summing unit, multiplier discharge analysis unit, result storage unit, control unit, the first control output of the control unit being connected with a control input of the data input unit, the first information output of which is connected to the information input of the multiplier register, the first control output of which is connected to the third control input of the unit board, the second to fourth control outputs of which are connected respectively to the first to third control inputs of the register of the multiplier, the information output of which is connected to the information input of the summing unit, the information output of which is connected to the information input of the result storage unit, the first to sixth control inputs of which are connected respectively from the ninth to fourteenth control outputs of the control unit, from the fifth to the seventh control outputs of which are connected respectively to the first through third control inputs of the multiplier register, the second control output of which is connected to the first control input of the multiplier discharge analysis unit, the first control output of which is connected to the fourth control input of the control unit, the eighth control output of which is connected to the second control input of the factor discharge analysis unit, the second control the output of which is connected to the fourth control input of the register of the multiplier, the information input of which is connected to the information output of the data input unit x, the control output of the data input unit is connected to the control input of the summing unit, the first and second control inputs of the control unit "START" and "RESET" are external inputs of the device.

Multiplication performed by the method of accumulation of partial works. The operation of multiplication in modern computers is most often performed by summing the partial products shifted by one or more digits, each of which is the result of multiplying the factor multiplied by the corresponding digit (s). With the exact multiplication of two numbers, the number of significant digits of the product can ultimately reach the double number of significant digits of the factors. Even more difficult is the situation when multiplying several numbers. Therefore, in a work, only in individual cases they use a double number of discharges, usually they are limited by the number of discharges that the factors had. The simplest operation of computer multiplication is in direct code. In this case, at the first stage, the sign of the product is determined by adding the signed digits of the factors modulo 2. The product is calculated as the sum of the partial products, each of which is obtained by successive shifts and multiplication of the multiplier by the corresponding digit of the factor. The product of two n-bit numbers is a 2n-bit number. Multiplication of the modules of the factors is carried out according to the rules of arithmetic according to the binary multiplication table. The result is assigned the character received. Since the multiplication is performed in the binary system, the partial products are either equal to 0 (when multiplied by 0), or to the factor itself (when multiplied by 1), shifted by the corresponding number of digits.

BVD - data input unit is used to enter operands and determine the sign of the operation.

RMN - the register of the multiplicand is used to store the multiplicand during the multiplication operation.

RMNL - the multiplier register is used to store the multiplier during the multiplication operation and determine the end of the multiplication operation.

BSUM - block summation is used to perform the addition operation.

BARMNL - the unit of analysis of the discharge of the multiplier serves to generate a shift signal of the multiplier.

BHR - the storage unit is used to store the work. BU - the control unit is used to control the device.

Figure 1 shows a structural diagram of a multiplier on neurons.

Figure 2 presents a variant of the technical implementation of the data input unit.

Figure 3 presents a variant of the technical implementation of the register of multiplicable.

Figure 4 presents a variant of the technical implementation of the register of the multiplier.

Figure 5 presents a variant of the technical implementation of the summation block.

Figure 6 shows a schematic diagram of a single-bit adder on neurons.

Figure 7 presents a variant of the technical implementation of the unit for analyzing the discharge of the multiplier.

On Fig presents a variant of the technical implementation of the storage unit.

In Fig.9, a meaningful graph diagram of the algorithm of the control unit of the multiplier on neurons.

Figure 10 is a labeled graph diagram of the algorithm of operation of the multiplier on neurons.

The multiplier (Fig. 1) contains: a data input unit, a multiplier register, a multiplier register, a summing unit, a multiplier discharge analysis unit, a storage unit, a control unit, threshold elements, neurons.

To describe the operation algorithm of control unit 7, the following identifiers are used.

1. CHP - signal the beginning of work.

2. SSRMN - signal to reset the register of the multiplicable.

3. SZMN - signal recording multiplicative.

4. VDMN - the issuance of this multiplier.

5. SSRMNL - signal to reset the register of the multiplier.

6. SZMNL - signal recording multiplier.

7. SSDMNL - signal shift factor.

8. PPR - a sign of an empty register.

9. SAN - signal analysis of the discharge of the multiplier.

10. PRI - rectangular pulses.

11. GI - generator pulses.

12. TI - clock pulses.

13. OBNSTR - signal to zero lines of RAM.

14. OBNST - signal zeroing the columns of RAM.

15. VK - a signal for selecting a crystal.

16. ЗП / ЧТ - write / read permission signal.

17. DMN - this is the multiplier.

18. DMNL - this multiplier.

19. ZRP - a significant discharge of a work.

20. PMM is the transformed multiplier.

21. RMNL - the rank of the multiplier.

22. SSDMN - shift signal of the multiplicand.

23. OL is a work.

24. RESET - reset signal (reset) of all combination blocks of the multiplier.

25. START - the signal the start of the multiplier.

The operation of the device control algorithm.

Content GAW control is shown in Fig.9 and reflects the operation of the control unit (Fig.1).

By the command "RESET = 1" (block 2) and the signal "START" (block 3), all the memory elements of the device are set to zero.

In block 4 of the algorithm, the commands: BKhR = GI, BKhR = TI, BKhR = VK, ZP = 1, rectangular pulse signals from the control unit are received at the RAM input of the result storage unit, and the chip is selected and the RAM is set to recording mode.

In block 5 of the algorithm, by the command CHP = 1, an enable signal for the operation of the encoder is received at the input of the data input block.

In block 6 of the algorithm, by the command CCPMN = 1, the multiplier register is reset to zero, and by the CCPMNL = 1 command, the multiplier register is reset to zero. The SZMN = 1 command allows writing the multiplicand to the multiplicative register. The SZMNL command = 1 allows the multiplier to be written to the multiplier register.

In block 7, the commands: RMN = DMN, RMNL = DNML using the encoder (keyboard) SR (figure 2) is loaded into the registers of the multiplier and factor of the operands.

In block 8 of the algorithm, the contents of the register of the multiplier are analyzed. This is accomplished using an SPR signal. If PPP = 1, then the register of the multiplier is empty and in this case the product is written to the storage unit by the command BHR = PR of block 16 and the multiplier finishes its work. If SPR = 0, then this means that the register of the multiplier is not empty, and by the command BARMNL = RMNL of block 9, the discharge of the multiplier is fed to the analysis block of the multiplier.

In block 10 of the algorithm, the discharge of the SAN signal multiplier is analyzed. If the signal SAN = 1, then there is a transition to block 11 of the algorithm. At the same time, by the signal РМН = VDMN, the transmission of the multiplicable from the register of the multiplicable to the summing unit is enabled. At the command BSUM = PMM block 12, the converted multiplicand is transferred from the register of the multiplicand to the summation block. By the command RMLN = SSDMNL of block 13, the factor is shifted in the register of the factor by 1 digit to the right, after which there is a transition to block 8 of the algorithm.

If the signal SAN = 0, there is a transition to block 14 of the algorithm, in which, according to the BARMNL = PRI command, rectangular pulses are fed to the multiplier discharge analysis block.

In block 15, at the command РМН = ССДМН, the multiplicative in the register of the multiplicative is shifted by one digit to the right. After this, the algorithm proceeds to block 8.

Block 17 of the algorithm is the final block of the algorithm.

The work of the multiplier on neurons is as follows.

External control signals "Start" and "Reset" are received in the control unit 7.

Block 1 data input BVD contains the encoder (conventional standard keyboard) DF DD8, adder modulo two DD9 (figure 2). This block allows you to enter binary numbers (multiplier and factor). From the output of the encoder, a binary code of the multiplier and the multiplier is formed with its own signs: DMN, DMNL, ZRMN, ZRMNL. Sign bits from the output of the encoder are fed to the input of the adder modulo two. The ZRP signal the sign bit of the product is formed at the output of the DD9 element. Modulo two adder is implemented on the formal neuron of the FN [2]. The output signal is calculated by the formula [1]:

where w1, w2, w3 are the gains, and T is the threshold voltage.

The output signals of the data input unit 1 are the binary codes of the multiplied DMN and the DMNL multiplier, as well as the sign bit of the product of the ZRP.

The register of multiplicative 2 РМН is a set of D-triggers DD10, DD11, DD12, DD13 (Fig. 3). This register is designed to store the bits of the multiplicand, as well as to organize the shift, the bits of the multiplicative are shifted by one bit in the direction of the younger part (to the right). The output of the D-trigger Tpi is the input for the next D-trigger Tpi + 1 (Fig. 30), thereby organizing the shift of information to the right by one bit. At the input of the register of the multiplier, the DMN bits of the multiplier from the data input unit 1 are received, while the highest bits are recorded starting from Tp1 and ending in Trn. The multiplier register is controlled from the control unit 7 by means of control signals. At the signal SSRMN, the reset signal of the register of the multiplicable is the reset of D-flip-flops. According to the SZMN signal, the record of the multiplicand records the bits of the multiplicative in the register of the multiplicable. At the VDMN signal, the output of the multiplier reads the bits of the PMN of the transformed multiplier. According to the signal SSDMN, the signal of the shift of the multiplicative occurs the shift of the multiplicable by one digit towards the lower part (to the right). At the output of the block, the PMN bits of the transformed multiplier are formed.

The register of the factor 3 of the RMNL is a set of D-triggers DD15, DD16, DD17, DD18 and an OR gate DD14 (Fig. 4). The multiplier register is designed to store the bits of the multiplier, to organize the shift of the bits of the multiplier by one bit in the direction of the senior part (to the right), in order to obtain and analyze the current senior bit of the multiplier. Information is recorded as follows: the most significant bits of the multiplier are written to the register on the right side. The senior rank is entered in Trn, the youngest in Tr1 (figure 4). At each shift to the right by one digit, the multiplier register is analyzed for the presence of multiplier bits. If there is at least one bit equal to one, the PPP signal indicates an empty register equal to one, otherwise the SPR signal takes a value equal to zero. The SPR signal is input to the control unit 7. At the input of the register of the multiplier received DMNL bits of the multiplier from block 1 data input. The register of the multiplier is controlled from the control unit 7 by means of control signals. According to the signal CSRMNL signal reset the register of the multiplier is reset D-flip-flops. According to the SZMLN signal, the multiplier record signal records the bits of the multiplier in the multiplier register. According to the SSDMNL signal, the multiplier shift signal causes the multiplier to shift by one bit toward the older part (to the right). At the block output, a PMNL signal is generated for the current senior bit of the multiplier, which is input to the multiplier discharge analysis block 5, and also an SPR signal is an empty register sign, which is input to the control block 7.

Block 4 summing BSUM consists of k-adders on neurons and is organized on the elements: DD19, DD20, DD21, DD22. The sign bit is stored in the D-trigger Tr, implemented on the element DD32. The block is designed to perform the operation of summation, in order to obtain partial sums at the intermediate steps of the calculation, as well as the categories of the product at the end of the operation of multiplication and storage of the sign discharge of the product of the PSA (figure 5). The input information of the block is the bits of the multiplied PMM. The output is the sum of the Si digits of the multiplicand and the sum obtained in the previous step and the transfer of Pi + 1 to the higher digits. The output of each block of summation is its second input, feedback is organized in order to add the intermediate sum with the converted multiplier on the next measure. The third input of each adder block receives the transfer from the lower digits Pi. Each summing unit is a single-bit adder, the inputs of which receive bits of the transformed multiplier, the sum of the numbers from the previous stage of addition and transfer from the lower digits. The output is the sum of Si obtained and the transfer of Pi + 1 to the highest order. The product of the PR numbers with its ZRP sign is recorded in the RAM random access memory of the result storage unit (Fig. 1).

The single-bit adder of the block consists of threshold elements, Fig. 6 shows a circuit diagram of a single-bit adder implemented on the threshold elements DD23 and DD24 (Fig. 6). Element DD23 is designed to receive a discharge transfer to the senior discharge. The _j jth digit of the multiplied, P _i transfer from the least significant bit from the output of the previous adder, Si-th digit of the sum is received at the input of the element. At the output of the block, a signal of the sum of Si is formed and P _{i + 1} transfer to the high order. The operation of this element is described using the formula [3]:

where w1, w2, w3 are the gain and T is the threshold voltage. Element DD24 is designed to receive the discharge of the amount. The aj jth digit of the multiplied, P _i -transfer to the senior digit from the output of the previous adder, S _i i-th digit of the sum, P _{i + 1} -transfer to the senior digit arrive at the input of the element. At the output of the block, a signal S _{i + 1} bit of the sum is formed. The operation of this element is described using the formula [4]:

where w1, w2, w3, w4 are the gains, and T is the threshold voltage.

Block 5 analysis of the discharge factor BARMNL consists of threshold elements DD25, DD26, DD27, as well as the D-trigger DD28. It is designed to analyze the current discharge of the multiplier, starting with the highest (Fig.7). At the block input, the RMPN receives the current digit of the multiplier, as well as the signal from the control unit — with rectangular pulses. At the output, a shift signal of the multiplicable SSSMN is formed, as well as an SAN analysis signal. Element DD25 performs the function of an inverter. The operation of this element is described using the formula [5]:

where w1 is the gain and T is the threshold voltage. Element DD26 performs the logical function of disjunction. The operation of this element is described using the formula [6]:

where w1, w2 are the gain and T is the threshold voltage. Element DD27 performs a logical conjunction function. The operation of this element is described using the formula [7]:

where w1, w2 are the gains, and T is the threshold voltage. The operation of the unit is as follows: the input signal is the next bit of the multiplier of the MPNL supplied to the inputs of the threshold elements DD25 and DD26, which implement the logical functions NOT and OR. If the digit of the multiplier is equal to the unit PMNL = 1, then this unit through the OR circuit will generate an input signal at the output of the threshold element DD26. The second input of the OR circuit DD26 will be zero, since this signal will pass through the inverter NOT threshold element DD25. If the digit of the factor is equal to zero PMNL = 0, then through the inverter NOT DD25, one will also arrive at the second input of the threshold element DD26. The first input of the OR OR DD26 circuit will receive zero. The output of DD26 will always be one. The combinational circuit, consisting of the elements DD25 and DD26, is a converter for the discharge of the multiplier (zero - unit information) to one. At the first input of the conjugator DD27 will receive a trigger signal equal to one from the output DD26. Rectangular pulses from the control unit 7 will go to the second input of the conjugator DD27. At the output of the conjunction circuit DD27, rectangular pulses of the SDMN will be generated, which are fed to the input of the register of the multiplicable PMN and organize the shift signal to the right of the operand bits. The AND logic implemented on the threshold element DD27 performs the function of an electronic key, through which the rectangular pulses of the PRI from the control unit organize the operation of shifting the multiple by one digit to the right. The D-trigger will always be set to a state equal to the digit of the multiplier. This is necessary for the analysis of the received discharge of the multiplier and the formation of the SAN signal from the output of the DD18 trigger. The analysis signal SAN is fed to the input of control unit 7. The DD28 D-flip-flop performs a delay function to avoid an asynchronous process in the multiplier.

Block 6 storing the result of BHR consists of RAM DD31, line counter DD30, column counter DD29 and is used to store binary bits of the result when performing the multiplication operation. The input of the block receives the bits of the product of PR. BHR is controlled by the control unit 7 by means of control signals. The GI signal generator pulses are fed to the input of the column counter DD29, to ensure that the work is recorded on a new line. The signal TI clock pulses are fed to the input of the line counter DD30 to record the bits of the product in the columns of RAM. The signal OBNST zeroing the columns is fed to the input of the column counter DD29 and is designed to reset this counter. The signal OBNSTR zeroing lines is input to the line counter DD30 and is designed to reset this counter. The VK signal selects the crystal at the RAM input and is designed to select the RAM crystal. The read / write / read / write signal sets the RAM to write / read mode.

Logical conditions: X1: "START" X2: "PPR" X3: SAN Operators: U1 "RESET: = 1" Y 11 "RMN = DMN" Y2 "BHR = GI" Y 12 "RMNL = DMNL" UZ "BHR = TI" Y 13 "BARMNL = RMNL" U4 "BHR = VK" Have 14 "RMN = VDMN" 5 "RFP = 1" At 15 "BSUM = PMM" Y6 "CHP = 1" U16 "RMNL = SSDMNL" 7 "SSRMN = 1" 17 "BARMNL = PRI" U8 "SSRMNL = 1" At 18 "RMN = SSDMN" 9 "SZMN = 1" U 19 "BHR = PR" Y 10: "SZMNL = 1"

SOURCES OF INFORMATION

1. Mkrtchyan S.O. Design of computer logical devices on neural elements. - M .: Energy, 1977

2. Dertouzos M. Threshold logic. - M .: Mir, 1967

3. Vavilov E.I. and others. Synthesis of schemes on threshold elements. - M .: Owls. radio. 1970 year

4. Galushkin A.I. Synthesis of multilayer pattern recognition schemes. M .: Energy, 1974

5. Pozin I.V. Modeling of neural structures. - M.: Science, 1970.

6. Patent N 94001646/09 (prototype).

7. Patent N 93031693/09 (analogue).

8. Patent N 506413 9/09 (analogue).

9. Patent N 95104047/09 (analogue).

Claims (1)

A multiplier on neurons containing a multiplier register and a multiplier register, characterized in that it is additionally introduced: a data input unit, a summing unit, a multiplier discharge analysis unit, a result storage unit, a control unit, the first control output of the control unit being connected to a control input of the data input unit the first information output of which is connected to the information input of the register of the multiplier, the first control output of which is connected to the third control input of the control unit, from the second to the fourth the leading outputs of which are connected respectively to the first through third control inputs of the register of the multiplier, the information output of which is connected to the information input of the summing unit, the information output of which is connected to the information input of the result storage unit, the first to sixth control inputs of which are connected with the ninth to fourteenth control outputs, respectively control unit, from the fifth to the seventh control outputs of which are connected respectively to the first to third control inputs a multiplier register, the second control output of which is connected to the first control input of the multiplier discharge analysis unit, the first control output of which is connected to the fourth control input of the control unit, the eighth control output of which is connected to the second control input of the factor discharge analysis unit, the second control output of which is connected to the fourth the control input of the register of the multiplier, the information input of which is connected to the information output of the data input unit, the control output of the data input unit connected to the control input of the summing unit, the first and second control inputs of the control unit "START" and "RESET" are external inputs of the device.

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