RU2235429C1 - Method and device for time-and-frequency synchronization of communication system - Google Patents

Abstract

FIELD: radio engineering; communication systems.

SUBSTANCE: proposed method and device are characterized in estimation of signal position in time involving two phases. First phase includes generation of decision function with wide friendly response to enhance probability of adequate signal detection. Second phase includes generation of decision function with narrow friendly response to provide for accurate estimate of signal position in time. Shaping frequency shift estimate also involves two phases, validity of this estimate being very high as it is based on high-reliable estimate of signal position in time. One more characteristic of proposed method and device is capability of synchronization at relatively high initial values of frequency shift which is inaccessible for most known methods and devices for time-and-frequency synchronization.

EFFECT: enhanced noise immunity of communication system time-and-frequency synchronization.

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Description

The invention relates to the field of radio engineering, in particular to a method and apparatus for time-frequency synchronization of a communication system.

In communication systems, including with moving objects, the signal propagation channels between the receiver and the data transmitter are multipath and non-stationary. The effectiveness of communication systems is largely determined by the ability of time-frequency synchronization algorithms to provide in multipath non-stationary channels the necessary accuracy in estimating the temporal position of a signal and the frequency mismatch between the frequency of the input signal and the frequency of the reference oscillator.

For the initial time-frequency synchronization, a special signal is usually used - the preamble that precedes the information message. The preamble and the information message can be a signal with a code spreading (CDM - Code - Division Multiplex) or OFDM (Orthogonal Frequency Division Multiplexing) signal.

To generate a signal with code spreading, pseudo-random sequences (PSPs) are used. A CDM signal consists of a sequence of code symbols with a length of several chips. The PSP chip is the duration of one elementary PSP time interval.

An OFDM signal is a sequence of OFDM symbols. Each such symbol consists of two parts - a prefix and a multi-frequency information symbol. A multi-frequency information symbol is the sum of modulated harmonics. The prefix means a certain sequence of samples of the signal, which immediately precedes each multi-frequency information symbol and is a part of this symbol. As a rule, the prefix duration is less than the duration of the information symbol. The presence of a prefix during signal processing can reduce or completely eliminate intersymbol interference (IEEE Std 802.11a - 1999, Prokis J., Digital Communication. Translation from English. M: Radio and Communication, 2000, p. 593.).

There is a method of frequency and time synchronization described by Tufvesson F., Faulkne M., Hoeher P., Edfors O., OFDM Time and Frequency Synchronization by Spread Spectrum Pilot Technique // 8th IEEE Communication Theory Mini Conference in conjunction to ICC'99 , june 1999, p. 115-119. This article proposes a method of frequency and time synchronization for OFDM systems, which is based on the use of a continuous code sequence. The code sequence is added to the OFDM information signal or used separately as a preamble signal. This method of time and frequency synchronization is as follows.

The input signal is processed in several filters, consistent with various parts of the known code sequence. The output signals of matched filters are used to form an integrated decision function. Each term of the decisive function is the sum of the pair products of the responses of the matched filters to the corresponding adjacent complex conjugate responses of the matched filters.

The estimate of the time delay (position) of the input signal is determined by the position of the maximum squared module of the decisive function. An estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined by the value of the argument of the decision function at the point corresponding to the estimate of the time delay.

The described method involves a one-stage procedure of time-frequency synchronization. As a result, with large values of the possible frequency shift between the carrier frequency of the input signal and the frequency of the reference signal, when implementing the method, it is necessary to use filters that are consistent with shorter parts of the known code sequence. This leads to a deterioration in the accuracy of estimating the time delay and frequency detuning and is the main disadvantage of this synchronization method.

The known method of time-frequency synchronization described in the article Schmidi T.M., Sokh D.S., Robust Frequency and Timing Synchronization for OFDM // IEEE Tran. on corn, v. 45, No. 12, Dec. 1997, p. 1613-1621.

This article proposes a method for synchronizing signal parameters in OFDM (Orthogonal Frequency Division Multiplexing) systems, which is based on the reception of a preamble consisting of two OFDM symbols. In the synchronization process at the first stage, the temporal position of the signal is determined from the first symbol, and a rough estimation of the partial mismatch is carried out with an accuracy of n · π · T, n = 1.2 ..., T is the duration of the OFDM symbol. The final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is carried out in a second step using a second OFDM symbol.

The first OFDM symbol consists of two identical parts, which differ in phase shift reception. First, the complex decisive function of the first stage is formed as the product of the samples of the first part of the symbol and the corresponding complex conjugate samples of the second part of the symbol. The estimate of the time delay of the input signal is determined by the position of the maximum squared module of the decisive function of the first stage. A rough estimate of the frequency shift between the carrier of the input signal and the frequency of the reference signal is calculated by the value of the argument of the decision function of the first stage at the point corresponding to the estimate of the time delay.

To determine the final estimate of the frequency mismatch, a decisive function of the second stage is formed for all possible values of n using both OFDM symbols. The estimate of the parameter n is determined by the position of the maximum of the decisive function of the second stage.

The disadvantages of the described method is the low accuracy of estimating the temporal position of the signal due to the wide enough flat top of the decision function of the first stage, the width of which is equal to the duration of the OFDM symbol prefix. In addition, the disadvantage is the incomplete use of the preamble resource, namely the rejection of the use of the second OFDM symbol in estimating the temporal position of the signal. These disadvantages lead to low noise immunity of the time-frequency synchronization of the communication system.

Closest to the claimed solution is a method of time-frequency synchronization of a communication system and an algorithm for its implementation, given in the book Nee R. Prasad R., OFDM for Wireless Multimedia Communication, London: “Artech House”, 2000, chapter 4. Synchronization. 4.6. Synchronization using Special Training Symbols, pp. 86-88; chapter 10. Applications of OFDM. 10.5.4 Training, pp. 246-247.

This method of time-frequency synchronization of a communication system is as follows:

on the transmitting side, a digital video signal is formed, which consists of two parts: the first part is 10 short multi-frequency characters, the second part is 2 long multi-frequency characters and a prefix consisting of a long character part; filtering the generated digital video signal, performing its digital-to-analog conversion, transferring the signal to the carrier frequency, amplifying and transmitting it through the communication channel;

on the receiving side, the input signal is filtered, amplified, transferred to the video frequency, its analog-to-digital conversion and decimation are carried out, forming the input digital complex signal at the video frequency; time-frequency synchronization is carried out in two stages: at the first stage, a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined, which is done by filtering the generated input digital complex signal, consistent with one short multi-frequency symbol, forming complex responses of the first stage; calculate the squares of the modules of the complex responses of the first stage, forming the decisive function of the first stage; determine the temporary position of the local maxima of the decisive function of the first stage, exceeding a predetermined threshold of the first stage H1; remember the complex responses of the first stage, corresponding to the local maxima of the decisive function of the first stage; form a preliminary estimate of the frequency shift by the averaged phase difference of the complex responses of the first stage, corresponding to the local maxima of the decisive function of the first stage; at the second stage, the temporal position of the preamble is estimated and the final estimate of the frequency shift between the carrier of the input signal and the frequency of the reference signal is made, for which the phase of the input digital complex signal is adjusted at the interval of the second stage, taking into account a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal ; filtering the corrected input digital complex signal, consistent with one long multi-frequency symbol, forming complex responses of the second stage; calculate the squares of the modules of the complex responses of the second stage, forming the decisive function of the second stage; comparing the values of the decisive function of the second stage with a given threshold of the second stage H2, if the threshold is not exceeded, the preamble is assumed to be undetected; if the threshold of the second stage H2 is exceeded, the preamble is considered to be detected, then an estimate of the temporary position of the preamble is determined by the temporary position of the first excess of the threshold of the second stage H2; determine the temporary position of the local maxima of the decisive function of the second stage, exceeding a predetermined threshold of the second stage H2; determining an additional estimate of the frequency shift by the phase difference of the two complex responses of the second stage, corresponding to the local maxima of the decisive function of the second stage; determine the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal as the sum of the preliminary and additional estimates of the frequency shift.

The assessment of the temporary position of the preamble, namely the beginning of the preamble, is determined to be equal to the difference in the temporary position of the first exceeding the threshold of the second stage H2 and the sum of the durations of the first part of the preamble and the prefix.

An additional estimate of the frequency shift is determined, for example, as the ratio of the phase difference of the adjacent complex responses of the second stage to the duration of a long multi-frequency symbol.

Note that in the above-mentioned information source, the structural diagram of the time-frequency synchronization device of the communication system is not shown. However, from the description of the algorithm, you can imagine a device that implements the prototype method. The prototype device on the transmitting side is made in figure 1, the prototype device on the receiving side is made in figure 2.

The prototype device on the transmitting side (Fig. 1) comprises a clock 1, a demultiplexer 2, a first counter 3 forming the number of short multi-frequency symbols, a second counter 4 forming a short multi-frequency symbol, a first read-only memory 5, and a third counter 6 forming a long multi-frequency symbol, the fourth counter 7, forming the number of long multi-frequency symbols, the second read-only memory 8, the adder 9, the data generating unit 10, the transmitting path 11, while the clock input RA 1 is the input of the device, the output of the clock generator 1 is connected to the first input of the demultiplexer 2, the second input of which is connected to the output of the first counter 3, the first output of the demultiplexer 2 is connected to the input of the second counter 4, the output of which is connected to the inputs of the first counter 3 and the first permanent memory 5, the output of the first read-only memory 5 is connected to the first input of the adder 9, the second output of the demultiplexer 2 is connected to the input of the third counter 6, the output of which is connected to the inputs of the second read only memory 8 and the fourth counter 7, the output of which is connected to the third input of the demultiplexer 2 and the input of the data generation unit 10, the output of which is connected to the third input of the adder 9, the second input of which is connected to the output of the second read-only memory 8, the output of the adder 9 is connected to the input of the transmission path 11, the output of which is the output of the device.

The prototype device on the receiving side (Fig. 2) contains a receiving path 12, the first 13 and second 14 matched filters, performing the filtering of the generated digital input complex signal and forming the complex responses of the first stage, the first 15 and the first 15, consistent with one short multi-frequency symbol the second 16 multipliers, the first adder 17, the complex multiplier 18, the harmonic generation unit 19, the frequency shift calculation unit 20, the first comparison unit with a threshold 21, the control unit 22, the clock 23, the third 24 and fourth 25 matched filters that filter the corrected input digital complex signal and formulate the complex responses of the second stage, the third 26 and fourth 27 multipliers, the second adder 28, the second comparison block with threshold 29, the block calculating an additional frequency shift 30 and the third adder 31, while the input of the receive path 12 is the input of the device, the first output of the receive path 12 is connected to the input of the first filter 13 and the first input of the complex multiplier 18, the second output of the receiving path 12 is connected to the input of the second matched filter 14 and the second input of the complex multiplier 18, the output of the first matched filter 13 is connected to the first and second inputs of the first multiplier 15 and the second input of the frequency shift calculation unit 20, the output of the second matched filter 14 is connected to the first and second inputs of the second multiplier 16 and the third input of the frequency shift calculation unit 20, the outputs of the first 15 and second 16 multipliers are connected inens, respectively, with the first and second inputs of the first adder 17, the output of which is connected to the first input of the first comparison unit with a threshold 21, the second input of which is combined with the fourth input of the frequency shift calculation unit 20 and connected to the first output of the control unit 22, the output of the first comparison unit with threshold 21 is connected to the first input of the frequency shift calculation unit 20 and to the second input of the control unit 22, the fifth output of which is connected to the fifth input of the frequency shift calculation unit 20, the output of the frequency shift calculation unit 20 is connected n with the first input of the harmonic generation unit 19 and the first input of the third adder 31, the second input of the harmonic generation unit 19 is combined with the third input of the control unit 22 and connected to the output of the clock generator 23, the first and second outputs of the harmonic generation unit 18 are connected respectively to the third and fourth the inputs of the complex multiplier 18, the first and second outputs of which are connected respectively to the inputs of the third 24 and fourth 25 matched filters, the output of the third matched filter 24 is connected to the first and watts by the third inputs of the third multiplier 26 and the first input of the additional frequency shift calculation unit 30, the output of the fourth matched filter 25 is connected to the first and second inputs of the fourth multiplier 27 and the second input of the additional frequency shift calculation unit 30, the outputs of the third 26 and fourth 27 multipliers are connected respectively to the first and second inputs of the second adder 28, the output of which is connected to the first input of the second comparison unit with a threshold 29, the second input of which is connected to the second output of the control unit 22 the fifth input of the additional frequency shift calculation unit 30, the output of the second comparison unit with a threshold 29 is connected to the third input of the additional frequency shift calculation unit 30 and the first input of the control unit 22, the third output of which is connected to the fourth input of the additional frequency shift calculation unit 30, the fourth output of the unit control is the first output of the device, the output of the unit for calculating the additional frequency shift 30 is connected to the second input of the third adder 31, the output of the third adder 31 is the second Odom device.

Device frequency-time synchronization of a communication system (on the transmitting side, figure 1) works as follows.

Clock 1, demultiplexer 2, first counter 3 forming the number of short multi-frequency symbols, second counter 4 forming a short multi-frequency symbol, third counter 6 forming a long multi-frequency symbol, fourth counter 7 forming the number of long multi-frequency symbols, first read-only memory 5 in which a short multi-frequency symbol is recorded, a second read-only memory 8 in which a long multi-frequency symbol is recorded, and an adder 9 of the described transmission device is used Preamble is used to generate the digital video signal, and the data generating unit 10 is used to generate the information signal of the communication system. The temporal structure of the preamble signal is predetermined.

The generated preamble signal and the data signal are transmitted through the transmitting path 11 to the communication channel.

When generating and transmitting the preamble signal and the information signal, a time division is performed. The information signal begins to enter the transmitting path by the signal of the end of the procedure for generating the preamble signal.

The procedure for generating the preamble signal is as follows. The clock generator 1, on a command to control the start or repeat transmission of the preamble signal supplied to its input, generates clock pulses. From the output of the clock generator 1, the clock pulses are fed to the first input of the demultiplexer 2, the second controlled input of which from the output of the first counter 3 receives a switching signal. At the third controlled input of the demultiplexer 2 and at the controlled input of the data generation unit 10, the output signal of the end of the preamble is received from the output of the fourth counter 7.

The initial state of the switching signals is set so that initially the clock pulses from the first output of the demultiplexer 2 are fed to the input of the second counter 4. This counter is programmed in such a way that a signal corresponding to the addresses of the current elements of the short multi-frequency symbol is formed at its outputs, and the signal is at the highest level , equal, for example, to a logical unit, indicates the end of the reading of the next short multi-frequency symbol.

The address signals from the output of the second counter 4 to the input of the first read-only memory 5 carry out a cyclic reading of the current elements of the short symbol, which are received from the output of the first read-only memory 5 to the first input of the adder 9 and then from its output go to the input of the transmitting path 11. The signal of reading the next short multi-frequency symbol, which is fed to the input of the first counter 3 from the output of the second counter 4, accumulate the number of read cycles and form iruyut at the output of the first counter control signal 3 of, for example, a logic one if the number of cycles equal to the predetermined number N = 10 in the short preamble symbols multifrequency signal.

At the same time, during the time interval for the formation of a given number of short multi-frequency symbols from the output of the second read-only memory 8 to the second input of the adder 9 and from the data generation unit 10 to the third input of the adder 9, signals equal to zero are read.

According to the generated control signal, which comes from the output of the first counter 3 to the second input of the demultiplexer 2, the commutation of the demultiplexer 2 is carried out, and clock pulses begin to arrive only from the second output of the demultiplexer 2 to the input of the third counter 6.

The third counter 6 is programmed in such a way that a signal corresponding to the addresses of the current elements of the long multi-frequency symbol is generated at its outputs, and a signal at the high order, equal, for example, to a logical unit, indicates the end of reading of the next long symbol. Initially, the third counter 6 is set so that the output signal matches the beginning of the prefix.

According to the address signals from the output of the third counter 6 to the input of the second read-only memory 8, the current elements of the long multi-frequency symbol are cyclically read, which are fed to the second input of the adder 9. According to the readout signal of the next long symbol, which is input to the fourth counter 7 from the output of the third counter 6, accumulate the number of read cycles and form at the output of the fourth counter 7 a control signal equal, for example, to a logical unit, if the number of cycles equal to three - the prefix and two long multi-frequency symbols in the preamble signal.

At the same time, during the time interval for the formation of a given number of long multi-frequency symbols coming from the output of the first read-only memory 5 to the first input of the adder 9 and from the output of the data generation unit 10 to the third input of the adder 9, signals equal to zero are read.

By the signal of the end of the formation of a predetermined number of long multi-frequency symbols, which is supplied to the output of the fourth counter 7 to the third input of the demultiplexer 2 and to the controlled input of the data forming unit 10, switching is performed in such a way that from the output of the first read-only memory 5 to the first input of the adder 9 and from the output of the second read-only memory 8 to the second input of the adder 9, read signals equal to zero, and from the output of the data generation unit 10 to the third input of the adder 9 read information ion signal.

From the output of the adder 9, the generated digital video signal enters the transmitting path 11. In the transmitting path 11, the preamble signal and the information signal are converted by performing a standard sequence of operations (filtering, digital-to-analog conversion, modulation, transfer to the carrier frequency, amplification, etc.), and transmit the received signal (message) to the communication channel.

Device frequency-time synchronization of a communication system (on the receiving side, figure 2) works as follows.

On the receiving side in the receiving path 12, the input signal is pre-filtered, amplified, transferred to the video frequency, its analog-to-digital conversion, decimation, etc. As a result, an input digital complex signal is generated at the video frequency. For time-frequency synchronization, which consists of two stages, a preamble signal is used. In this case, at the first stage, a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined. At the second stage, the temporal position of the preamble is estimated and the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is performed.

At the first stage, the in-phase and quadrature components of the input digital complex signal from the first and second outputs of the receiving path 12 are received respectively at the inputs of the first 13 and second 14 matched filters and at the first and second inputs of the complex multiplier 18.

In the first 13 and second 14 matched filters, at the first stage, filtering, respectively, in-phase and quadrature components of the input digital complex signal, consistent with one short multi-frequency symbol, is carried out and responses are generated for the in-phase and quadrature components of the input digital complex signal, which are received respectively at the first and second inputs of the first 15 and the second 16 multipliers and the second and third inputs of the unit for calculating the frequency shift 20. In the first 15 and second 16 multipliers calculate response frames for the in-phase and quadrature components of the input digital complex signal of the first stage, which are supplied to the first and second inputs of the first adder 17. In the first adder 17, by summing the corresponding squares of the responses of the in-phase and quadrature components of the input digital complex signal, the squares of the modules of the complex responses of the first stage are calculated forming the decisive function of the first stage. The responses of the first stage come from the output of the first adder 17 to the first input of the first block of comparison with threshold 21.

In the first comparison unit with the threshold 21, the summation results from the output of the first adder 17 are successively compared with the threshold of the first stage H1. The comparison results from the output of the first comparison unit with a threshold of 21 are fed to the first input of the frequency shift calculation unit 20 and to the second input of the control unit 22.

At the second input of the first comparison unit with a threshold 21 and at the fourth input of the frequency shift calculation unit 20, a control signal is received from the first output of the control unit 22, corresponding to the end of the time domain exceeding the decision function values of the first stage of the threshold H1. Using this signal, in the first block of comparison with threshold 21, the initial (initial) value of the threshold of the first stage is set, and the in-phase and quadrature components of the complex responses of the first stage corresponding to the local maximum of the decision function of the first stage (received in the second and third the inputs of block 20 from the first 13 and second 14 matched filters).

In the block for calculating the frequency shift 20 by the signal of exceeding the threshold of the first stage and by the control signal of the end of the time domain of exceeding by the values of the decisive function of the first stage of the threshold H1, temporary positions corresponding to the local maxima of the decisive function of the first stage are determined.

The signal of the end of the reception of the first part of the preamble, which comes from the fifth output of the control unit 22 to the fifth input of the frequency shift calculation unit 20, in block 20, according to the in-phase and quadrature components of the complex responses of the first stage, corresponding to the local maxima of the decisive function of the first stage, a preliminary estimate of the frequency shear. A preliminary estimate of the frequency shift is formed, for example, as the ratio of the averaged phase difference of the complex responses of the first stage corresponding to local maxima to the duration of a short multi-frequency symbol. The averaged phase difference is formed, for example, as follows. For temporary positions of local maxima of the decisive function of the first stage, the sum of the products of pairs of current complex responses and previous complex conjugate responses is formed. The value of the argument of the obtained complex number is equal to the averaged phase difference. Moreover, the ratio of the averaged phase difference to the duration of a short multi-frequency symbol is equal to a preliminary estimate of the frequency shift.

Evaluation of the preliminary frequency shift comes from the output of the frequency shift calculation unit 20 to the first input of the harmonic generation unit 19 and to the first input of the third adder 31 and corresponds to the value of the “rough” estimate of the frequency detuning. At the second input of the harmonic generation unit 19 and at the third input of the control unit 22, a clock signal is supplied from the output of the clock generator 23.

In the harmonic generation unit 19, according to a preliminary estimate of the frequency shift and the signal from the clock generator 23, a complex unit amplitude multiplier is formed, the phase of which is equal to the product of the preliminary estimate of the frequency shift by the temporary position of the current samples, which corresponds to the standard exponential representation of the complex factor. On the other hand, a complex factor can be equivalently formed as an in-phase and a quadrature component. In this case, the in-phase part of the complex factor is equal to the cosine, and the imaginary part is the sine of the argument, which is equal to the product of the preliminary estimate of the frequency shift by the temporary position of the current samples. This representation of the complex factor is easily implemented in a functional converter based on a memory device in which the values of the corresponding samples of the sine and cosine functions are recorded.

The generated quadrature components of the complex factor from the first and second outputs of the harmonics forming unit 19 are supplied to the third and fourth inputs of the complex multiplier 18, respectively.

In the complex multiplier 18, the phase of the input digital complex signal for the second synchronization stage is adjusted taking into account a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal obtained in the first stage. To do this, in the complex multiplier 18 carry out the well-known operation of multiplying the samples of the input digital complex signal by a complex factor.

The in-phase and quadrature components of the adjusted input digital complex signal from the first and second outputs of the complex multiplier 18 are received respectively at the inputs of the third 24 and fourth 25 matched filters.

In the third 24 and fourth 25 matched filters for the in-phase and quadrature components of the input corrected digital complex signal, filtering is matched with one long multi-frequency symbol, and the in-phase and quadrature responses of the second stage are respectively generated. The generated in-phase and quadrature components of the responses of the second stage from the outputs of the third 24 and fourth 25 matched filters are received respectively at the first and second inputs of the third 26 (in-phase) and fourth 27 (quadrature) multipliers and at the first and second inputs of the block for calculating the additional frequency shift 30. B the third 26 and fourth 27 multipliers form respectively the squares of the in-phase and quadrature components of the responses of the second stage, which are fed to the first and second inputs of the second adder 28, where calculating a summation of the squares of the moduli of the complex response of the second stage to give a crucial feature of the second stage. The calculated squares of the modules of the complex responses of the second stage from the output of the second adder 28 go to the first input of the second block of comparison with the threshold 29.

In the second block of comparison with the threshold 29, the squares of the modules of the complex responses of the second stage are compared with the threshold of the second stage H2. The result of the comparison from the output of the second comparison unit with a threshold 29 is fed to the first input of the control unit 22 and to the third input of the calculation unit for the additional frequency shift 30.

If the threshold H2 is not exceeded, the preamble is assumed to be undetected and the frequency-time synchronization procedure is continued.

If the threshold is exceeded, H2 is assumed to be detected. In this case, the signals for exceeding the threshold in the control unit 22 determine the estimate of the temporary position of the preamble as the temporary position of the first excess of the threshold of the second stage H2. The resulting estimate from the fourth output of the control unit 22 is supplied to the first output of the device.

The final assessment of the temporary position of the preamble is determined to be equal to the difference in the temporary position of the first exceeding the threshold of the second stage H2 and the sum of the durations of the first part of the preamble and the prefix.

From the second output of the control unit 22, to the second input of the second comparison unit with a threshold 29 and to the fifth input of the calculation unit for the additional frequency shift 30, a signal is received for the end of reception of the second part of the preamble, which is, for example, a logical unit.

In the block for calculating the additional frequency shift 30, the temporal positions corresponding to the local maxima of the decisive function of the second stage are determined by the values of the threshold exceeding signal and the control signal of the end of the time domain exceeding the threshold function of the threshold of the second stage arriving at its fourth input from the third output of the control unit 22.

In the block for calculating the additional frequency shift 30 by the signal of the end of the reception of the second part of the preamble, the in-phase and quadrature components of the complex responses of the second stage, corresponding to the local maxima of the decisive function of the second stage, are used to determine the additional frequency shift.

Evaluation is performed, for example, as follows. The phase difference of the two complex responses of the second stage corresponding to local maxima is formed as the product of the complex conjugate response to the subsequent complex response. As a result, the argument of the obtained complex number corresponds to an estimate of the additional phase shift. An additional estimate of the frequency shift is determined, for example, as the ratio of the estimate of the additional phase shift to the duration of the long multi-frequency symbol. An additional estimate of the frequency shift from the output of block 30 goes to the second input of the third adder 31. In the third adder 31, the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined as the sum of the preliminary and additional estimates of the frequency shift. The resulting final assessment from the output of the third adder 31 is fed to the second output of the device.

The disadvantages of the prototype method and the device include the rejection of a preliminary assessment of the temporary position of the signal and, as a result, from the use of incoherent processing in the first stage. This drawback leads to insufficiently high noise immunity of the estimation of the temporary position and frequency mismatch, especially in conditions of multipath signal propagation. The presence of a prefix in the second part of the preamble may lead to an abnormal error in assessing the temporary position in the second stage.

The problem that the proposed invention solves is to increase the noise immunity of the time-frequency synchronization of the communication system.

This problem is solved in that in the method of time-frequency synchronization of a communication system, namely, that

on the transmitting side:

form a digital video signal, which consists of two parts,

filtering the generated digital video signal, performing its digital-to-analog conversion, transferring the signal to the carrier frequency, amplifying and transmitting it through the communication channel,

on the receiving side:

the input signal is filtered, amplified, transferred to the video frequency, its analog-to-digital conversion and decimation are carried out, forming the input digital complex signal at the video frequency,

time-frequency synchronization is performed in two stages:

at the first stage, a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined, for which

- filtering the generated input digital complex signal, forming complex responses of the first stage,

- calculate the squares of the modules of the complex responses of the first stage,

- carry out a comparison with a given threshold of the first stage,

- determine a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal,

at the second stage, the temporal position of the preamble is estimated and the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is performed, for which

- adjust the phase of the input digital complex signal on the interval of the second stage, taking into account a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal,

- carry out a coordinated filtering of the adjusted input digital complex signal, forming the complex responses of the second stage,

- calculate the squares of the modules of the complex responses of the second stage,

- carry out a comparison with a given threshold of the second stage, if the threshold is not exceeded, the preamble is assumed to be undetected,

- when the threshold of the second stage is exceeded, the preamble is considered to be detected, then the final estimate of the temporary position of the preamble is determined by the temporary position of the first excess of the threshold of the second stage,

- determine the temporary position corresponding to the maximum value of the square of the integrated response module of the second stage,

- determine an additional estimate of the frequency shift by the phase difference of the complex responses of the second stage,

determine the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal as the sum of the preliminary and additional estimates of the frequency shift,

according to the invention:

on the transmitting side:

the digital video signal, consisting of two parts, is formed so that the parts of the digital video signal are separated by a pause of a given duration, the first part being N short code sequences, and the second part M long code sequences,

on the receiving side:

when performing the first stage of the time-frequency synchronization, a priori time interval of the temporal position of the preamble for the second stage is determined,

to determine a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal in the first stage:

- filtering the input generated digital complex signal, consistent with one short code sequence,

- calculate the sum of N squares of the modules of the complex responses of the first stage, taken with an interval equal to the duration of the short code sequence,

- with the given threshold of the first stage, the obtained sums of N squares of the modules of the complex responses of the first stage are compared, when the threshold is exceeded:

- the temporary position of the beginning of the preamble corresponding to the amount received is considered the current temporary position of the preamble,

- form the current estimate of the frequency shift by the averaged phase difference of adjacent complex responses of the first stage from the n-th to the (N-n + 1) -th corresponding to the summation terms of the N squares of the modules of the complex responses of the first stage, where n is an integer,

- the threshold of the first stage is set equal to the result of the summation;

determine the beginning of the a priori interval of the temporary position of the second part of the preamble by the temporary position of the preamble corresponding to the first excess of the threshold of the first stage,

determine the end of the a priori interval of the temporary position of the second part of the preamble according to the current temporary position of the preamble,

a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined by the time the second stage begins as the current estimate of the frequency shift,

by the time the a priori time interval of the second position of the preamble begins, the threshold of the first stage is assumed to be equal to the initial value, and the current temporary position of the preamble is considered to be undefined,

in the second stage:

filtering the corrected input generated digital complex signal, consistent with one long code sequence,

the squares of the modules of the complex responses of the second stage are compared with a predetermined threshold of the second stage on an a priori interval of the time position of the second part of the preamble,

an additional estimate of the frequency shift is determined by the averaged phase difference M of the complex responses of the second stage: the complex response of the second stage, corresponding to the maximum value of the square of the module, and the responses of the second stage, separated from this response by an integer of the length of the interval of the long code sequence from 1 to (M-1 )

A current estimate of the frequency shift is formed, for example, as the ratio of the averaged phase difference of the complex responses of the first stage to the duration of a short code sequence.

The beginning of the a priori interval of the time position of the second part of the preamble is determined, for example, to be equal to the sum of the time position of the preamble corresponding to the first exceeding the threshold of the first stage, the duration of (N-2) -x short code sequences and the duration of the pause.

The end of the a priori interval of the time position of the second part of the preamble is determined, for example, equal to the sum of the current time position of the preamble, the duration of (N + 3) -x short code sequences and the duration of the pause.

The phase of the input digital complex signal in the interval of operation of the second stage is adjusted by multiplying the samples of the input digital complex signal by a complex factor of unit amplitude, the phase of which is equal to the product of the preliminary estimate of the frequency shift by the time positions of the samples.

An additional estimate of the frequency shift is determined, for example, as the ratio of the averaged phase difference of the complex responses of the second stage to the duration of a long code sequence.

The final assessment of the temporary position of the preamble, namely the beginning of the preamble, is determined equal to the difference in the temporary position of the first exceeding the threshold of the second stage and the sum of the durations of the first part of the preamble and pause.

The problem is also solved by the fact that in the device of the time-frequency synchronization of a communication system containing

on the transmitting side: a clock generator, a demultiplexer, a first counter, a second counter, a first read-only memory, a third counter, a fourth counter, a second read-only memory, an adder, a data generation unit transmitting a path, the input of the clock being the input of the device, the output the clock is connected to the first input of the demultiplexer, which is the input of the clock signal, the second input of the demultiplexer, which is the input controlled, is connected to the output of the first counter, the first output of the demultiplexer is connected to the input of the second counter, the output of which is connected to the inputs of the first counter and the first read-only memory, the output of the first read-only memory is connected to the first input of the adder, the second output of the demultiplexer is connected to the input of the third counter, the output of which is connected to the inputs the second read-only memory and the fourth counter, the output of which is connected to the third input of the demultiplexer, which is a controllable input ohm, and the input of the data forming unit, the output of which is connected to the third input of the adder, the second input of which is connected to the output of the second read-only memory device, the output of the adder is connected to the input of the transmitting path, the output of which is the output of the device,

on the receiving side:

the receiving path, which generates an input digital complex signal at the video frequency at the outputs, the first and second matched filters that filter the corresponding in-phase and quadrature components of the generated digital input complex signal and generate complex responses of the first stage, the first and second multipliers, the first adder, complex multiplier, block harmonics generation, frequency shift calculation unit, first threshold comparison unit, control unit, clock generator forming the clock signal, the third and fourth matched filters that filter the adjusted input digital complex signal and generate complex responses of the second stage, the third and fourth multipliers, the second adder, the second threshold comparison unit, the additional frequency shift calculator and the third adder, the input of the receiving path is the input of the device, the first output of the receiving path is connected to the input of the first matched filter and the first input of the complex multiply sprucing up, the second output of the receiving path is connected to the input of the second matched filter and the second input of the complex multiplier, the outputs of the first and second multipliers are connected respectively to the first and second inputs of the first adder, the output of which is connected to the first input of the first comparison unit with a threshold, the second input of which is connected to the first output of the control unit, the output of the first comparison unit with a threshold is connected to the first input of the frequency shift calculation unit, the output of which is connected to the first input of the unit for generating ha monics and the first input of the third adder, the second input of the harmonic generation unit is connected to the output of the clock generator, the first and second outputs of the harmonic generation unit are connected respectively to the third and fourth inputs of the complex multiplier, the first and second outputs of which are connected respectively to the inputs of the third and fourth matched filters, the output of the third matched filter is connected to the first and second inputs of the third multiplier and the first input of the additional frequency shift calculation unit, the output of the fourth matched filter is connected to the first and second inputs of the fourth multiplier and the second input of the additional frequency shift calculation unit, the outputs of the third and fourth multipliers are connected respectively to the first and second inputs of the second adder, the output of which is connected to the first input of the second comparison unit with a threshold, the second input which is connected to the second output of the control unit, forming at this output the signal of the end of the second stage, the output of the second comparison unit with a threshold is connected to the third the input of the unit for calculating the additional frequency shift and the first input of the control unit, the third output of which is connected to the fourth input of the unit for calculating the additional frequency shift, the fourth output of the control unit is the first output of the device and the output of the signal for the final assessment of the temporary position of the preamble, the first output of the unit for calculating the additional frequency shift, forming an additional estimate of the frequency shift at the first output, connected to the second input of the third adder, forming a signal at the output l final estimate of the frequency offset, the output of the third adder is the output of the second device,

according to the invention

on the transmitting side:

the first counter is designed in such a way that allows the number of short code sequences to be counted in the preamble signal, generating an output clock control signal for a given number of N read cycles,

the second counter is designed in such a way that allows counting the number of clock pulses in the signal of the short code sequence of the preamble, generating an output signal corresponding to the addresses of the current elements of the short code sequence, the third counter is designed in such a way that allows counting the number of the preamble in the signal of the long code sequence clock pulses, forming the output signal corresponding to the addresses of the current elements of a long code sequence, the fourth with the meter is designed in such a way that it allows the number of long code sequences to be counted in the preamble signal, generating a control signal of clock pulses at a given number M of read cycles and a signal of the end of the preamble, the first read-only memory is designed to store short code sequence samples , the second read-only memory is designed in such a way that allows you to store samples of a long code sequence, the account is entered IR pause performing the interval count pause preamble number of clock pulses forming the signal at the output end of the pause, the pause counter input connected to the third output of the demultiplexer, and an output - to a fourth input of the demultiplexer, which is a control input

on the receiving side introduced:

the first and second delay lines, N-1 of the first and N-1 of the second multipliers, a block for determining the boundaries of the a priori interval, generating at the first output a signal for the beginning of the a priori time interval of the second part of the preamble, and at the second output, the signal for the end of the a priori time interval of the second part preambles, wherein the input of the first delay line is connected to the output of the first matched filter, the input of the second delay line is connected to the output of the second matched filter, the first and second matched filters with agreed with a short code sequence, N outputs of the first delay line are connected to their respective N second inputs of the frequency shift calculation unit and to the first and second inputs of their corresponding N first multipliers, N outputs of the second delay line are connected to their corresponding N third inputs of the frequency shift calculation unit and with the first and second inputs of the corresponding N second multipliers, the outputs N-1 of the first multipliers are connected to N-1 by additional first inputs of the first adder, the outputs N-1 of the second n multipliers are connected to N-1 by additional second inputs of the first adder, the output of the clock generator is connected to the fifth input of the block for calculating the additional frequency shift and the first input of the block for determining the boundaries of the a priori interval, the second input of which is connected to the output of the first block for comparison with the threshold, the first output of the block for determining the boundaries a priori interval is connected to the second input of the control unit and the third input of the first block comparing with a threshold, the second output of the block determining the boundaries of the a priori interval is connected n with the third input of the control unit, forming a control signal at the first output that determines the moment of completion or restart of the first stage, at the third output - the signal that the threshold of the second stage is exceeded, at the fifth output - the signal of the end of the a priori interval of the second part of the preamble, the fifth output of the control unit connected to the sixth input of the additional frequency shift calculation unit, at the sixth output, an identification signal for the a priori interval of the second part of the preamble, the sixth output of the control unit is connected to the third m the input of the second comparison unit with a threshold, the fourth input of the control unit is connected to the second output of the unit for calculating the additional frequency shift.

The inventive method of time-frequency synchronization of a communication system and a device for its implementation have significant differences from the closest analogues found when searching from the prior art.

These differences are as follows: the temporal position of the preamble signal is evaluated in two stages, and at the first stage, they form a decisive function with a wide useful response, which increases the likelihood of capture (a successful rough estimate of the temporal position), and at the second stage, they form a decisive function with a narrow useful response that allows you to get an accurate estimate of the temporal position of the preamble signal. The frequency shift estimate is also formed in two stages, and the quality of this estimate is high, because it is based on a qualitative assessment of the temporary position.

In fact, in the present invention, a two-stage joint assessment of the temporal position and frequency shift of the preamble signal is carried out, and due to the selected type of preamble signal, high accuracy of the estimated parameters is achieved.

The listed features of the proposed method and device for its implementation both on the transmitting side and on the receiving side are different from the closest analogues identified when searching from the prior art, therefore, the claimed solutions satisfy the patentability condition of the invention of “novelty”.

Analysis of the prior art for compliance of the claimed solutions with the condition of patentability of the invention “inventive step” showed that the known technical solutions do not allow to provide the required level of noise immunity for communication systems. And the claimed method and device by improving the quality of the time-frequency synchronization increase the noise immunity of the communication system, therefore, we can conclude that the claimed technical solutions meet the condition of patentability “inventive step”.

All the features of the claimed device of the time-frequency synchronization of the communication system allows you to fully implement the features of the proposed method, because The claimed inventions are so interconnected that they form a single inventive concept.

The invention is illustrated by examples and drawings:

figure 1 is a structural diagram of a device of the prototype on the transmitting side,

figure 2 is a structural diagram of a prototype device on the receiving side;

figure 3 is a structural diagram of the inventive device on the transmitting side;

figure 4 is a structural diagram of the inventive device on the receiving side;

figure 5 is a structural diagram of a block for determining the boundaries of the a priori interval 35, shown as an example of execution;

Fig.6 is a structural diagram of a comparison unit with a threshold of 21 and 29, is shown as an example of execution;

Fig.7 is a structural diagram of a unit for calculating an additional frequency shift 30, is given as an example of execution;

on Fig - control unit 22, shown as an example implementation.

The inventive device of the time-frequency synchronization of the communication system contains on the transmitting side (Fig. 3) a clock 1, a demultiplexer 2, a first counter 3, a second counter 4, a first read-only memory 5, a third counter 6, a fourth counter 7, and a second read-only device 8, adder 9, data generating unit 10, transmitting path 11, while the input of the clock generator 1 is the input of the device, the output of the clock generator 1 is connected to the first input of the demultiplexer 2, the second input of which is connected to the output m of the first counter 3, the first output of the demultiplexer 2 is connected to the input of the second counter 4, the output of which is connected to the inputs of the first counter 3 and the first read-only memory 5, the output of the first read-only memory 5 is connected to the first input of the adder 9, the second output of the demultiplexer 2 is connected to the input of the third counter 6, the output of which is connected to the inputs of the second read-only memory 8 and the fourth counter 7, the output of which is connected to the third input of the demultiplexer 2 and the input of the form block data 10, the output of which is connected to the third input of the adder 9, the second input of which is connected to the output of the second read-only memory 8, the output of the adder 9 is connected to the input of the transmission path 11, the output of which is the output of the device, according to the invention further comprises a pause counter 32, performing the accumulation of clock pulses of a given duration, forming the output signal control the end of the pause, the input of the pause counter is connected to the third output of the demultiplexer, and the output - the fourth input of the demultiplexer; on the receiving side: the receiving path 12, which generates an input digital complex signal at the video frequency at the outputs, the first 13 and second 14 matched filters that filter the in-phase and quadrature components of the generated digital complex signal, respectively, and form the complex responses of the first stage, the first 151 and second 161 multipliers, the first adder 17, a complex multiplier 18, a harmonic generation unit 19, a frequency shift calculation unit 20, a first comparison unit with a threshold 21, a control unit 22, a clock generator 23, which generates a clock signal at the output, the third 24 and fourth 25 matched filters that filter the adjusted input digital complex signal and generate complex responses of the second stage, the third 26 and fourth 27 multipliers, the second adder 28, the second comparison unit with threshold 29, the calculation unit for the additional frequency shift 30 and the third adder 31, while the input of the receive path 12 is the input of the device, the first output of the receive path 12 is connected to the input of the first filter 13 and the first input of the complex multiplier 18, the second output of the receiving path 12 is connected to the input of the second matched filter 14 and the second input of the complex multiplier 18, the outputs of the first 151 and second 161 multipliers are connected respectively to the first and second inputs of the first adder 17, the output of which is connected with the first input of the first comparison unit with a threshold 21, the second input of which is connected to the first output of the control unit 22, the output of the first comparison unit with a threshold 21 is connected to the first input of the calculation unit frequently a sharp shift 20, the output of which is connected to the first input of the harmonic generation unit 19 and the first input of the third adder 31, the second input of the harmonic generation unit 19 is connected to the output of the clock generator 23, the first and second outputs of the harmonic generation unit 19 are connected respectively to the third and fourth inputs of the complex a multiplier 18, the first and second outputs of which are connected respectively to the inputs of the third 24 and fourth 25 matched filters, the output of the third matched filter 24 is connected to the first and second input by the third multiplier 26 and the first input of the additional frequency shift calculation unit 30, the output of the fourth matched filter 25 is connected to the first and second inputs of the fourth multiplier 27 and the second input of the additional frequency shift calculation unit 30, the outputs of the third 26 and fourth 27 multipliers are connected to the first and the second inputs of the second adder 28, the output of which is connected to the first input of the second comparison unit with a threshold 29, the second input of which is connected to the second output of the control unit 22, it is at this output the signal of the end of the second stage, the output of the second comparison unit with a threshold 29 is connected to the third input of the additional frequency shift calculation unit 30 and the first input of the control unit 22, the third output of which is connected to the fourth input of the additional frequency shift calculation unit 30, the fourth output of the unit control 22 is the first output of the device and the output of the signal for the final assessment of the temporary position of the preamble, the first output of the unit for calculating the additional frequency shift 30, forming at the first output de additional estimate of the frequency shift, connected to the second input of the third adder 31, which generates the final frequency shift estimate signal at the output, the output of the third adder is the second output of the device, according to the invention, the first 33 and second 34 delay lines, N-1 of the first 15 _N-1 and N-1 second 16 _N-1 multipliers, determination unit 35 a priori interval boundaries, forming on the first output start signal interval priori temporal position of the second part of the preamble, and the second output - ok signal starting an a priori time interval of the second part of the preamble, wherein the input of the first delay line 33 is connected to the output of the first matched filter 13, the input of the second delay line 34 is connected to the output of the second matched filter 14, while the first 13 and second 14 matched filters are matched with the short code by the sequence, N outputs of the first delay line 15 are connected to the corresponding N second inputs of the frequency shift calculating unit 20 and to the first and second inputs of the N first multipliers 15, N outputs of the second and delays 34 are connected to the N third inputs of the frequency shift calculation unit 20 and to the first and second inputs of the N second multipliers 16, the outputs N-1 of the first multipliers 15 are connected to N-1 by the additional first inputs of the first adder 17, the outputs N-1 of the second multipliers are connected with (N-1) additional second inputs of the first adder 17, the output of the clock generator 23 is connected to the fifth input of the unit for calculating the additional frequency shift 30 and the first input of the unit for determining the boundaries of the a priori interval 35, the second input of which is connected to the output ohm of the first comparison block with threshold 21, the first output of the block for determining the boundaries of the a priori interval 35 is connected to the second input of the control unit 22 and the third input of the first block of comparison with the threshold 21, the second output of the block for determining the boundaries of the a priori interval 35 is connected to the third input of the control unit 22 at the first output, a control signal that determines the moment of completion or restart of the first stage, at the third output - the signal that the threshold of the second stage is exceeded, at the fifth output - the signal of the a priori and interval of the second part of the preamble, the fifth output of the control unit 22 is connected to the sixth input of the additional frequency shift calculation unit 30, the sixth output is an identification signal of the a priori interval of the second part of the preamble, the sixth output of the control unit 22 is connected to the third input of the second comparison unit with a threshold of 29, the fourth the input of the control unit 22 is connected to the second output of the unit for calculating the additional frequency shift 30.

The block for determining the boundaries of the a priori interval 35 (Fig. 5) contains serially connected first register 36, first key 37 and first counter 38 forming the first arm, serially connected second register 39, second key 40 and second counter 41 forming the second arm, circuit I 42 and the circuit NOT 43, while the first and second inputs of the first 36 and second 39 registers and the first input of the AND circuit are combined to form the second input of the block for determining the boundaries of the a priori interval 35, the second inputs of the first 37 and second 40 keys are combined to form the first input of block 35 , out q the first counter 38 is the first output of block 35 and connected to the input of the circuit NOT 43 and the third input of the first register 36, the output of the second counter 41 is the second output of the block 35 and connected to the third input of the second register 39, the second input of the second counter 41 is connected to the output of the circuit And, the input of which is connected to the output of the circuit NOT 43.

The first 21 and second 29 blocks of comparison with the threshold are made equivalently, an example of their implementation is shown in Fig.6. The threshold comparison unit contains a comparator 42, a first key 43, a second key 44, a register 45 and a third key 46, while the first inputs of the comparator 42 and the second key 44 are combined to form the first input of the comparison unit with a threshold, which is a signal input, the second input the comparator 42 is connected to the output of the register 45, the output of the comparator 42 is connected to the first input of the first key 43, the second input of the first key 43 is controlled by the second input of the comparison unit with a threshold, the output of the first key 43 is the output of the comparison unit with a threshold and is connected from the second m the input of the second key 44, the output of which is connected to the input of the register 45 and the first input of the third key 46, the second input of which is the third input of the comparison unit with the threshold and is a controlled input, the third input of the third key 46 is the signal input of the initial threshold value (respectively, the first or second stage) and is formed inside the block.

The calculation unit for the additional frequency shift 30 is shown as an example of execution (Fig. 7) and contains: first 47, second 48, third 49 and fourth 50 registers, first 51, second 52, third 53, fourth 54 and fifth 55 keys, first 56 and the second 57 counters and the frequency shift calculation node 58, while the first inputs of the first register 47 and the second key 52 are combined to form the first input of the block 30, the first inputs of the second register 48 and the first key 51 are combined to form the second input of the block 30, the second inputs of the first register 47, the second register 48 and the first input of the first counter 56 ob are Din, forming the third input of block 30, the outputs of the first 47 and second 48 registers are connected respectively to the first inputs of the third 53 and fourth 54 keys, the second inputs of which are combined to form the fourth input of block 30, the first and second inputs of the fifth key 55 are respectively fifth and sixth the inputs of block 30, the output of the fifth key 55 is connected to the second input of the first counter 56, the output of the first counter 56 is connected to the input of the second counter 57 and the second inputs of the first 51 and second 52 keys, the outputs of the first 51 and third 53 keys are connected to the input third register 49, the outputs of the second 52 and fourth 54 keys are connected to the input of the fourth register 50, the outputs of the third 49 and fourth 50 registers are connected respectively to the first and second inputs of the frequency shift calculation unit 58, the output of which is the first output of block 30, the third input of the calculation unit frequency shift 58 is connected to the output of the second counter 57, the output of which is the second output of the block 30.

The control unit 22 (Fig. 8) is shown as an example of execution and contains: the first 59, the second 60 and the third 61 of the AND circuit, the first 62 and the second 63 of the NOT circuit, the OR circuit 64, the first 65 and second 66 pulse shapers and register 67, with this, the first input of the first circuit And 59 is the second input of the control unit 22, the first input of the second circuit And and the input of the second circuit are NOT combined, forming the third input of the block 22, the output of the second circuit is NOT connected to the second input of the first circuit And, the output of which is the sixth output of the block control 22 and is connected to the first input of the circuit OR 64, the second input is a cat the swarm is combined with the input of the first pulse shaper 65 and the second input of the second circuit And 60 and is connected to the output of the register 67, the output of which is the third output of the control unit 22, the first and second inputs of the register 67 are combined to form the first input of the control unit 22, the output of the OR circuit 64 connected to the input of the first circuit NOT 62 and the first input of the third circuit And 61, the output of the first circuit is NOT the first output of the control unit 22, the output of the first pulse shaper 65 is the fourth output of the control unit 22, the second input of the third circuit And 61 is I fourth input unit 22, and its output - the second output unit 22, the output of the second AND circuit 60 is connected to the input of the second pulse shaper 66, the output of which is the fifth output of the control unit 22.

Carry out the inventive method of time-frequency synchronization of a communication system as follows:

on the transmitting side:

- form a digital video signal consisting of two parts separated by a pause of a given duration,

the first part is N short code

sequences

the second part is M long code

sequences;

- filter the generated digital video signal, perform its digital-to-analog conversion, transfer the signal to the carrier frequency, amplify and transmit it through the communication channel;

on the receiving side, the input signal is filtered, amplified, transferred to the video frequency, its analog-to-digital conversion and decimation are carried out, forming the input digital complex signal at the video frequency;

- frequency-time synchronization is performed in two stages, while at the first stage, determine the a priori interval of the temporal position of the preamble for the second stage and a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal, for which

carry out the filtering of the generated input digital complex signal, consistent with one short code sequence, forming complex responses of the first stage,

calculate the squares of the modules of the complex responses of the first stage,

calculate the sum of N squares of the modules of the complex responses of the first stage, taken with an interval equal to the duration of the short code sequence,

compare the received amount with a given threshold of the first stage, if the threshold is exceeded:

the temporary position of the beginning of the preamble corresponding to the amount received is considered the current temporary position of the preamble,

form the current estimate of the frequency shift by the averaged phase difference of adjacent complex responses of the first stage from the n-th to the (N-n + 1) -th corresponding to the summation terms, where n is an integer,

the threshold of the first stage is set equal to the received amount;

determining the beginning of the a priori time interval of the second part of the preamble by the temporary position of the preamble corresponding to the first excess of the threshold of the first stage;

determine the end of the a priori interval of the temporary position of the second part of the preamble according to the current temporary position of the preamble;

by the time the second stage begins, a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined as the current estimate of the frequency shift;

by the time of the start of the a priori time interval of the second part of the preamble, the threshold of the first stage is assumed to be equal to the initial value, and the current temporary position of the preamble is considered to be undefined;

- at the second stage, the temporal position of the preamble is estimated and the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is performed, for which

adjust the phase of the input digital complex signal in the interval of operation of the second stage, taking into account a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal,

carry out a filtering of the corrected input digital complex signal, consistent with one long code sequence, forming complex responses of the second stage,

calculate the squares of the modules of the complex responses of the second stage,

comparing the squares of the modules of the complex responses of the second stage with a given threshold of the second stage on an a priori interval of the time position of the second part of the preamble, if the threshold is not exceeded, the preamble is considered undetected,

when the threshold of the second stage is exceeded, the preamble is considered to be detected, then

determine the final assessment of the temporary position of the preamble by the temporary position of the first excess of the threshold of the second stage,

on the a priori time interval of the second part of the preamble, determine the temporary position corresponding to the maximum value of the square of the complex response module of the second stage of the long code sequence,

determine an additional estimate of the frequency shift from the averaged phase difference M of the complex responses of the second stage:

the complex response of the second stage, corresponding to the maximum value of the square of the module, and the responses of the second stage, separated from this response by an integer of the duration of the interval of the long code sequence from 1 to (M-1),

determine the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal as the sum of the preliminary and additional estimates of the frequency shift.

A current estimate of the frequency shift is formed, for example, as the ratio of the averaged phase difference of the complex responses of the first stage to the duration of a short code sequence.

The beginning of the a priori interval of the time position of the second part of the preamble is determined, for example, to be equal to the sum of the time position of the preamble corresponding to the first exceeding the threshold of the first stage, the duration of (N-2) -x short code sequences and the duration of the pause.

The end of the a priori interval of the time position of the second part of the preamble is determined, for example, equal to the sum of the current time position of the preamble, the duration of (N + 3) -x short code sequences and the duration of the pause.

The phase of the input digital complex signal in the interval of operation of the second stage is adjusted by multiplying the samples of the input digital complex signal by a complex factor of unit amplitude, the phase of which is equal to the product of the preliminary estimate of the frequency shift by the time positions of the samples.

An additional estimate of the frequency shift is determined, for example, as the ratio of the averaged phase difference of the complex responses of the second stage to the duration of a long code sequence.

The final assessment of the temporary position of the preamble, namely the beginning of the preamble, is determined equal to the difference in the temporary position of the first exceeding the threshold of the second stage and the sum of the durations of the first part of the preamble and pause.

The inventive method is implemented on the device of the time-frequency synchronization of the communication system, the structural diagram of which is made in figure 3 and 4.

Consider the implementation of the proposed method on the transmitting side, using for this figure 3.

Clock generator 1, demultiplexer 2, first counter 3, second counter 4, third counter 6, fourth counter 7, pause counter 32 and adder 9 are used to generate the digital video signal of the preamble, and the data generating unit 10 is used to generate the information signal of the communication system. The temporal structure of the preamble signal is predetermined.

In the inventive device on the transmitting side, the first 3, second 4, third 6, fourth 7 counters and pause counter 32 use standard programmable counters, for example, series 564 IE10 and others. As the first 5 and second 8 read-only memory devices use known read-only memory devices with the required memory capacity.

The generated preamble signal and the information signal are transmitted through the transmitting path 11 to the communication channel.

When generating the preamble signal and the information signal, they are temporarily separated. The information signal enters the transmitting path after the signal the end of the procedure for generating the preamble signal.

The procedure for generating the preamble signal is as follows.

The clock generator 1, upon a command to control the start or repeat transmission of the preamble signal arriving at its input, generates clock pulses, the parameters of which are determined by the duration of the code sequence chip (PSP). From the output of the clock generator 1, the clock pulses are supplied to the first input of the demultiplexer 2, the second and fourth controlled inputs of which, respectively, from the output of the first counter 3 and from the output of the pause counter 32 receive control signals (switching).

At the third controlled input of the demultiplexer 2 and at the controlled input of the data generation unit 10, a switching signal — the end of the preamble — is received from the output of the fourth counter 7.

The initial state of the control (switching) signals is set so that initially the clock pulses only from the first output of the demultiplexer 2 are fed to the input of the second counter 4. The second counter 4 is programmed so that it generates a signal at the output corresponding to the addresses of the current elements of the short code sequence, and the signal at the highest level, equal, for example, to a logical unit, indicates the end of the reading of the next short code sequence.

The signal addresses of the current elements of the short code sequence, coming from the output of the second counter 4 to the input of the first read-only memory 5, in block 5, cyclically read the current elements of the short code sequence, which are received from the output of the first read-only memory 5 to the first input of the adder 9 and then from its output they go to the input of the transmitting path 11. By the signal of the end of reading the next short code sequence, which goes to the input ervogo counter 3, comprising: counting (accumulation) of read cycles and generating at the output of the first counter control signal 3 of, for example, a logic one if the number of cycles equal to the predetermined number N of short code sequences in the preamble signal.

At the same time, during the time interval for the formation of a given number of short code sequences from the output of the second read-only memory 8 to the second input of the adder 9 and from the output of the data generation unit 10 to the third input of the adder 9, signals equal to zero are read.

According to the generated control signal from the output of the first counter 3, the demultiplexer 2 is switched, and the clock pulses from its third output are fed to the input of the pause counter 32. In the pause counter 32, the clock pulses are counted (accumulated) and programmed so that it appears in its oldest a discharge of a signal equal, for example, to a logical unit, corresponded to the end of the formation of a pause of a given duration.

At the same time, during the interval of a pause from the output of the first read-only memory 5 to the first input of the adder 9, from the output of the second read-only memory 8 to the second input of the adder 9 and from the data generation unit 10, the signals are read to the third input of the adder 9 and to the input of the transmitting path 11 equal to zero.

The signal the end of the formation of a pause of a given duration, which comes from the output of the pause counter 32 to the fourth input of the demultiplexer 2, carry out its switching, and clock pulses come only from the second output of the demultiplexer 2 to the input of the third counter 6.

The third counter 6 is programmed in such a way that a signal corresponding to the addresses of the current elements of a long code sequence is generated at its outputs, and a signal at the high order, equal, for example, to a logical unit, indicates the end of reading of the next long code sequence.

According to the address signals from the output of the third counter 6 to the input of the second read-only memory 8, the current elements of the long code sequence are cyclically read, which are fed to the second input of the adder 9. The signal for reading the next long code sequence, which is input to the fourth counter 7, they count (accumulate) the number of read cycles and form at the output of this counter a control signal equal, for example, to a logical unit, if lo cycles equal to a predetermined number M of long code sequences in the preamble signal.

At the same time, during the time interval for the formation of a given number of long code sequences from the output of the first read-only memory 5 to the first input of the adder 9 and from the data generation unit 10 to the third input of the adder 9, signals equal to zero are read.

By the signal of the end of the formation of a predetermined number of long code sequences, which is output from the fourth counter 7 of the number of long code sequences to the third input of the demultiplexer 2 and to the controlled input of the data generation unit 10, switching is performed in such a way that the output from the first read-only memory 5 to the first the input of the adder 9 and from the output of the second permanent storage device 8 to the second input of the adder 9 read signals equal to zero, and from the output of the data formation unit 10 to the third input of the adder 9 is read information signal.

From the output of the adder 9, the generated digital video signal enters the transmitting path 11. In the transmitting path 11, the preamble signal and the information signal are converted by performing a standard sequence of operations (filtering, digital-to-analog conversion, modulation, transfer to the carrier frequency, amplification, etc.), and transmit the received signal (message) to the communication channel.

The preamble signal is used for time-frequency synchronization, which consists of two stages. In this case, at the first stage, an a priori time interval of the temporal position of the second part of the preamble and a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal are determined. At the second stage, the temporal position of the preamble is estimated and the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is performed.

Consider the implementation of the proposed method on the receiving side, using for this figure 4, which shows a structural diagram of the inventive device on the receiving side.

On the receiving side in the receiving path 12, the input signal that is received at its input is pre-filtered, amplified, transferred to the video frequency, its analog-to-digital conversion, decimation, etc. As a result, an input digital complex signal is generated at the video frequency.

The in-phase and quadrature components of the input digital signal from the first and second outputs of the receiving path 12 are respectively supplied to the inputs of the first 13 and second 14 matched filters and to the first and second inputs of the complex multiplier 18.

In the first matched filter 13, the common-mode component of the input signal is matched with one short code sequence. In the second matched filter 14, the quadrature component of the input signal is matched to one short code sequence.

The outputs of the first 13 and second 14 matched filters generate correlation responses, respectively, for the in-phase and quadrature components of the input digital complex signal, which are fed to the inputs of the first 33 and second 34 delay lines, respectively, for the in-phase and quadrature components of the signal.

In the first 33 and second 34 delay lines, the responses for the in-phase and quadrature components are sampled, for example, in one chip on an interval of duration N short code sequences, respectively, recorded (recorded). Each delay line, respectively, for in-phase and quadrature components has N outputs.

In the first 15 ₁ -15 _N and second 16 ₁ -16 _N multipliers, the squares of the corresponding responses for the in-phase and quadrature components of the first stage are calculated, which are fed to the corresponding first and second inputs of the first adder 17.

In the first adder 17, by summing the corresponding squares of the in-phase and quadrature components of the responses, the sum of N squares of the modules of the complex responses of the first stage, taken at intervals equal to the duration of the short code sequence, which are received at the first input of the first comparison unit with threshold 21, is calculated. comparison with the threshold 21 from the first output of the control unit 22 receives a control signal that determines the moment of completion or restart of the first stage. At the third input of the first comparison unit with a threshold 21 and the second input of the control unit 22 from the first output of the unit for determining the boundaries of the a priori interval 35, a signal is received of the beginning of the a priori interval of the time position of the second part of the preamble, according to which the initial (initial) threshold value of the first stage is set. This setting is necessary to start the next cycle of the first phase of synchronization. In the first comparison unit with the threshold 21, the summation results from the output of the first adder 17 are successively compared with the threshold of the first stage H1. The comparison results from the output of the first comparison unit with a threshold of 21 are fed to the second input of the unit for determining the boundaries of the a priori interval 35 and to the first input of the frequency shift calculation unit 20.

If the threshold of the first stage is exceeded:

the current temporary position of the preamble is considered the temporary position of the beginning of the preamble corresponding to the result of the summation;

in the unit for calculating the frequency shift 20 form the current estimate of the frequency shift;

in the block for determining the boundaries of the a priori interval 35, the beginning of the a priori interval of the time position of the second part of the preamble (by first exceeding the threshold) and the end of the a priori interval of the time position of the second part of the preamble (by the last exceeding of the threshold of the first stage) are determined;

the current estimate of the frequency shift is formed in the block for calculating the frequency shift 20 by the average phase difference of the complex responses of the first stage, arriving at the second and third inputs of block 20.

The averaged phase difference is formed, for example, as the sum of the products of complex responses to complex conjugate adjacent responses. Moreover, n-1 initial and n-1 last correlation responses are not used in the formation of the sum. The value of the argument of the obtained complex number is equal to the averaged phase difference. In this case, the ratio of the averaged phase difference to the duration of the short code sequence is equal to the estimate of the current frequency shift.

An estimate of the current frequency shift comes from the output of block 20 to the first input of the harmonic generation block 19 and to the first input of the third adder 31 and corresponds to the current “rough” estimate of the frequency detuning. At the second input of the harmonic generation block 19, at the first input of the block for determining the boundaries of the a priori interval 35 and at the fifth input of the block for calculating the additional frequency shift 30, a clock signal is received from the output of the clock generator 23, the period of which is equal in this case to the memory bandwidth chip.

The beginning of the a priori time interval of the second part of the preamble is determined in the block for determining the boundaries of the a priori interval 35, for example, equal to the sum of the temporal position of the preamble corresponding to the first excess of the threshold of the first stage, the duration of (N-2) -x short code sequences and the duration of the pause. Starting from the moment of the start of the a priori time interval of the second part of the preamble, a signal equal, for example, to a logical unit, from the first output of the boundary determination unit of the a priori interval 30 is supplied to the second input of the control unit 22 and the third input of the first comparison unit with a threshold 21.

The end of the apriori interval of the time position of the second part of the preamble is determined in the block for determining the boundaries of the a priori interval 35, for example, equal to the sum of the current temporal position of the preamble, the duration of (N + 3) -x short code sequences and the duration of the pause. The signal for the end of the a priori interval comes from the second output of the block determining the boundaries of the a priori interval 35 to the third input of the control unit 22.

After each excess of the threshold of the first stage, its value is set in the first block of comparison with the threshold 21 equal to the result of the summation in the first adder 17.

By the time the second stage begins, in the frequency shift calculation unit 20, a preliminary estimate of the frequency shift between the input signal carrier and the reference signal frequency is formed, which is equal to the last current frequency shift estimate.

In the harmonic generation unit 19, according to a preliminary estimate of the frequency shift and the signal from the clock generator 23, a complex multiplier of unit amplitude is formed, the phase of which is equal to the product of the preliminary estimate of the frequency shift by the temporary position of the current samples. The quadrature components of the complex factor from the first and second outputs of the harmonic generation unit 19 are respectively supplied to the third and fourth inputs of the complex multiplier 18, in which the phase of the input digital complex signal is corrected in the second stage. To do this, in the complex multiplier 18 carry out the well-known operation of multiplying the samples of the input digital complex signal by a complex factor.

At the beginning of the a priori time interval of the second part of the preamble in the first block comparing with threshold 21, the threshold of the first stage is set equal to the initial value H1. From this moment in time, the second stage begins, during which the temporal position of the preamble and the final estimate of the frequency shift between the carrier of the input signal and the frequency of the reference signal are estimated.

In the interval of operation of the second stage in the complex multiplier 18, the phase of the input digital complex signal is constantly adjusted taking into account a preliminary estimate of the frequency shift between the carrier of the input signal and the frequency of the reference signal obtained in the first stage.

The in-phase and quadrature components of the input digital complex signal, phase-corrected, from the first and second outputs of the complex multiplier 18 are supplied respectively to the inputs of the third 24 and fourth 25 matched filters.

In the third 24 and fourth 25 matched filters, matched filtering is performed with one long code sequence for the in-phase and quadrature components of the input corrected digital complex signal, respectively, and the in-phase and quadrature components of the responses of the second stage are respectively formed. The generated in-phase components of the responses of the second stage from the output of the third matched filter are supplied to the first and second inputs of the third multiplier 26 and to the first input of the calculation unit for the additional frequency shift 30. The generated quadrature components of the responses of the second stage from the output of the fourth 25 matched filter are fed to the first and second inputs of the fourth multiplier 27 and to the second input of the unit for calculating the additional frequency shift 30.

In the third 26 and fourth 27 multipliers, respectively, the squares of the in-phase and quadrature components of the responses of the second stage are formed, which are received respectively at the first and second inputs of the second adder 28, where by summing them, the squares of the modules of the complex responses of the second stage are calculated.

The calculated squares of the second-stage complex response modules from the output of the second adder 28 go to the first input of the second comparison unit with a threshold 29. A control signal equal to, for example, a logical unit is received at the second input of the second comparison unit with a threshold 29 from the second output of the control unit 22 the current time delay is inside the a priori time interval of the second part of the preamble. From the sixth output of the control unit 22 to the third input of the second unit of comparison with the threshold 29 receives the signal of the end of the second stage, equal, for example, to a logical unit.

In the second block of comparison with the threshold 29 for time delays on the a priori time interval of the temporal position of the second part of the preamble, the squares of the modules of the complex responses of the second stage are compared with the threshold of the second stage H2. The result of the comparison from the output of the second comparison unit with a threshold 29 is fed to the first input of the control unit 22 and to the third input of the calculation unit for the additional frequency shift 30.

If threshold H2 is not exceeded in the a priori time interval of the second part of the preamble, the preamble is assumed to be undetected, the first stage control signal is generated at the first output of control unit 22, which is fed to the second input of the first comparison unit with threshold 21, and the time-frequency synchronization procedure is repeated, starting from the first stage.

If the threshold H2 is exceeded (at least once) in the a priori interval of the time position of the second part of the preamble, the preamble is considered to be detected. Moreover, the signals for exceeding the threshold in the control unit 22 determine the final assessment of the temporary position of the preamble as the temporary position of the first excess of the threshold of the second stage H2. The resulting estimate from the fourth output of the control unit 22 is supplied to the first output of the device.

The final assessment of the temporal position of the preamble (the beginning of the preamble) is uniquely determined by the temporal position of the first exceeding the threshold of the second stage H2 and is equal to the difference between the temporal position of the first exceeding the threshold of the second stage H2 and the sum of the durations of the first part of the preamble and pause.

In the block for calculating the additional frequency shift 30 according to the control signal for exceeding the threshold of the second stage and for the control signal for the end of the a priori interval of the second part of the preamble, respectively, arriving at its fourth and sixth inputs from the third and fifth outputs of the control unit 22, and the signal for exceeding the threshold received at the third input from the output of the second comparison unit with the threshold 29, determine the temporary position corresponding to the maximum value of the square of the integrated response module of the second stage.

In the block for calculating the additional frequency shift 30, the in-phase and quadrature components of the complex responses of the second stage, corresponding to the maximum value of the square of the module, and the responses of the second stage, separated from this response by an integer number of durations of intervals of a long code sequence from 1 to (M-1), are used for determining an additional estimate of the frequency shift.

Evaluation is performed, for example, as follows. The averaged phase difference M of the adjacent complex responses of the second stage is formed as the sum of the products M-1 of complex conjugate responses to subsequent complex responses spaced apart by a time interval equal to a long code sequence. As a result, the argument of the obtained complex number is equal to the average phase difference of the adjacent complex responses of the second stage and determines the estimate of the additional phase shift. An additional estimate of the frequency shift is determined, for example, as the ratio of the averaged phase difference of adjacent complex responses of the second stage to the duration of a long code sequence. An additional estimate of the frequency shift from the first output of block 30 goes to the second input of the third adder 31.

In the third adder 31, the final estimate of the frequency shift between the input carrier and the frequency of the reference signal is determined as the sum of the preliminary and additional estimates of the frequency shift. The resulting final assessment from the output of the third adder 31 is fed to the second output of the device.

At the end of the procedure for additionally estimating the frequency shift, in the unit for calculating the additional frequency shift 30, a signal is generated for the end of the second stage, which from the second output of the block 30 is fed to the fourth input of the control unit 22. The signal is completed for the time-frequency synchronization of the communication system.

For a better understanding of the implementation of the claimed method of time-frequency synchronization of the communication system and device for its implementation, we consider the operation of the block for determining the boundaries of the a priori interval 35, the first 21 and second 29 blocks of comparison with the threshold, the unit for calculating the additional frequency shift 30, and the control unit 22.

The block determining the boundaries of the a priori interval 35 can be performed, for example, as shown in Fig. 5, and operates as follows.

In the first arm containing the first register 36, the first key 37 and the first counter 38, a signal of the beginning of the region of the a priori interval of the second stage is generated. In the second arm containing the second register 39, the second key 40 and the second counter 41, the end signal of the region of the a priori interval of the second stage is generated.

The circuit NOT 43 and the circuit OR 42 carry out the switching operation of the block 35.

The first and second inputs of the first 36 and second 39 registers and the first input of the AND circuit 42 receive a comparison signal with the threshold of the first stage from the second input of block 35. At the second input of AND circuit 42, from the output of circuit NOT 43, a signal is inverse to its input signal.

From the output of the first counter 38 (beginning) to the third input of the reset (zeroing) of the first register 36, to the input of the circuit NOT 43 and to the first output of the block 35, a signal equal to logical zero until the start of the a priori interval of the second stage and equal to a logical one otherwise .

At the third input of reset (zeroing) of the second register 39 and at the second output of block 35 from the output of the second counter 41 (end), a signal equal to logical zero until the end of the a priori interval of the second stage and equal to a logical unit in the opposite case is received.

When the threshold of the first stage is exceeded, the first 36 and second 39 registers record a signal equal to a logical unit, which from the outputs of the first 36 and second 39 registers is fed to the first controlled inputs of the first 37 and second 40 keys, respectively. The second inputs of the first 37 and second 40 keys from the first input of block 35 receive a signal from the clock generator, which through the first key 37 is fed to the input of the first counter 38, and through the second key 40 to the first input of the second counter 41. To the second input of the second counter 41 from the output of the circuit And 42 receives a signal of zeroing (control).

The circuit NOT 43 and the circuit AND 42 generate a zeroing signal of the second counter 41 and provide control of the operation mode of the second arm of this block.

Upon first exceeding the threshold of the first stage, the first key 37 is closed and the first counter 38 accumulates clock pulses. It is programmed in such a way that the signal of the beginning of the a priori interval of the time position of the second part of the preamble, equal to a logical unit, appears at its output at a point in time equal, for example, to the sum of the time position of the preamble corresponding to the first exceeding the threshold of the first stage, the duration of N-2 short code sequences and duration of a pause.

The signal of the beginning of the a priori time interval of the second part of the preamble, equal to a logical unit, from the output of the first counter 38 goes to the first output of block 35, to the input of the circuit NOT 43 and to the third input of the first register 36, by which the first register 36 is reset, and the first key 37 and the first counter 38 is blocked. At the same time, at the output of AND circuit 42, a signal equal to logical zero is generated, blocking the reset of the second counter 41.

When there is no signal at the beginning of the a priori time interval of the second part of the preamble, the output signal of the first counter 38 is logic zero, according to which, in circuit I 42, each time the threshold of the first stage is exceeded, a reset signal of the second counter 41 is generated, which is equal to a logical unit, as a result of which the second counter 41 zeroed out.

It should be noted that each subsequent excess of the threshold of the first stage corresponds to a greater response of the first stage. Therefore, the last excess of the threshold of the first stage for the proposed reception procedure determines the greatest response of the first stage. The temporary position of this response in the proposed procedure is used to form the end of the a priori interval of the temporary position of the second part of the preamble. Ultimately, the procedure for determining the time position of the end of the a priori interval of the time position of the second part of the preamble is to determine the time position of the greatest response of the first stage.

In the second counter 41, for each current signal exceeding the threshold of the first stage, clock pulses are accumulated. The proposed procedure for resetting the second counter 41 by a signal from the output of circuit I 42 provides the formation of a signal for the end of the a priori interval of the time position of the second part of the preamble according to the time position of the highest response of the first stage.

The second counter 41 is programmed in such a way that the signal for the end of the a priori time interval of the second part of the preamble, equal to a logical unit, appears at its output at a point in time equal, for example, to the sum of the current temporary position of the preamble, duration (N + 3) -x short code sequences and duration of a pause.

The signal for the end of the a priori time interval of the second preamble’s second position, equal to a logical unit, from the output of the second counter 41 goes to the second output of block 35 and to the third input of the second register 39. This signal is used to reset the second register 39 and complete the procedure for generating the a priori time interval of the second parts of the preamble.

The first 38 and second 41 counters can be implemented, for example, on the basis of standard programmable counters such as 564IE10 or the like.

Let us consider in more detail the operation of the first 21 and second 29 comparison blocks with a threshold. Blocks 21 and 29 are made identically and differ only in signals arriving at circuit elements. Therefore, the structural diagram for both blocks is presented in General form in Fig.6.

Consider the operation of the first comparison unit with threshold 21. The second control input of the first key 43 from the second input of the first comparison unit with threshold 21 (respectively, from the first output of the control unit) receives a control signal that determines the moment of completion or restart of the first synchronization stage. The second controlled input of the third key 46 from the third input of block 21 receives a signal of the beginning of the a priori time interval of the second position of the preamble.

Preliminarily, when the receiving device is turned on, a signal equal to a logical unit is set to the second controlled input of the first key 43, by which the first key 43 is opened (closed), and the threshold exceeding signal from the output of the comparator 42 is transmitted through the first key 43 to the output of the first comparison unit with the threshold 21 and to the second controlled input of the second key 44. Previously, the initial threshold value of the first stage H1 is recorded in the register 45. At the first controlled input of the third key 46, a signal is set equal to logical zero, by which this key is closed (open). The signal from the output of the third key 46 or the signal from the output of the second key 44 goes to the input of the register 45, is stored in it and from the output of the register 45 goes to the second input of the comparator 42.

The first inputs of the second key 44 and the comparator 42 from the first input of block 21 receive the squares of the integrated response modules of the first stage, which are compared in the comparator 42 with the threshold of the first stage.

When the threshold is exceeded, the output of the comparator 42 generates a signal equal to a logical unit, which, through the first key 43, enters the output of the first comparison unit with threshold 21 and the second controlled input of the second key 44. By this signal, the square of the module of the current complex response through the second key 44 enters to the input of the register 45, it is stored in it and from its output goes to the second input of the comparator 42 as the value of the current threshold of the first stage, and the comparison procedure with the threshold is repeated.

The comparison procedure with the threshold ends at the moment the first key 43 of the control signal arrives at the second controlled input, which determines the moment of completion or restart of the first stage (logical zero). In this case, the first key 43 is blocked (open).

According to the signal of the beginning of the a priori time interval of the second part of the preamble (logical unit), supplied to the second controlled input of the third key 46, a signal equal to the initial threshold value of the first stage H1 (stored inside the block) is supplied to the register input 45 from the first signal input of the third key 46 , and stored in the register 45.

The comparison procedure with the threshold of the second stage is performed similarly, however, the following are used as input signals.

The first inputs of the second key 44 and the comparator 42 from the first input of block 29 receive the computed squares of the integrated response modules of the second stage.

The second controlled input of the first key 43 from the second input of block 29 (respectively, from the second output of the control unit 22) receives a control signal equal to, for example, a logical unit if the current time delay is inside the a priori time interval of the second position of the preamble.

The second input of the second comparison unit with a threshold 29 and, respectively, the second controlled input of the third key 46 from the third input of the block 29 (respectively, from the second output of the control unit 22) receives the end signal of the second stage, which is, for example, a logical unit.

The calculation unit of the additional frequency shift 30 (Fig.7) works as follows. The first 47 and second 48 registers, the third 53 and fourth 54 keys are used to highlight the complex response of the second stage, corresponding to the maximum value of the square of the module of the complex response of the second stage.

The first 51, second 52, and fifth 55 keys, third 49 and fourth 50 registers, the first counter 56 (long code sequence counter), the second counter 57 (long code number counter), and the frequency shift calculation unit 58 implement the procedure for calculating the additional frequency shift.

The first inputs of the first register 47 and the second key 52 from the first input of the block 30 receive the in-phase components of the responses of the second stage.

The first inputs of the second register 48 and the first key 51 receive the quadrature components of the responses of the second stage.

The second inputs of the first 47 and second 48 registers and the first input of the first counter 56 from the third input of block 30 receives a signal for exceeding the threshold of the second stage.

The second controlled inputs of the first 51 and second 52 keys and the input of the second counter 57 from the output of the first counter 56 receives a pulse signal, the period of which is equal to the length of a long code sequence.

The second input of the first counter 56 receives a signal from the output of the fifth key 55, the first input of which from the fifth input of block 30 receives a clock signal, the period of which is equal in this case to the DSP chip. The second controllable input of the fifth key 55 from the fourth input of block 30 receives a signal of the presence of a threshold exceeding the second stage.

The signals of exceeding the threshold of the second stage in the first 47 and second 48 registers store the corresponding values of the in-phase and quadrature components of the responses of the second stage, which from their outputs go to the first inputs of the third 53 and fourth 54 keys, respectively. In this case, the first counter 56 is reset, and the first 51 and second 52 keys are closed (open). To the second inputs of the third 53 and fourth 54 keys from the sixth input of block 30, a signal is received for the end of the a priori interval of the second part of the preamble, which is equal to logical zero during the a priori interval of the second part of the preamble. At the end of the a priori interval, the second inputs of the third 53 and fourth 54 keys receive a signal equal to a logical unit, this signal corresponds to the in-phase and quadrature components of the responses of the second stage, from the outputs of the third 53 and fourth 54 keys are fed to the inputs of the third 49 and fourth 50 parallel registers and are stored in them. According to this procedure, the in-phase and quadrature components of the responses of the second stage stored in the third 49 and fourth registers correspond to the maximum response of the second stage.

The second input of the fifth key 55 receives a signal equal to a logical unit if there was at least one excess of the threshold in the a priori interval of the time position of the second part of the preamble. On this signal from the output of the fifth key 55 to the second (counting) input of the first counter 56 receives the signal of the clock generator, which accumulates in it. The first counter 56 is programmed so that a pulse signal is generated at its output with a period equal to the length of a long code sequence. According to this signal, through the first 51 and second 52 keys, they sequentially write to the third 49 and fourth 50 registers and form a sequence of corresponding in-phase and quadrature components of the responses of the second stage, separated from the maximum response of the second stage to time intervals that are multiples of the length of the long code sequence. The generated sequence of responses of the second stage is supplied to the corresponding first in-phase and second quadrature inputs of the frequency shift calculation unit 58.

The responses of the second stage, the number of which is equal to M, which is determined by the output signal of the second counter 57, are used to calculate the frequency shift. The second counter 57 is programmed so that at its output, an impulse signal of duration M-1 of long code sequences is generated, which is fed to the third input of the frequency shift calculation unit 58 and to the second output of block 30. According to the output of the second counter 57 in the calculation unit the frequency shift 58 of the M in-phase and quadrature components of the responses of the second stage, formed in the third 49 and fourth 50 registers, implement the procedure for calculating the estimates of the frequency detuning w in accordance with the expression

- комплексные отклики второго этапа, Uc_k,Us_k,

- соответственно синфазные и квадратурные составляющие откликов второго этапа, (*) - операция комплексного сопряжения.where L is the number of chips in a long memory bandwidth, δ is the duration of the memory bandwidth chip, U _k = Uc _k + jUs _k ,

- complex responses of the second stage, Uc _k , Us _k ,

- respectively, in-phase and quadrature components of the responses of the second stage, (*) - operation of complex pairing.

The obtained additional estimate of the frequency detuning w from the output of the frequency shift calculation unit 58 is supplied to the first output of the additional frequency shift calculation unit 30.

The third 49 and fourth 50 registers with sequential recording and parallel reading are implemented, for example, on the basis of standard microcircuits of the 561PR1 series or 1564IR8 series or the like.

The first 56 and second 57 counters are easily implemented, for example, on the basis of standard microcircuits such as 564IE10 or the like.

The control unit 22 for the inventive device, made in Fig.8, operates as follows.

From the second input of the control unit 22 to the first input of the first circuit And 59 receives the signal of the beginning of the a priori time interval of the second position of the preamble.

From the third input of the control unit 22 to the first input of the second circuit And 60 and to the input of the second circuit NOT 63 receives the end signal of the a priori time interval of the second position of the preamble. The inverse signal of the end of the a priori time interval of the second part of the preamble from the output of the second circuit NOT 63 is supplied to the second input of the first circuit And 59. The control signal from the output of the first circuit And 59 is equal, for example, to a logical unit if the current time delay is inside the a priori time interval the position of the second part of the preamble, is fed to the first input of the OR circuit 64 and to the sixth output of the control unit 22.

From the first input of the control unit to the first signal input and to the second input of the register register 67, a signal of the comparison result with a predetermined threshold of the second stage H2 is received, according to which, if there is at least one excess, a signal equal to a logical unit is recorded in register 67. The signal from the output of the register 67 is fed to the second input of the OR circuit 64, to the input of the first pulse shaper 65, to the second input of the second circuit And 60 and to the third output of the control unit 22.

At the output of the second circuit And 60, at the end of the a priori interval of the second stage, a signal equal to a logical unit is formed if there was at least one excess of the threshold of the second stage. The generated signal from the output of the second circuit And 60 is fed to the input of the second pulse shaper 66, at the output of which a pulse signal is generated at the end of the a priori interval of the second stage, if there was at least one excess of the threshold of the second stage. The output signal of the second pulse shaper is the fifth output of the control unit 22.

Based on the output signal from register 67 at the output of the first pulse shaper 65, an estimate of the temporary position of the first threshold exceeding the second stage H2 is formed in the form of a pulse, the temporary position of which corresponds to the first exceeding the threshold of the second stage or the beam signal with the least time delay. The output of the first pulse shaper 65 is the fourth output of the control unit 22.

At the output of the OR 64 circuit, a signal is generated that is equal to a logical unit if there was at least one excess of the threshold of the second stage, or if the current time delay is inside the a priori interval of the second stage, or if both of these conditions are observed simultaneously. Otherwise, the signal at the output of the OR circuit 64 is logical zero. The signal from the output of the OR circuit 64 is fed to the input of the first circuit NOT 62 and to the first input of the third circuit And 61, the second input of which from the fourth input of the control unit 22 receives the end signal of the second stage.

At the output of the first circuit NOT 62, a control signal is generated that determines the moment of completion or restart of the first stage. The output of the first circuit NOT 62 is the first output of the control unit 22.

At the output of the third circuit And 61 form the signal for the end of the second stage. The output of the third circuit And 61 is the second output of the control unit 22, according to this signal in the second block comparing with threshold 29, the initial value of the threshold of the second stage is set.

The first 65 and second 66 pulse shapers can be implemented in the form of a well-known single-pulse generator based on, for example, a standard 564TM2 microcircuit (trigger) or similar.

The claimed group of inventions is a method of time-frequency synchronization of a communication system and a device for its implementation, created in a single inventive concept in comparison with the known technical solutions in this field of technology, has the following advantages: the temporal position of the preamble signal is evaluated in two stages, and in the first at the stage they form the decisive function with a wide useful response, which increases the probability of the correct detection of the preamble signal, at the second stage they form the decisive a function with a narrow useful response that allows you to get an accurate estimate of the temporal position of the preamble signal; the frequency shift estimate is also formed in two stages, and the quality of this estimate is high, because it is based on a qualitative estimate of the temporal position of the signal. Another distinguishing feature of the invention is the ability to synchronize at relatively large initial values of the frequency shift, which is not available to many known methods of time-frequency synchronization.

The present invention significantly increase the noise immunity of the time-frequency synchronization of the communication system and expands the scope of its applicability.

Claims (8)

1. The method of time-frequency synchronization of a communication system, which consists in the fact that a digital video signal consisting of two parts is formed on the transmitting side, the generated digital video signal is filtered, its digital-to-analog conversion is performed, the signal is transferred to the carrier frequency, amplified and transmitted through the channel connection, on the receiving side, the input signal is filtered, amplified, transferred to the video frequency, its analog-to-digital conversion and decimation are carried out, forming the input digital complex signal on the video frequency, the time-frequency synchronization is performed in two stages: at the first stage, a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined, for which the generated digital complex signal is filtered, forming the complex responses of the first stage, the squares of the modules of complex responses of the first stage, carry out a comparison with a given threshold of the first stage, determine a preliminary estimate of the frequency shift between the carrier hour of the input signal and the frequency of the reference signal, in the second stage, the temporal position of the preamble and the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal are estimated, for which the phase of the input digital complex signal is adjusted in the interval of operation of the second stage, taking into account a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal, carry out a coordinated filtering of the adjusted input digital complex forming the complex responses of the second stage, calculate the squares of the modules of the complex responses of the second stage, compare with the given threshold of the second stage, if the threshold is not exceeded, the preamble is considered undetected; if the threshold is exceeded, the preamble is detected, then the final estimate of the temporal position of the preamble is determined by the time the position of the first excess of the threshold of the second stage, determine the temporary position corresponding to the maximum value of the square of the module xn response of the second stage, determine an additional estimate of the frequency shift by the phase difference of the complex responses of the second stage, determine the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal as the sum of the preliminary and additional estimates of the frequency shift, characterized in that on the transmitting side is a digital video signal , consisting of two parts, is formed so that the parts of the digital video signal are separated by a pause of a given duration, while the first hour l is N short code sequences, and the second part is M long code sequences, on the receiving side, when performing the first stage of the time-frequency synchronization, the prior interval of the temporal position of the preamble for the second stage is determined to determine a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal in the first stage, filter the input generated digital complex signal, consistent with one short By the next sequence, the sums of N squares of the complex response modules of the first stage are taken, taken at an interval equal to the duration of the short code sequence, the obtained sums of N squares of the complex response modules of the first stage are compared with the given threshold of the first stage; when the threshold is exceeded, the temporal position of the beginning of the preamble corresponding to the sum obtained , consider the current temporary position of the preamble, form the current estimate of the frequency shift by the averaged phase difference of adjacent complex responses in the first stage from the n-th to the (N-n + 1) -th, corresponding to the summation terms of the N squares of the modules of the complex responses of the first stage, where n is an integer,

the threshold of the first stage is set equal to the summation result, the beginning of the a priori time interval of the second position of the second preamble is determined by the temporal position of the preamble corresponding to the first excess of the threshold of the first stage, the end of the a priori time interval of the second position of the second preamble is determined by the current temporary position of the preamble, a preliminary estimate of the frequency shift between the carrier by the frequency of the input signal and the frequency of the reference signal is determined by the time the second stage begins as the current the estimate of the frequency shift, by the time the beginning of the a priori interval of the time position of the second part of the preamble begins, the threshold of the first stage is assumed to be equal to the initial value, and the current temporary position of the preamble is considered undefined; at the second stage, the adjusted input generated digital complex signal is filtered, consistent with one long code sequence, the squares of the second stage complex response modules are compared with a predetermined threshold of the second stage at the a priori time interval of the second position of the preamble, an additional estimate of the frequency shift is determined by the averaged phase difference M complex responses of the second stage: a complex response of the second stage corresponding to the maximum value the square of the module, and the responses of the second stage, separated from this response by an integer of the duration of the interval of the long code sequence from 1 to (M-1). 2. The method according to claim 1, characterized in that the current frequency shift estimate is formed as the ratio of the average phase difference of the complex responses of the first stage to the duration of the short code sequence. 3. The method according to claim 1, characterized in that the beginning of the a priori time interval of the second part of the preamble is determined, for example, to be equal to the sum of the temporary position of the preamble corresponding to the first excess of the threshold of the first stage, the duration of (N-2) -x short code sequences and the duration pauses. 4. The method according to claim 1, characterized in that the end of the a priori time interval of the second part of the preamble is determined, for example, to be equal to the sum of the current temporary position of the preamble, the duration of (N + 3) -x short code sequences and the duration of the pause. 5. The method according to claim 1, characterized in that the phase of the input digital complex signal in the interval of operation of the second stage is adjusted by multiplying the samples of the input digital complex signal by a complex factor of unit amplitude, the phase of which is equal to the product of the preliminary estimate of the frequency shift by the temporal positions of the samples. 6. The method according to claim 1, characterized in that the additional estimate of the frequency shift is determined, for example, as the ratio of the averaged phase difference of the complex responses of the second stage to the duration of a long code sequence. 7. The method according to claim 1, characterized in that the final assessment of the temporary position of the preamble, namely, the beginning of the preamble, is determined equal to the difference in the temporary position of the first exceeding the threshold of the second stage and the sum of the durations of the first part of the preamble and pause. 8. A frequency-time synchronization device for a communication system comprising a clock, a demultiplexer, a first counter, a second counter, a first read-only memory, a third counter, a fourth counter, a second read-only memory, an adder, a data generation unit transmitting a path, the input of the clock is the input of the device, the output of the clock is connected to the first input of the demultiplexer, which is the input of the clock signal, the second input is the ultiplexer, which is a controlled input, is connected to the output of the first counter, the first output of the demultiplexer is connected to the input of the second counter, the output of which is connected to the inputs of the first counter and the first read-only memory, the output of the first read-only memory is connected to the first input of the adder, the second output of the demultiplexer is connected with the input of the third counter, the output of which is connected to the inputs of the second read-only memory and the fourth counter, the output of which is connected connected with the third input of the demultiplexer, which is a controlled input, and the input of the data generation unit, the output of which is connected to the third input of the adder, the second input of which is connected to the output of the second permanent storage device, the output of the adder is connected to the input of the transmitting path, the output of which is the output of the device , on the receiving side, the receiving path, forming at the outputs an input digital complex signal at the video frequency, the first and second matched filters that filter according the common-mode and quadrature components of the generated input digital complex signal and forming the complex responses of the first stage, the first and second multipliers, the first adder, the complex multiplier, the harmonic generation unit, the frequency shift calculation unit, the first threshold comparison unit, the control unit, the clock generator, generating the output signal is a clock pulse, the third and fourth matched filters that filter the adjusted input digital complex signal and form comprehensive responses of the second stage, the third and fourth multipliers, the second adder, the second threshold comparison unit, the additional frequency shift calculator and the third adder, the input of the receiving path being the input of the device, the first output of the receiving path connected to the input of the first matched filter and the first the input of the complex multiplier, the second output of the receiving path is connected to the input of the second matched filter and the second input of the complex multiplier, the outputs of the first and second multipliers connected respectively to the first and second inputs of the first adder, the output of which is connected to the first input of the first comparison unit with a threshold, the second input of which is connected to the first output of the control unit, the output of the first comparison unit with a threshold connected to the first input of the frequency shift calculation unit, the output of which is connected with the first input of the harmonic generation unit and the first input of the third adder, the second input of the harmonic generation unit is connected to the output of the clock generator, the first and second outputs of the ha formation unit rmonics are connected respectively to the third and fourth inputs of the complex multiplier, the first and second outputs of which are connected respectively to the inputs of the third and fourth matched filters, the output of the third matched filter is connected to the first and second inputs of the third multiplier and the first input of the additional frequency shift calculation unit, the output of the fourth matched the filter is connected to the first and second inputs of the fourth multiplier and the second input of the unit for calculating the additional frequency shift The odes of the third and fourth multipliers are connected respectively to the first and second inputs of the second adder, the output of which is connected to the first input of the second comparison unit with a threshold, the second input of which is connected to the second output of the control unit, which forms the output signal for the end of the second stage, the output of the second comparison unit with the threshold is connected to the third input of the additional frequency shift calculation unit and the first input of the control unit, the third output of which is connected to the fourth input of the additional hour calculation unit total shift, the fourth output of the control unit is the first output of the device and the output of the signal for the final assessment of the temporal position of the preamble, the first output of the unit for calculating the additional frequency shift, forming at the first output an additional estimate of the frequency shift, is connected to the second input of the third adder, forming the final evaluation signal at the output frequency shift, the output of the third adder is the second output of the device, characterized in that on the transmitting side the first counter is made that In this way, which allows counting the number of short code sequences in the preamble signal, generating an output clock control signal for a given number N of read cycles, the second counter is designed in such a way that it allows counting the number of clock pulses in the short code sequence signal of the preamble the output signal corresponding to the addresses of the current elements of the short code sequence, the third counter is designed in such a way that allows l counting the number of clock pulses in the signal of the long code sequence of the preamble, generating at the output a signal corresponding to the addresses of the current elements of the long code sequence, the fourth counter is designed in such a way that allows counting the number of long code sequences in the preamble signal, generating the control signal of the clock pulses for a given number M of read cycles and a signal for the end of the preamble, the first read-only memory is configured such that Allows you to store samples of a short code sequence, the second read-only memory device is designed in such a way that allows you to store samples of a long code sequence, a pause counter is introduced, which counts the number of clock pulses in the pause interval of the preamble, generating a pause end signal at the output, the pause counter input is connected to the third the output of the demultiplexer, and the output with the fourth input of the demultiplexer, which is a controlled input; on the receiving side, the first and second delay lines, (N-1) first and (N-1) second multipliers, a block for determining the boundaries of the a priori interval, which generates a signal at the first output of the beginning of the a priori interval of the time position of the second part of the preamble, and at the second output, are introduced the end signal of the a priori time interval of the second part of the preamble, while the input of the first delay line is connected to the output of the first matched filter, the input of the second delay line is connected to the output of the second matched filter, the first the second matched filters are matched with a short code sequence, N outputs of the first delay line are connected to their respective N second inputs of the frequency shift calculator and to the first and second inputs of the corresponding N first multipliers, N outputs of the second delay line are connected to their corresponding N third inputs of the block calculation of the frequency shift and with the first and second inputs of the corresponding N second multipliers, the outputs (N-1) of the first multipliers are connected to (N-1) additional first inputs ne of the adder, the outputs (N-1) of the second multipliers are connected to (N-1) additional second inputs of the first adder, the output of the clock generator is connected to the fifth input of the additional frequency shift calculation unit and the first input of the boundary interval determination unit, the second input of which is connected to the output of the first comparison unit with a threshold, the first output of the unit for determining the boundaries of the a priori interval is connected to the second input of the control unit and the third input of the first comparison unit with a threshold, the second output of the determination unit the boundaries of the a priori interval is connected to the third input of the control unit, which generates a control signal at the first output that determines the moment of completion or restart of the first stage, at the third output - the signal for exceeding the threshold of the second stage, at the fifth output - the signal for the end of the a priori interval of the second part of the preamble, fifth the control unit output is connected to the sixth input of the additional frequency shift calculation unit, at the sixth output, an identification signal for the a priori interval of the second part of the preamble, the sixth output the control unit is connected to a third input of the second comparator to a threshold, the fourth control unit input is connected to the second output of the additional frequency shift calculating unit.

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