RU2231917C2 - Pulse generator - Google Patents

Abstract

FIELD: pulse engineering.

SUBSTANCE: proposed pulse generator that can be used in computer engineering devices and control systems has RS flip-flop, 2NOR gate, 2NAND gate, two inverters, four resistors, and two capacitors.

EFFECT: enhanced operating reliability.

1 cl, 1 dwg

Description

The invention relates to a pulse technique and can be used in computing devices and control systems.

A known pulse generator (see AS USSR No. 482878 from 04.24.72, MKI N 03 K 5/01, H 03 K 3/26, “Multivibrator” by B. A. Krylov and V. V. Myatezhnikov, publ. . 30.08.75, bull. No. 34), containing two triggers, two capacitors and two diodes. The first and second outputs of the first trigger are connected respectively to the first and second inputs of the second trigger. The first output of the second trigger is connected to the cathode of the first diode, the anode of which is connected to the second input of the first trigger and the first output of the second capacitor, the second output of which is connected to a common bus. The second output of the second trigger is connected to the cathode of the second diode, the anode of which is connected to the first input of the first trigger and the first output of the first capacitor, the second output of which is connected to a common bus.

The disadvantage of the pulse generator is the low reliability of operation due to the possibility of "freezing" of the circuit when power is applied.

The closest to the claimed invention in terms of essential features is a pulse generator (see AS USSR No. 1019592 dated 01/06/82, MKI N 03 K 3/281, “Multivibrator” by V.P. Belousov, publ. 23.05.83 , Bull. No. 19), containing an RS-trigger, a capacitor connected between the inputs of the trigger, the first and second diodes, the anodes of which are connected respectively to the S- and R-inputs of the trigger, and a logical inverter. The cathode of the first diode is connected to the inverse output of the trigger.

The input of the logical inverter is connected to the inverse output of the trigger, and the output is connected to the cathode of the second diode.

The disadvantage of the pulse generator is the low reliability due to a sharp increase in the repetition rate of the output pulses in case of failure (break) of the capacitor.

The problem solved by the invention is the creation of a pulse generator with high reliability.

The technical result, which consists in increasing the reliability of operation, is achieved by the fact that a second capacitor, a 2AND-NOT element, a 2OR-NOT element, a second inverter, and a second inverter are introduced into a pulse generator containing an RS-trigger whose inverse output is connected to the inverter input four resistors, the inverse output of the RS flip-flop connected to the first terminals of the capacitors, the second terminal of the first of which connected to the first terminals of the first and second resistors, the second terminal of the first resistor connected to the first inputs of the element 2 AND NOT and the element 2 OR NOT, the second output of the second resistor is connected directly to the output of the first inverter and through the third resistor to the second output of the second capacitor and the first output of the fourth resistor, the second output of which is connected to the second inputs of the element 2 OR NOT and the element 2 AND NOT , the output of which through the second inverter is connected to the R-input of the RS-flip-flop, the S-input of which is connected to the output of element 2 OR NOT.

The specified set of features allows to increase the reliability of the pulse generator due to the fact that in case of failure (break) of one of the capacitors, the output pulse repetition rate is determined by the other capacitor.

The drawing shows a schematic diagram of a pulse generator.

The pulse generator contains RS-trigger 1, first 2 and second 3 inverters, element 2I-NOT 4, element 2OR-NOT 5, first 6 and second 7 capacitors, first 8, second 9, third 10 and fourth 11 resistors. The inverse output of the RS-flip-flop 1 is connected to the input of the inverter 2 and the first terminals of the capacitors 6 and 7. The second terminal of the capacitor 8 is connected to the first terminals of the resistors 8 and 9. The second terminal of the resistor 8 is connected to the first inputs of the 2AND-NOT 4 element and the 2AND-NOT 5. The second terminal of the resistor 9 is connected directly to the output of the inverter 2 and through the resistor 10 to the second terminal of the capacitor 7 and the first terminal of the resistor 11, the second terminal of which is connected to the second inputs of the element 2 OR NOT 5 and the element 2 AND NOT 4, the output of which is through the inverter 3 connected to the R-input RS-tr igger 1, the S-input of which is connected to the output of element 2 OR NOT 5.

The pulse generator operates as follows.

After applying the supply voltage RS-trigger 1 is installed in one of the stable positions. Consider the case when at the inverse output of the RS-flip-flop 1 is set the logical level "1". In this case, the logic level “0” is set at the output of the inverter 2. Since the capacitors 6 and 7 are initially discharged, then the inputs of the elements 2I-NOT 4 and 2OR-NOT 5 through the resistors 8 and 11 receives the logical level "1". At the outputs of elements 2I-NOT 4 and 2OR-NOT 5, the logic level “0” is set, and at the R- and S-inputs of the RS-trigger 1, the levels of logical “1” and logical “0” are established, confirming the initial state of the RS-trigger 1 The capacitor 6 begins to charge on the circuit "inverse output of the RS-trigger 1, resistor 9, the output of the inverter 2". At the same time, the capacitor 7 begins to charge on the circuit "inverse output of the RS-trigger 1, resistor 10, the output of the inverter 2". As the capacitors 6 and 7 charge, the voltage at the inputs of 2I-NOT 4 and 2IL-5 elements starts to decrease. Due to the non-identity of the nominal values of the capacitors 6, 7 and resistors 9 and 10, the charge of the capacitors 6 and 7 will occur at different speeds. For definiteness, we will assume that the constant of the charge circuit of the capacitor 6 is less than the constant charge circuit of the capacitor 7. Therefore, the voltage at the first inputs of elements 2I-NOT 4 and 2OR-NOT 5 will reach the switching threshold earlier than at the second inputs. At this moment, the logic level “1” will be set at the output of the 2AND-NOT 4 element, and the logic level “0” will remain at the output of the 2AND-NOT 5 element, while both inputs of the RS-trigger 1 will have logic zero levels and the trigger will be in information storage mode. When the voltage at the second inputs of the elements 2I-NOT 4 and 2OR-NOT 5 reaches the switching threshold level, the output level of the last logic level will be set to "1", which, entering the S-input of the RS-trigger 1, will set it to a single state. At the inverse output of the RS-flip-flop 1, the logic level “0” will appear and the recharging of capacitors 6 and 7 will begin. Since at the initial moment of time at both inputs of elements 2I-NOT 4 and 2OR-NOT 5 there will be a logic level “0”, and on R and S-inputs of RS-flip-flop 1 will receive logic "0" and logical "1" levels respectively, then the state of RS-flip-flop 1 will not change. As the capacitors 6 and 7 are recharged, the voltage at the inputs of 2I-NOT 4 and 2OR-NOT 5 elements will increase. The voltage at the first inputs of 2I-NOT 4 and 2OR-NOT 5 elements will reach the switching threshold level earlier, however, this will not lead to the overturning of the RS-trigger 1, since there will be logical “0” levels on both inputs. When the voltage at the second inputs of the elements 2I-NOT 4 and 2OR-NOT 5 reaches the switching threshold level, the output level of the 2I-NOT 4 element will be set to logic "0", and at the R-input of the RS-trigger 1, the logic level is "1". RS-trigger 1 will be set to the state corresponding to the logic level “1” at its inverse output. Next, the process of generating output pulses is repeated.

In the event of a failure (break) of one of the capacitors, an increase in the frequency of generation of output pulses will not occur, since the operation description shows that the switching frequency of the RS trigger 1 is determined by the capacitor with the largest capacity.

A mock generator was made. Tests confirmed the operability of the claimed device and its practical value.

Claims (1)

A pulse generator containing an RS flip-flop, the inverse output of which is connected to the input of the inverter, and a capacitor, characterized in that a second capacitor is inserted, a 2AND-NOT element, a 2OR-NOT element, a second inverter and four resistors, the RS-trigger inverse output being connected with the first terminals of the capacitors, the second terminal of the first of which is connected to the first terminals of the first and second resistors, the second terminal of the first resistor is connected to the first inputs of the 2AND-NOT element and the 2OR-NOT element, the second terminal of the second resistor is connected directly with the output of the first inverter and through the third resistor with the second output of the second capacitor and the first output of the fourth resistor, the second output of which is connected to the second inputs of the element 2OR-NOT and element 2I-NOT, the output of which through the second inverter is connected to the R-input of the RS flip-flop, The S-input of which is connected to the output of element 2 OR NOT.