RU2231916C2 - Pulse generator - Google Patents

Abstract

FIELD: pulse engineering.

SUBSTANCE: proposed pulse generator that can be used for computer engineering devices and control systems has majority gate, 2NOR gate, two resistors, two capacitors, and two diodes.

EFFECT: enlarged functional capabilities.

1 cl, 1 dwg

Description

The invention relates to a pulse technique and can be used in computing devices and control systems.

A known pulse generator (see the book of Yakovlev V.N., Voskresensky V.V., Miroshnichenko S.I. et al. Handbook of microelectronic pulsed technology. K .: Technics, 1983, Fig. 9.3 g), containing two elements 2 OR NOT, two resistors, two capacitors, two diodes and a voltage source. The output of the first 2OR-NOT element is connected directly to the first input of the second 2OR-NOT element and the first output of the first capacitor and through the first resistor to the first output of the second capacitor, the anode of the first diode and its first input. The output of the second ORI-NOT element is connected directly to the second input of the first ORI-2 element and the second output of the second capacitor and through the second resistor to the second output of the first capacitor, the anode of the second diode and its first input. The cathodes of the diodes are combined and connected to the positive pole of the voltage source, the negative terminal of which is connected to a common bus. The outputs of the first and second elements 2OR are NOT outputs of the pulse generator.

The disadvantages of the pulse generator are the presence of voltage spikes at the inputs of 2OR-NOT elements and overloading of the output current at the time of switching due to overcharging of the capacitors.

The closest to the claimed invention by the set of essential features is a pulse generator (see. A. S. USSR No. 1279056 from 06.01.82, MKI: N 03 K 5/01, 5/153, “Protection device from bounce” authors V. L. Chervyak, M.A. Guranchik and A.V. Ryvkin, publ. 12/23/86, Bull. No. 47), containing the majority element, inverter and delay element. The first input of the majority element is connected to the input bus. The second input of the majority element is connected to its output, the output bus and the inverter input. The inverter output through the delay element is connected to the third input of the majority element.

The disadvantage of the pulse generator is the inability to generate a sequence of pulses due to circuit design.

The problem solved by the invention is the creation of a pulse generator having advanced functionality, namely the ability to generate a sequence of pulses.

The technical result, which consists in expanding the functionality, is achieved by the fact that, in the pulse generator containing the majority element, the input and output bus connected to the output of the majority element and its second input, the 2OR-NOT element, two resistors, two diodes and two capacitors are introduced the first conclusions of which are combined and connected to a common bus, the second output of the first capacitor is connected directly to the first input of the majority element and the anode of the first diode and through the first resistor to the second output in orogo capacitor, the third input element of majority and the cathode of the second diode, the anode of which is connected to the cathode of the first diode through the second resistor and - a yield of 2 or-NO element, whose first input is connected to the input bus and the second input - to the output of the majority element.

The specified set of features allows you to expand the functionality of the pulse generator of the generator due to the ability to generate a sequence of pulses by changing the duration of the control input signal.

The drawing shows a schematic diagram of a pulse generator.

The pulse generator contains a majority element 1, input 2 and output 3 buses, element 2 OR NOT 4, the first 5 and second 6 capacitors, the first 7 and second 8 resistors, the first 9 and second 10 diodes. The output of the majority element 1 is connected to its second input and the output bus 3. The first outputs of the capacitors 5 and 6 are combined and connected to a common bus. The second output of the capacitor 5 is connected directly to the first input of the majority element 1 and the anode of the diode 9 and through the resistor 7 to the second output of the capacitor 6, the third input of the majority element 1 and the cathode of the diode 10. The anode of the diode 10 is connected to the cathode of the diode 9 and the first output of the resistor 8. The second output of the resistor 8 is connected to the output of the element 2 OR NOT 4, the first input of which is connected to the input bus 2, the second input to the output of the majority element 1.

The pulse generator operates as follows.

Consider the case when at the time of supply of the supply voltage on the input bus 2 there is a logic level of "1". At the output of element 2 OR NOT 4, the logic level is set to “0”, which is fed to the first and third inputs of the majority element 1. At the output of the majority element 1, the logic level is set to “0”. The generator is in a stable state and does not produce output pulses. When a triggering signal is applied to the input bus 2 in the form of a logic level “0”, the output level of the element 2 OR NOT 4 is set to the logical level “1”. The charge of the capacitor 6 begins with the output of the element 2 OR NOT via the resistor 8 and the diode 10 and the capacitor 5 with the output of the element 2 OR NOT via the resistor 8, the diode 10 and resistor 7. Since the charge time constant of the capacitor 5 is greater than the charge time constant of the capacitor 6, then the voltage at the latter will reach the switching threshold level faster and will continue to increase, tending in the limit to the logical level “1”. When the voltage at the capacitor 5 reaches the switching threshold of the majority element 1, the logical level “1” will appear at its output. At the same time, the logic level “0” is set at the output of the 2OR-NOT 4 element and the discharge of the capacitor 6 begins through the resistors 7, 8 and the diode 6 and the capacitor 5 through the diode 6 and the resistor 7. Since the discharge time constant of the capacitor 6 is greater than the charge constant of the capacitor 5, then the voltage at the last one will reach the switching threshold level faster and will continue to decrease, tending in the limit to the level of logical "0". When the voltage on the capacitor 6 reaches the switching threshold of the majority element 1, the logical level “0” will appear at its output. Further, the process of generating output pulses will be repeated. The number of output pulses will be determined by the duration of the control pulse supplied to the input bus 2, since when a logic “1” level appears on the input bus 2 at the output of the 2 OR NOT 4 element, the logic level “0” is set and the generator stops generating output pulses.

Thus, the inventive generator has a wider functionality compared to the prototype, namely, it provides the formation of not only single pulses, but also a series of pulses depending on the duration of the control input pulse.

A mock generator was made. Tests have shown the operability of the claimed device and its practical value.

Claims (1)

A pulse generator containing a majority element, an input and output bus connected to the output of the majority element and its second input, characterized in that the 2OR-NOT element is introduced, two resistors, two diodes and two capacitors, the first terminals of which are connected and connected to a common bus , the second terminal of the first capacitor is connected directly to the first input of the majority element and the anode of the first diode and through the first resistor to the second output of the second capacitor, the third input of the majority element and the cathode of the second diode Which anode is connected to the cathode of the first diode and the second resistor via a first input with the output 2or-NO element is connected to the input bus and the second input - to the output of the majority element.