RU2224356C2 - Memory location - Google Patents

Abstract

FIELD: pulse engineering; computers and control systems. SUBSTANCE: device has switching unit, N series RC circuits, asynchronous D flip-flop, two bidirectional switches, three NOR gates, multiplexer, pulse counter, and two synchronous D flip-flops. EFFECT: enhanced reliability in memory saving mode. 1 cl, 1 dwg

Description

 The invention relates to the field of pulse technology and can be used in devices of computer technology and control systems.

 A well-known memory cell (see A.S. USSR 1706362 dated 02.04.90, MKI N 03 K 3/037, "Trigger device", Eremin AN, Shishkin GI, publ. 08/28/97, Bull. 24), containing a D-trigger, the first, second and third elements OR-NOT, element AND-NOT, bidirectional switch, resistor and capacitor. One of the resistor leads through a capacitor is connected to a common bus. The first and second inputs of the first OR-NOT element are connected respectively to the first installation input of the device and the output of the second OR-NOT element. The first and second inputs of the second element OR are NOT connected respectively to the second installation input of the device and the direct output of the D-trigger. The clock input of the D-trigger is connected to the output of the third OR-NOT element, the first and second inputs of which are connected to the first inputs of the first and second OR-NOT elements, respectively. The bi-directional key output is connected to the information input of the D-trigger and the other output of the resistor, the input is connected to the output of the first OR-NOT element, and the control input is connected to the output of the AND-NOT element. The first and second inputs of the AND-NOT element are connected respectively to the output of the third OR-NOT element and to the additional input of the device.

 The disadvantage of this memory cell is the small amount of stored information.

 A well-known memory cell (see RF patent 2042268 from 06/28/91, MKI N 03 K 23/64, "Pulse counter in the Gray code", Dikarev II, Shishkin GI, publ. 08/20/95, Bull. 23), containing bits from zero to N-th, consecutive RC circuits by the number of bits, a demultiplexer, two switches and in each bit an asynchronous D-trigger and a multiplexer containing two bidirectional keys and an OR-NOT element, whose inputs are addressable multiplexer inputs. In each category, the outputs of the bidirectional keys are connected to the trigger input and to the corresponding input of the first switch, the output of which is connected to the output of the second switch, the inputs of which are connected to the first outputs of the corresponding RC circuits, the second outputs of which are connected to the common bus. The demultiplexer input is connected to the first input bus, the address inputs are connected to the second input bus and the corresponding address inputs of the switches, and the outputs are connected to the first inputs of the OR-NOT elements of the corresponding bits, the second input of the OR-NOT element of each bit is connected to the control input of the first bidirectional key and is an input for recording information permission, and the output is connected to the control input of the second bidirectional key, the input of which is connected to the direct output of the trigger. Information on the second input bus changes when a signal is received on the first input bus. The input of the first bidirectional key is the information input of the discharge of the memory cell.

 The memory cell is the closest in technical essence to the claimed device and is taken as a prototype.

 The disadvantage of the prototype is the complexity of the device.

 The problem solved by the invention is the creation of a memory cell with a simpler circuit implementation while increasing reliability in memory storage mode.

 The technical result is achieved by the fact that in the memory cell containing the switch, N serial RC circuits, the first conclusions of which are connected to the corresponding inputs of the switch, and the second conclusions are connected to the common bus, asynchronous D-trigger, two bi-directional keys, the output of the first of which is connected to the input of the second bidirectional key and the input of the asynchronous D-flip-flop, the direct input of which is connected to the output of the second bidirectional key, the control input of which is connected to the output of the first logic element OR connected to Odom first logic gate NOR. New is that an additional multiplexer, a pulse counter, two synchronous D-flip-flops, two OR-NOT gates are introduced, the output of the second OR-NOT logic element is a data output of the memory cell, and the first input is connected to the inverse output of the asynchronous D-flip-flop, the input of which is connected to the output of the switch, the control inputs of which are connected to the corresponding outputs of the multiplexer, the first two inputs of which are connected to the corresponding outputs of the pulse counter, and the other two inputs of the multiplexer are address inputs of the memory cell, the pulse counter input is connected to the first input of the first logical element OR-NOT, the C-inputs of the first and second synchronous D-flip-flops, the direct outputs of which are connected respectively to the first and second inputs of the third logical element OR-NOT, the output of which is connected with the control input of the multiplexer and is the gate output of the memory cell, the inverse output of the second of the synchronous D-flip-flops is connected to the second input of the second logical element OR NOT, the direct output of the first of the synchronous D-three gerov is connected to the second input of the first logical element OR-NOT and the control input of the first bidirectional key, the input of which is the data input of the memory cell, the information inputs of the first and second synchronous D-flip-flops are respectively the write and read inputs.

 The specified set of features allows you to simplify the memory cell while increasing reliability in the data storage mode by introducing a pulse counter and a multiplexer.

 The drawing shows an electrical circuit diagram of a memory cell.

 The memory cell contains an OR-NOT 1 logic element, an asynchronous D-trigger 2, a bi-directional key 3, an OR-NOT logic 4, a bi-directional key 5, a pulse counter 6, synchronous D-triggers 7, 8, a multiplexer 9, an OR- NOT 10, switch 11, serial RC circuits 12-15, data input 16, address bus 17, write and read inputs 18, 19, gate output 20, clock input 21 and output. The first outputs of the serial RC circuits 12-15 are connected to the corresponding outputs of the switch 11, and the second to the common bus. The data input 16 is connected to the input of a bi-directional key 5, the output of which is connected to the output of the switch 11, the input of the asynchronous D-trigger 2 and the output of the bi-directional key 3, the direct output of the asynchronous D-trigger 2 is connected to the input of the bi-directional key 3, the control input of which is connected to the output logical gate OR NOT 4, the first input of which is connected to the input of the pulse counter 6, the C-inputs of two synchronous D-flip-flops 7, 8 and the synchronization input 21 memory cells, the direct outputs of the synchronous D-flip-flops 7, 8 are connected to the first and second inputs by the logic element OR-NOT 10, respectively, the output of which is connected to the control input of the multiplexer 9 and is the gate output 20 of the memory cell. The inverse outputs of the asynchronous D-flip-flop 2 and the synchronous D-flip-flop 8 are connected respectively to the first and second inputs of the OR-NOT 1 logic element, the output of which is the output of the memory cell, the first input of the OR-NOT 10 logic element is connected to the second input of the OR-NOT 4 and the control input of the bidirectional key 5. The information inputs of synchronous D-flip-flops 7, 8 are respectively the inputs of record 18 and read 19 of the memory cell.

 As the elemental base of the device, the 564 series, made according to CMOS technology, was selected.

 The memory cell works as follows.

 The memory cell has a data recording mode, a data reading mode and a storage mode in which dynamic data regeneration occurs.

 In recording mode, the data is fed to the input of the bidirectional key 5 through the data input 16, and the logical signal “1”, which allows recording, is fed to the data input of the synchronous D-flip-flop 7 through the recording input 18. On the edge of the clock signal supplied to the synchronizing input 21 of the memory cell , at the output of the synchronous D-flip-flop 7, a logical "1" signal appears, which is fed to the second input of the OR-NOT 4 logic element, at the output of which a logical "0" signal appears, which closes the bidirectional switch 3, which leads to the disconnection of the D- trigger 2 on its direct output. Logical signal "1" from the output of the synchronous D-flip-flop 7 also goes to the control input of the bidirectional key 5, as a result of which the data from the input of the data 16 of the memory cell goes to the input X of the switch 11 (it is the output). The same logical signal from the output of the synchronous D-flip-flop 7 goes to the first input of the OR-NOT 10 logic element, the output of which is the logical "0" signal, which is fed to the gate output 20 of the memory cell and the control input of the multiplexer 9, as a result of the outputs X, Y are connected to the address bus 17, the combination of signals on which determines the discharge address of the memory cell into which data is recorded.

 In the read mode, the data input of the synchronous D-trigger 8 through the read input 19 receives a logical signal "1". On the front of the synchronization signal supplied to the input 21 of the memory cell, a logical "1" signal appears on the direct output of the synchronous D-flip-flop 8, which is fed to the second input of the OR-NOT 10 logical element, after which the address of the memory cell from which the reading takes place data, similar to data recording mode. The data comes from the output X of the switch 11 to the input of the asynchronous D-flip-flop 2, from the inverse output of which the data goes to the first input of the logical element OR-NOT 1. From the inverse output of the synchronous D-flip-flop 8 to the second input of the logical element OR-NOT 1 logical "0", after which the data goes to the output of the memory cell.

 In the storage mode, at the inputs of the record 18 and read 19 there are logical “0” levels, and a synchronization pulse is fed to the synchronization input 21, which leads to the appearance of a logical “I” level at the output of the OR-NOT 10 logical element, which is fed to the control input of the multiplexer 9 . Its outputs X and Y are connected to the inputs XI and Y1, respectively, and the pulse counter 6 sequentially enumerates the addresses of the bits of the memory cell. On the front of the clock signal at the synchronization input 21 of the memory cell, the discharge address of the device changes accordingly, and the input of the asynchronous D-trigger 2 is disconnected from its direct output through the OR-NOT 4 logic element and the bidirectional switch 3. The information stored by the discharge of the device with the selected address (regenerated discharge) appears at the output X of the switch 11. The data from the direct output of the asynchronous D-trigger 2 goes to the input of the bidirectional key 3, at the end of the clock pulse, the logical signal is generated at the output of the OR-NOT 4 logic element " 1 ", as a result of which the bidirectional switch 3 is closed and the regenerated data is fed back to the input X of the switch 11 and then to the selected bit of the memory cell.

 The frequency of the clock pulses arriving at the synchronization input 21 of the memory cell must be such that, in the storage mode, the state of the bits of the memory cell is maintained in the intervals between the clock pulses (capacitors of RC circuits 12-15 must retain their charge).

 A laboratory model of a memory cell was made, tests of which confirmed the feasibility and practical value of the claimed object.

Claims (1)

A memory cell containing a switch, N serial RC circuits, the first pins of which are connected to the corresponding pins of the switch, and the second pins are connected to a common bus, an asynchronous D-trigger, two bidirectional keys, the output of the first of which is connected to the input of the second bidirectional key and the input asynchronous D-flip-flop, the direct output of which is connected to the input of the second bidirectional key, the control input of which is connected to the output of the first logical element OR-NOT, characterized in that the multiplexer is additionally introduced , a pulse counter, two synchronous D-flip-flops, two OR-NOT logic gates, the output of the second OR-NOT logical gate is the data output of the memory cell, and the first input is connected to the inverse output of the asynchronous D-trigger, the input of which is connected to the output of the switch the inputs of which are connected to the corresponding outputs of the multiplexer, the first two inputs of which are connected to the corresponding outputs of the pulse counter, and the other two inputs of the multiplexer are address inputs of the memory cell, the pulse counter input with It is connected to the first input of the first logical element OR-NOT, the C-inputs of the first and second synchronous D-flip-flops, the direct outputs of which are connected respectively to the first and second inputs of the third logical element OR-NOT, the output of which is connected to the control input of the multiplexer and is a gating output memory cells, the inverse output of the second of the synchronous D-flip-flops is connected to the second input of the second logical element OR NOT, the direct output of the first of the synchronous D-flip-flops is connected to the second input of the first logical element OR-NOT and the control input of the first bidirectional key, the input of which is the data input of the memory cell, the information inputs of the first and second synchronous D-flip-flops are respectively the write and read inputs.