RU2222100C2 - Memory location - Google Patents

Abstract

FIELD: pulse engineering, computer engineering, control systems. SUBSTANCE: device has switching unit, N series RC circuits, three input buses, address bus, read- out bus, multiplexer, asynchronous D flip-flop, NOR gate, two NAND gates, comparator, and pulse counter. EFFECT: enlarged stored information content. 1 cl, 1 dwg

Description

 The invention relates to the field of pulse technology and can be used in devices of computer technology and control systems.

 A well-known memory cell (see USSR AS 1706362 dated 02.04.90, MKI N 03 K 3/037, Trigger device, Eremin A.N., Shishkin G.I., published on 08.28.97, BI 24), containing a D-trigger, the first, second and third elements OR-NOT, the element NAND, bidirectional switch, resistor and capacitor. One of the resistor leads through a capacitor is connected to a common bus. The first and second inputs of the first OR-NOT element are connected respectively to the first installation input of the device and the output of the second OR-NOT element. The first and second inputs of the second element OR are NOT connected respectively to the second installation input of the device and the direct output of the D-trigger. The clock input of the D-trigger is connected to the output of the third OR-NOT element, the first and second inputs of which are connected to the first inputs of the first and second OR-NOT elements, respectively. The bi-directional key output is connected to the information input of the D-trigger and the other output of the resistor, the input is connected to the output of the first OR-NOT element, and the control input is connected to the output of the AND-NOT element. The first and second inputs of the AND-NOT element are connected respectively to the output of the third OR-NOT element and to the additional input of the device.

 The disadvantage of this memory cell is the small amount of stored information.

 Known memory cell (see RF patent 2042268 from 06/28/91, MKI N 03 K 23/64, the counter of the pulses in the code Gray, Dikarev II, Shishkin GI, publ. 20.08.95, BI 23). containing bits from the Nth to the Nth, consecutive RC circuits in the number of bits, a demultiplexer, two switches and in each bit an asynchronous D-trigger and a multiplexer containing two bidirectional keys and an OR-NOT element, the inputs of which are the address inputs of the multiplexer. In each category, the outputs of the bidirectional keys are connected to the trigger input and to the corresponding input of the first switch, the output of which is connected to the output of the second switch, the inputs of which are connected to the first outputs of the corresponding RC circuits, the second outputs of which are connected to the common bus.

 The demultiplexer input is connected to the first input bus, the address inputs are connected to the second input bus and the corresponding address inputs of the switches, and the outputs are connected to the first inputs of the OR-NOT elements of the corresponding bits, the second input of the OR-NOT element of each bit is connected to the control input of the first bidirectional key and is an input for recording information permission, and the output is connected to the control input of the second bidirectional key, the input of which is connected to the direct output of the trigger. Information on the second input bus changes when a signal is received on the first input bus. The input of the first bidirectional key is the information input of the discharge of the memory cell.

 The memory cell is the closest in technical essence to the claimed device and is taken as a prototype.

 The disadvantage of the prototype is the complexity of the device.

 The problem solved by the invention is the creation of a memory cell, characterized by the simplicity of the circuit implementation.

 The technical result is achieved by the fact that in the memory cell containing the switch, N serial RC circuits, the first conclusions of which are connected to the corresponding inputs of the switch, and the second conclusions are connected to the common bus, three input buses, a multiplexer and an asynchronous D-trigger, the input of which connected to the output of the multiplexer, and a direct output to the first input of the multiplexer, the second and third inputs of which are connected to the first input bus, the first address input of the multiplexer is connected to the second input bus, the inverse output of the asynchronous D-trigger connected to the first input of the logic element OR NOT.

 What is new is that an impulse counter is introduced, two NAND gate elements and a comparator, the first and second inputs of which are connected to the address bus, and the third and fourth inputs - with the first and second address inputs of the switch and the first and second outputs of the pulse counter, the input of which is connected to the second input bus, the second address input of the multiplexer is connected to the output of the first AND gate, the first input of which is connected to the third input bus, and the second input to the output of the comparator and to the first input of the second of an AND-NOT logical element, the second input of which is connected to the read bus, and the output - with the second input of the OR-NOT logical element, whose output is the output of the device, the input of the asynchronous D-trigger is connected to the output of the switch.

 The specified set of features allows to simplify the circuit implementation.

 The schematic diagram of the memory cell is shown in the drawing.

 The memory cell contains 4 bits (from zero to third), three input buses 1, 2, 3, read bus 4, address bus 5, output bus 6, switch 7, serial RC circuits 8 (8-0 ... 8- 3), asynchronous D-flip-flop 9, multiplexer 10, pulse counter 11, comparator 12, logical element OR-NOT 13, the first and second logic elements AND-NOT 14 and 15, respectively, and a common bus 16.

 The first and second inputs of the comparator 12 are connected to the address bus 5, and its third and fourth inputs are connected to the first and second address input of the switch 7 and to the first and second output of the pulse counter 11, the input of which is connected to the second input bus 2 and to the first address input multiplexer 10, the second address input of which is connected to the output of the first NAND gate 14, the first input of which is connected to the third input bus 3, and the second input to the output of the comparator 12 and to the first input of the second NAND gate 15, the second input whose oedinen the bus read 4, and its output is connected to the second input of OR-NO element 13 whose output is an output device.

 The first input of the OR gate 13 is connected to the inverse output of the asynchronous D-trigger 9, the direct output of which is connected to the first input of the multiplexer 10, the second and third inputs of which are connected to the first input bus 1, and the output to the input of the asynchronous D-trigger 9 and with the output of the switch 7, the corresponding inputs of which are connected to the first terminals of the serial RC circuits 8 (8-0 ... 8-3), the second terminals of which are connected to the common bus 16 of the device.

 The memory cell works as follows.

 When the supply voltage is turned on, a signal with a logic level of “0” is supplied to all the buses of the device, the pulse counter 11 is set to zero (the initial installation circuit is not shown), the output X of the switch 7 is connected to its input X0, so the serial RC circuit 8-0 is connected to the input of the asynchronous D-flip-flop 9. The remaining serial RC circuits (8-1 .. .8-3) are disabled. At the output of the logical element AND-NOT 14 there is a logical level of "1". therefore, the output X of the multiplexer 10 is connected to its input X2, and the input and direct output of the asynchronous D-trigger 9 are connected.

 When applying clock pulses to the second input bus 2 (clock input of the device), the pulse counter 11, sequentially sorting through its states, sequentially connects the serial RC circuits 8 (8-0 ... 8-3) to the input of the asynchronous D-trigger 9 and the output X of the multiplexer 10, which leads to the regeneration of data stored in the corresponding bits of the memory cell.

 The pulse counter 11 changes its state along the edge of the clock pulse and at the same time the connection between the input and the direct output of the asynchronous D-trigger 9 is broken, since at the given moment the output X of the multiplexer 10 is connected to its input X3. The frequency of the clock pulses must be such that during the time between the calls of the pulse counter 11 to any discharge of the device, the capacitors of the corresponding serial RC circuits 8 (8-0 ... 8-3) can lose only a small part of their charge so that they logical state at the time of the next request is preserved. This mode of operation of the device is a data storage mode.

 Writing data to the bits of a memory cell occurs as follows. A signal with a logic level of “0” is fed to read bus 4, a signal with a logic level of “1” is fed to input bus 3 (device write enable), data to be written to input bus 1 (data bus), and address bus 5 is fed the discharge address of the device where you want to write them.

 When applying clock pulses, the pulse counter 11 sequentially goes through its states (the device regenerates the stored data) and, when its state is equal to the address set on address bus 5, the comparator 12 generates a signal with a logic level “1” at its output. which arriving at the second input of the AND-NOT 14 logical element and causes the appearance of a signal at its output with a logic level of "0". This leads to the connection of the data bus 1 (through the inputs X0 or X1) to the output X of the multiplexer 10 and, through the output X of the switch 7, to the serial RC circuit 8 (8-0 ... 8-3) of the selected discharge of the device. When the pulse counter 11 switches to the next state (different from the address 5 installed on the bus), the device continues to perform data regeneration. This mode of operation of a memory cell is a data storage mode.

 Reading information is as follows. A signal with a logic level of “1” is fed to read bus 4, a signal with a logic level of “0” is input to input bus 3, and a discharge address of the device from where data must be read is sent to address bus 5. The operation of the pulse counter 11 and the comparator 12 is similar to the recording mode, while the signal from the output of the comparator 12 causes the output of the logical element AND-NOT 15 signal with a logic level of "0". The discharge data of the memory cell with the address set on address bus 5 comes from the output X of the switch 7 to the input of the asynchronous D-trigger 9, and its inverse output goes to the second input of the OR-NOT 13 logic element, the first input of which is supplied with a signal with a level logical "0". As a result, the read data appears at the output of the memory cell.

 A laboratory layout of the memory cell was made, made according to the drawing scheme, tests of which confirmed the feasibility and practical value of the claimed object. The layout was performed on 564 series microcircuits.

Claims (1)

A memory cell containing a switch, N serial RC circuits, the first pins of which are connected to the corresponding inputs of the switch, and the second pins are connected to a common bus, three input buses, a multiplexer and an asynchronous D-trigger, the input of which is connected to the output of the multiplexer, and the direct output - with the first input of the multiplexer, the second and third inputs of which are connected to the first input bus, the first address input of the multiplexer is connected to the second input bus, the inverse output of the asynchronous D-trigger is connected to the first input of the logic element OR-NOT, characterized in that the pulse counter is additionally introduced, two NAND gates and a comparator, the first and second inputs of which are connected to the address bus, and the third and fourth inputs - with the first and second address inputs of the switch and the first and second the outputs of the pulse counter, the input of which is connected to the second input bus, the second address input of the multiplexer is connected to the output of the first logical element NAND, the first input of which is connected to the third input bus, and the second input to the output of the comparator and to the first input the second AND-NOT logical element, the second input of which is connected to the read bus, and the output is connected to the second input of the OR-NOT logical element, the output of which is the device output, the asynchronous D-trigger input is connected to the switch output.