RU2214066C2 - Memory architecture for multiple-format video- signal processor unit - Google Patents

Abstract

FIELD: video signal processing means for display. SUBSTANCE: digital processor unit has standard architecture and has input circuit, decoder, memory for saving formatted high-resolution data and standard-resolution data, and display processor designed for processing mentioned data of different resolution. Processing of video signals includes their reception, identification, decoding, conversion of block pixel format data into format suitable for display, and saving of mentioned pre-processed data of standard- resolution format in mentioned memory in the course of processing. EFFECT: ability of concurrent processing of standard- and high-resolution data. 14 cl, 22 dwg, 2 tbl

Description

FIELD OF THE INVENTION
The invention relates to the processing of video signals for display.

State of the art
Compressed video transmission systems, such as systems using the MPEG2-2 compression format (cinematography expert group standard) ("Encoding of moving images and associated sound", ISO / IEC JTC1 / SC29 / WG11 702 (revised) May 10, 1994) broadcast digital TVR (high-resolution television) signals from a number of control locations. Soon it is planned to begin broadcasting commercial programs when the first TVP TV receivers appear on the market. TBP signals are not compatible with current television receivers, such as television receivers for processing standard NTSC signals in the United States. Therefore, a transitional period will occur during which CP (standard definition) television signals conforming to NTSC or PAL television standards will continue to be transmitted on television in order to prevent the CP television receivers from becoming obsolete immediately. Also, for some period of time, the preparation of some programs will not be available in MPEG2 format, as television broadcasters will face a change in logistics.

 Video data is transmitted in various formats (for example, with 4: 3 or 16: 9 picture display compression ratios, 4: 4: 4, 4: 2: 2 and 4: 2: 0 data sample formats; interlaced and non-interlaced scans) and with various spatial resolution (for example, 352, 480, 544, 640, 720 ... 1920 pixels per line and 240, 480, 720, 1080 active lines per frame). It is usually impractical for both aesthetic and cost reasons to equip video receivers with the ability to display decompressed signals in their format before transmission. Better post-decompression processing schemes are preferably included to transcode the various formats of the decompressed video data into the desired display format.

 There are many transcoding systems or space-time conversion systems known to those skilled in the art of video processing. Typically, each is aimed at a specific type of conversion, such as converting interlaced to non-interlaced scanning or doubling the sampling frequency, row frequency or field frequency.

Even if the video decompression systems contain a suitable number of circuits, it is desirable to use additional circuits for processing uncompressed or standard-resolution video signals. The post-processing schemes included in the receiver could transcode the SR video signal without significantly increasing the number of transcoding schemes. This is difficult because "digital television signals formatted in accordance with MPEG2 enter the MPEG2 compatible display processor in a decoded pixel block format. CP television signals typically arrive at the display processor as multiplexed analog YC _R St pixel-ready display lines (raster scan) in a 4: 2: 2 ratio in either NTSC or PAL format, and also lower resolution CP signals than many of the high resolution (BP) mappings associated with MPEG2 BP signals. increasing the frequency, which correctly compensates for the movement occurring in the image, is a complex process, since the image is temporarily present as interlaced field data. Considerable memory is required to create an image frame suitable for display.

SUMMARY OF THE INVENTION
In accordance with the present invention, the digital video processing system receives both MPEG2 compatible data and non-MPEG2 compatible data. A display processor including a block-to-line converter for processing data of block MPEG2 format and converted from lines to data blocks of non-MPEG2 format receives digital video data. The shared memory stores MPEG2 format data and MPEG2 non-format data during processing by the said system.

Brief Description of the Drawings
Figure 1 depicts a block diagram of an embodiment of the present invention.

 2A is a block diagram of a CPEG / TBP MPEG2 decoder and display processing circuits using the present invention.

 FIG. 2B is a block diagram illustrating an embodiment of an MPEG2 decompressor as used in FIG. 2A.

 Fig. 2C is a block diagram of a display processor of Fig. 2A.

 Figure 3 illustrates an example of converting strings to blocks.

 4A, 4B through 8A, 8B illustrate various signal format transformations implemented by a decoder circuit.

 FIG. 9 is a block diagram of a signal path through a receiver including a decoder in accordance with the present invention.

Description of the preferred embodiment
FIG. 1 illustrates the basic elements of a preferred embodiment of the invention. The compressed MPEG2 data from the compressed data input (SD) and from the MPEG2 input provide compressed MPEG2 data to the MPEG2 decoder 16. MPEG2 data can be any data compressed and transmitted in the MPEG2 standard settings. This includes, for example, high resolution data and standard resolution data. The data decoded in accordance with MPEG2 is supplied to the block memory 20, and from there to the display processor 40. Non-standard definition MPEG2 data, such as data formatted in accordance with CCIR601, is received by the CP interface 22, which receives line data and converts it to block data. Block memory 20 receives standard resolution (CP) data in block format from the CP interface 22 and feeds, if required, to the same display processor 40. The display processor 40 receives the block data through the memory 20 from both sources and provides formatted data in accordance with the conversion of the blocks into rows and the compression ratio to the desired display device. The tire structure between the elements 16, 20, 22 and 40 may be a common bus, as shown, or separate tires connecting each of the elements 16, and 22, and 40 with the element 20.

 2A is a block diagram of a portion of a compressed video decoder including display processing circuits for converting signals arriving in various formats to a preferred format or formats. All of the illustrated circuits, with the possible exception of external memory and system control, can be included in one integrated circuit or not included depending on the requirements of a particular system. The device of FIG. 2A may be included, for example, in an advanced television receiver (USP) including tuner / IF circuits, interlace elimination circuits, error correction circuits, and reverse transfer circuits to provide, for example, MPEG2-compressed digital video signal. The device of FIG. 2A assumes that the television receiver will provide, for example, decoded NTSC, PAL, or SECAM signals (all referred to as CP) in digital format, such as CCIR601. In addition, the device of FIG. 2A receives and decodes compressed video signals from other sources, which can transmit with constant or variable frequencies both continuously and in packets. Other data formats may be input to decoder 10 by adding a converter to provide a signal in an acceptable format. Such data formats may be formats known, for example, in the computer industry, for example RGB, VGA, SVGA, etc.

 Decoder 10 includes an input interface 12 that connects external compressed video data other than the video data CP to a decoder. For example, the input interface 12 is connected to the system-wide controller 14, to the primary MPEG2 unpacker 16, and to the memory interface 18. The input interface 12 connects external data and control signals to various parts of the decoder 10 via a read bus, the bit capacity of which in this example is 21 bits. The compressed video data is extracted from packets formatted according to MPEG2 and buffered in the external memory 20 before unpacking.

 Non-MPEG2 standard definition digital video data is supplied directly from an external source to the CP interface 22 via an 8-bit bus. CP data is received in a digital raster string format, i.e. line by line. The CP interface 22 is operated by the KLP 24 (local memory controller), transferring the CP data to the external memory 20 as pixel block data compatible with the input requirements of the display processor 40. Since the CP data is inline formatted pixel representations, the pixel data is simply reorganized locally into pixel blocks when they are written to memory 20. Converting the CP data into pixel blocks favorably allows processing both the CP data and the decompressed MPEG2 data by the same display processor.

 The CP interface 22 is simpler and less expensive than the parallel display processor 40 or providing a second compatible display processor. Parallel switching requires reprogramming and reconfiguring many of the elements in the display processor 40 for control when the CP data is received, since pixel data blocks are not processed in the same way as bitmap line data. The CP interface 22 is an uncomplicated element that controls certain tasks. These tasks include receiving and counting a certain number of pixels in a row, guaranteeing the correct amount of information that is always output to external memory 20, and not outputting data during erasure periods. In addition, KLP 24 requires only a simple algorithm to control the reorganization of data received by the SR interface.

 FIG. 3 illustrates one example of the reorganization of data from an inline form to a block form. Typically, the data received by the CP interface 22 is digital. However, a converter (not shown) can easily be added to or in front of the input of the CP interface 22 to digitalize the data when necessary. Rows A through L represent pixel data having a 4: 2: 2 compression ratio and a bitmap line format. Data series continue in accordance with the accepted data format. The CP interface 22 reorganizes the data by dividing the brightness value and the U and V color values. Luminance data is grouped into 8x4 blocks, and color data U and V are grouped into 4x4 blocks. The color data blocks include odd data positions in block U and even positions in block V. Also during the reorganization, the compression ratio is converted from 4: 2: 2 to 4: 2: 0, however, the compression ratio will depend on the requirements of the input data of the display device . Reorganization data is stored as blocks in the external memory 20.

 Compressed data that can appear only once, which can be received with a variable frequency or which can be received in packets, is received by the decoder 10 via the SD priority interface 32 (compressed data). When data is in the LED interface 32, the decoder 10 prioritizes the operation of the interface to ensure proper reception. Interface 32 SD receives compressed video in a format compatible with MPEG2. Interface 32 LED includes a buffer with 8-bit input and 128-bit output, which converts the data and sends them to external memory 20 before unpacking.

 The external memory 20 is also connected externally to the decoder 10 and may be 96 Mbit for high-definition television signals. The connection is a 64-bit bus connected through a multiplexer / demultiplexer 26. Block 26 converts data from the 128-bit data bus of the internal memory (memory bus) to a 64-bit memory bus. KLP 24 controls the reading / writing of external memory 20 upon request of various interfaces and various processing circuits. KLP 24 is programmed to store video data in memory 20 in block format, where the block is consistent with the 8x8 pixel data block structured in accordance with MPEG2.

 The decoder 10 uses an external memory of 20 frames as a receiving and synchronizing buffer for compressed video data due to its memory capacity. A large memory space is required to buffer incoming data before unpacking. Inserting this buffer into an integrated circuit disadvantageously consumes significant physical space. Buffering also facilitates the formation of pixel blocks for frame recovery. Additional overhead information is cut out by the initial code detector 34, which receives the information necessary for unpacking.

 Compressed video input is extracted from external memory for initial decompression and fed through the memory bus to MPEG2 unpacker 16. Other types of unpacking can be used without affecting the essence of the present invention. The decompression in accordance with MPEG2 of the predicted frames requires that the previously decompressed “reference” frames are stored in memory and retrieved when required for decompressing and restoring the image. The device of FIG. 2A preferably includes secondary compression of the MPEG2-decompressed video data before the finished frames are stored in the memory 20, thereby significantly reducing the amount of external memory required in the receiver. Secondary compression is hereinafter referred to as re-compression.

 The first compression and subsequent decompression is the formatting of the data in MPEG2 format for transmission in the transfer stream. 2B is an example of an MPEG2 decompressor. Unpacker 16 of FIG. 2A is enlarged to display the necessary features of MPEG2 unpacker. The encoded, compressed in accordance with MPEG2 data is received on the read bus by the variable length decoder 100 (DPD). The DPD 100 transmits decoded data to a digital-to-analog converter 102, which transmits the analog data to an analog processor 104, which creates block-based unpacked data in accordance with MPEG2. This data is combined with data from the moving image processor 108 in combiner 106 and transmitted to the re-compression device 28.

 The recompressor 28 is different from the MPEG2 compression in the MPEG2 encoder and can be applied in many forms. For example, re-compression may include block-based differential pulse code modulation and subsequent fixed, variable, or variable-length coding. Alternatively, it may include block-based Huffman coding. Compression can be lossless or lossy.

 Re-compression is performed according to FIG. 2A by a compression device 28 connected between an MPEG2 unpacker 16 and a memory bus. Thus, the decoded and decompressed MPEG2 video data is supplied to the compression device 28 for re-compression of the data and then stored in the external memory 20. When the re-compressed video data is extracted to restore the predicted MPEG2 frames in the moving image processing network, they are first fed to the unpacker 30, which operates opposite to the compression device 28. The extracted data after passing through the unpacker 30 is in a state for use by the MPEG2 decoder 10 to recover predicted s frame compensation processing in the motion picture.

 Both the unpacked high-resolution video frames and the CP video frames are extracted from the external memory 20 and supplied to the display processor 40 via the memory bus for processing before displaying or storing as component signals with the desired compression ratio and image resolution, as shown in Fig. 2C. Data extracted from the external memory 20 is supplied to the display processor 40 via the reverse store type (UOMT) devices 42, 44, 46, 48, 50, which perform two functions. The first is temporary data buffering. The second is the conversion of sixteen bytes (128 bits) of data from the memory bus into one bytes of bit width (MPEG2 data for unpacker 52) or four bytes of bit capacity (CP data for a linear adaptive converter with increasing frequency of a moving image (LAPCHDI) 54). The indicated bit sizes in bytes are exemplary.

 A display processor 40 is depicted in FIG. 2C. In the display processor 40, the re-compressed MPEG2 video data is first supplied to the unpacker 52, which is similar to the unpacker 30. The unpacker 52 provides the unpacked video components of the luminance (Y) and color of the image (C) on a block basis. Unpacked in accordance with MPEG2 constituent signals from the unpacker 52 are fed into the respective converters 56 and 58 of the blocks in the line of brightness and color. The block converters in the line feed Y and C components of the signals line by line into the vertical converter of the luminance format (VLF of luminance 60) and the vertical converter of the format of chroma (VLF of luminance 62), respectively. Both luminance and chrominance converters 60, 62 include circuits for vertical format conversion and horizontal conversion of sample frequency. The vertical and horizontal converters are separated by inverse store-type devices to control the synchronization of transitions between the converters.

 Sampling frequency converters are programmable in accordance with the parameters of a particular system and can increase or decrease the number of lines in an image and / or increase or decrease the number of pixels in a line. The luminance and chrominance components of the data from the sampling rate converters are combined into a screen display (EO 64), which is selectively aligned when it is known to superimpose text and / or graphic objects onto the component video signals. Either the system controller 14 or the input data stream can provide EO data that is stored in the external memory 20 via a non-block basis.

 Decoder 10 advantageously includes circuits for eliminating the alternation of CP image formats and an output signal of 480 (active) sequential scan lines. These patterns are located in LAPCHDI 54. The SR image format has 480 active interlaced lines. To provide higher vertical resolution for display on a high resolution monitor, the output signal is increased to 480 active consecutive lines.

 LAPCHDI 54 performs the linear conversion required by the output image display device and caused by alternating fields from the image frame. The CP signal is stored and subsequently retrieved from the external memory 20, because LAPCHDI 54 requires the CP signal at the same time from neighboring fields to calculate the image movement and generate the serial signal with the same or higher resolution. This is not motion compensation, as is known in the MPEG2 format. For each field, the corresponding lines pass through LAPCHDI 54, which evaluates the lines intermediate to the field lines based on the magnitude of the image movement. The movement of the image is estimated from the differences between the corresponding pixel values in the previous and subsequent fields. If the magnitude of the motion is generally zero, then the average of the row from the previous and subsequent fields is used as the estimated row. If there is a high degree of movement for the estimated pixels, then the pixel value is estimated from the average of the line above and the line below the intermediate line in the current field. If there is only a small degree of movement, then the intermediate line is estimated from a combination of the line in the previous field and the averaged lines from the current field. The greater the presence of movement, the greater the average of the lines above and below the current line from the current field is used relative to the interlaced line from adjacent fields. More preferably than limited memory 20 for providing adjacent lines for averaging lines, the memory internal to the block converter in the luminance line 60 is advantageously used to simultaneously provide the video signal from neighboring lines in LAPDCH 54. However, only the previous or next line is accessible from the line memories in the converter 60 In addition, LAPCHDI 54 can clarify frames using filters and line and / or field delays based on movement within the frame.

 LAPCHDI 54 requires memory for processing BP data, since the image frame is represented in two alternating fields that must be temporarily processed in order to correctly restore the motion information from the original image. Processing cannot be completed until adjacent rows from both fields are available. The image field for CP data is approximately 240 active lines. It is preferable to provide additional internal memory for this function, as was done earlier, the processed data can be stored and retrieved from memory 20. A significant part of memory 20 is available, since it is not fully used, as it would be for processing BP data (described above ) By sending the data from LAPCHDI 54 to the memory 20, rather than providing local memories in the integrated circuit of the display processor, the size and cost of the integrated circuit is reduced. Due to the existing memory buses of the data read bus, and the data write bus, and the firmware associated with the LAPCHDI 24, the transfer to the memory 20 is fast and efficient.

 Data can be fed into and out of the memory bus through the UOMT memory, internal to the processing elements (not shown to simplify the drawing). The elements of FIG. 2A have input and / or output devices of the reverse store type, which allow the decoder 10 to operate in a seamless manner. When loading a data segment into buffers / UOMT, each element can access the memory bus when it becomes available, while maintaining a constant data stream inside the processing element.

 The display processor has two separate clock generators controlling the individual sections, an unpacking clock generator region 66 and a display clock generator region 68, as seen in FIG. 2C. Region 66 of the decompression clock generator contains all functions that must be synchronized with direct access memories 56, 58 converting blocks into lines, and must be performed with a clock frequency of 40 to 81 MHz to obtain the required frequency band. The display clock generator region 68 contains functions that are executed synchronously with the final output with clock frequencies from 27 to 81 MHz. Two clock generators can operate at the same frequency or at different frequencies depending on the application. The video data passing between the two regions of the clock generator passes through the UOMT 71, 73 (each separately for luminance and color) when a read request is made for reverse store-type devices coming from the controller of the converter of horizontal sampling speed.

 Each UOMT includes a control logic that is sensitive to acknowledgment and read and write requests from the display processor 40 and the CLP 24. A control logic also exists to track the amount of data in the corresponding UOMT and to control the asynchronous interface between the end of the UOMT bus that uses the same clock generator as the data bus, and the end of the WOMT “display” that uses the decompression clock. Since the display section contains a control logic, the number of circuits actually operating outside the “bus” clock is desirably minimized.

 Primary or decompressed in accordance with MPEG2 data (except secondary re-compressed data) is selected from the external memory 20 on a block-by-block basis and fed through the UOMT3 46 and UOMT4 48 to the secondary brightness and color decompressors, which provide the unpacked pixel block brightness and color values. Blocks of unpacked pixel values of brightness and color are supplied to the corresponding converters 56 and 58 of the blocks in the line containing the local memory PPD. Continuous rows of 8x4 blocks (brightness) and 4x4 blocks (color) are recorded in the corresponding local memory. The memory is read line by line or in multiple lines in parallel, depending on the current function of the converter circuits connected to the external memory. When data is read, new data is written to this location to minimize the amount of local memory required. The approximate sizes for local memories of converters 56 and 58 blocks per line are 16 bytes of capacity for 960 words of depth and 16 bytes of capacity for 720 words of depth. Local memories include input multiplexers and output multiplexers for arranging the input data into 16-byte data for storing in local memory and for appropriately arranging 16-byte data read from the memory for use by an appropriate vertical sampling rate converter.

 The horizontal and vertical sampling rate converters for processing the MPEG2-decompressed video data to be displayed on a 16: 9 high-resolution display device will perform the linear transforms listed in Tables I and II (see end of description), respectively. The horizontal converter must allow a maximum output frequency of 81 MHz pixel.

 Tables I and II describe the conversion of the luminance signal. Similar conversions are performed on color signals. Regarding color, the compressed signal is in a 4: 2: 0 format, and the above color conversion includes an additional conversion from 4: 2: 0 to 4: 2: 2. Typically, color processing will be included along with any other vertical conversion required. For vertical color conversion, a two-tap multiphase filter is usually used for combined re-quantization and conversion of 4: 2: 0 to 4: 2: 2.

 When considering Fig.4-8, it may seem that the crosses and circles are not aligned or incorrectly aligned. Despite the fact that the figures really approximate the placement, the general ratio of the cross to the circle is correct. Apparent misalignment or alignment is correct and is due to an integer transform coefficient.

 FIG. 4 illustrates the graphically vertical / time relationship of input and output color strings when only 4: 2: 0 to 4: 2: 2 conversion is required (i.e., accept 480 serial and display 480 interlaced or accept 1080 serial and display 1080 interlaced). Figure 4 represents a portion of the lines in a field. The circles represent the original pixels in 4: 2: 0 format. The crosses represent the pixels of the converted 4: 2: 2 signal. The interpolated lines in each field are calculated from the lines in the corresponding field. Figure 4 depicts a display based on the field. In this case, even chroma lines (starting from line 0) are used to generate the first or top field, and odd chroma lines are used to generate the second or lower field.

 5A and 6A illustrate luminance conversion options in a view similar to that described with respect to FIG. 2A. 5A illustrates the vertical and temporal relationship of input and output brightness lines when 720 serial format is converted to interlaced 1080 format. 6A illustrates the vertical and temporal relationship of input and output brightness lines when 720 serial format is converted to interlaced 480 format.

 FIG. 5B and 6B illustrate respective color conversion options with respect to the luminance transforms described above. 5B depicts the vertical and temporal relationship of input and output color strings when 720 serial format is converted to interlaced 1080 format. FIG. 6B illustrates the vertical and temporal relationship of input and output color strings when 720 serial format is converted to 480 interlaced format.

 No temporary processing is included in these exemplary transformations. Processing of brightness and color occurs only in the vertical direction. In addition, the input color information is frame-based, and only 4: 2: 0 to 4: 2: 2 conversion based on the frame needs to be considered.

 Figa and 7B are different. Fig. 7A depicts the vertical and temporal dependence of input and output brightness strings when 1080 interlaced format is converted to 480 interlaced format. Fig. 7B depicts the vertical and temporal relationship of input and output color strings when 1080 interlaced format is converted to 480 interlaced format.

 FIG. 8A and 8B illustratively illustrate a vertical conversion of luminance and color, respectively, of a video signal CP performed by LAPCHDI 54. Recall that vertical and temporal processing is included in these transformations rather than just vertical processing. Usually, the operation of the striping elimination algorithm is required only for image sizes up to 720x480 interlaced (i.e., CCIR601 resolution). These images can come from the MPEG2 decoding process or as input from the input port of the CP.

 FIG. 9 is a block diagram of a signal path through a receiver including a decoder, in accordance with the principles of the present invention. The input signal is received by the receiver in block 120. The input signal is formatted as a signal compatible with MPEG2 or incompatible with MPEG2, as described above. The signal format is determined in block 122 and a specific signal is sent to a suitable processing route. If the signal format is compatible with MPEG2, the signal is decoded in block 124, as described above, and block data compatible with the display processor is created and stored in memory 20. If the signal is incompatible with MPEG2, the signal is processed and stored in memory 20 in block 126 as described above. This data is also block data compatible with the display processor 40 of FIG. 1. Block data compatible with the display processor is transmitted to the display processor 40 from the memory 20. Block 128 creates formatted data that is compatible with a particular display device or other storage device. Data requiring higher resolution is transferred between the display processor 40 and the memory 20 during such processing. Finally, data compatible with the display device is sent to the display device (or storage medium) in block 130.

 The general architecture, which is disclosed above, is applicable for storing field information and image frames in the memory 20 during other processing of standard definition data, as well as when the memory 20 is not used otherwise. For example, standard-resolution data is often filtered by a combined filter that can use enough memory to store a field or image frame. This memory is usually separated from the memory used for other functions. By using the general structure described above, frame memory can be used, thus saving design and implementation costs. Screen display may also use memory 20 in a similar manner to eliminate the need for separate memory.

Claims (14)

 1. A digital processor having a common architecture for processing video signals in a variety of formats, comprising an input circuit for receiving formatted high-resolution video data and formatted standard-definition video data, a decoder coupled to said input circuit to generate formatted high-resolution video data and formatted standard-format video data permissions, a memory for storing high-resolution formatted data for processing by the processor, and a process a display p for processing said high resolution formatted data for display purposes, wherein said digital processor further comprises a converter coupled to said input circuit for converting said standard resolution formatted data into a block pixel format compatible with high resolution formatted data, said memory provides shared memory for storing high-resolution data and converted standard-resolution data in processing time by said processor, and said display processor also processes said converted standard definition formatted data for display.  2. The processor according to claim 1, characterized in that said decoded and decompressed high-resolution data is presented in block pixel format, said high-resolution data is compatible with the MPEG2 cinematography expert group standard, said display processor receives video data in block pixel format, and said converter converts said standard resolution data into a block pixel format.  3. The processor according to claim 1, characterized in that said input circuit receives packet compressed data.  4. The processor according to claim 1, characterized in that said memory receives data based on data blocks and field and frame data in a raster format.  5. The processor according to claim 2, characterized in that it further comprises a re-compression device for re-compression of the data decoded and decompressed in accordance with the MPEG2 standard before storing in said memory.  6. The processor according to claim 1, characterized in that said display processor is programmable to provide an output video format compatible with a display device connected to said display processor.  7. The processor according to claim 1, characterized in that said input circuit includes an input for receiving data of the MPEG2 format and an input for receiving data of a format other than the MPEG2 standard, said display processor includes a data block to string converter for processing block data the MPEG2 standard format and converted from strings to data blocks of a format different from the MPEG2 standard format, and said shared memory stores said data of the MPEG2 standard format and said data other than the MPEG2 format standard, while The processing name of the processor.  8. The processor according to claim 7, characterized in that said memory receives data based on data blocks and field and frame data in a raster format.  9. The processor according to claim 1, characterized in that it comprises a first processing route associated with said first circuit, comprising an input for receiving MPEG2 format information, an MPEG2 decoder corresponding to said decoder, and said display processor having an output for transmitting information image to the display device, a second processing route associated with said input circuit comprising an input for receiving standard resolution format information, a converter of data lines into data blocks, and said processor imagery, switching means for selectively transmitting display information to said display output along said first and said second processing routes and in which said shared memory is block based and data is transferred to and from memory in said first and said second processing routes, said display processor includes means for changing the resolution of said standard resolution format information, and said switching means remembers said inf Formation of a standard resolution format in said memory during processing.  10. The processor according to claim 9, characterized in that said memory receives data based on data blocks and field and frame data in a raster format.  11. A method of processing video signals in a variety of formats, comprising the steps of: receiving a signal containing data to be processed, identifying said received signal as one of the signals: an MPEG format signal or a standard resolution format signal, decode the input MPEG format signal for generating pixel block format data at reception, bring said block pixel format data to a format suitable for displaying an image, save said the data in MPEG format in memory during processing, and transmit the data adapted to the display to a display device, characterized in that said method further comprises preprocessing the input signal in a standard resolution format to generate block pixel format data compatible with said format signal MPEG, and save said pre-processed standard-resolution format data in said memory during processing.  12. The method according to claim 11, characterized in that at said pre-processing step, said conversion of data in a row format or data in a block pixel format is carried out.  13. The method according to claim 11, characterized in that at the said stage of alignment transform the data of the block pixel format into the data of the line format.  14. The method according to claim 11, characterized in that said memory receives data based on data blocks and field and frame data in a raster format.

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