RU2169945C2 - Relational processor for identifying data signal by bit of its affiliation to submedian or supermedian subsets of analog signal array - Google Patents

Abstract

FIELD: automatic control; data ranking and sorting. SUBSTANCE: device has input demultiplexer and output multiplexer; demultiplexer and multiplexer incorporate relaters each having comparator and switch-over channels with circuit closing and opening switches. EFFECT: simplified design. 4 dwg

Description

 The invention relates to automation and analog computing and can be used to identify and select one of the signals belonging to a given set of analog signals, for tolerance control of an information signal based on its belonging to submedian or supramedian groups of rank variables, etc.

Relative ranking (sorting) devices are known that, when an even number n of analogue signals x ₁ , x ₂ , ..., x _n are combined, when combining their outputs in the form of a group (sub-median and supra-median), these two outputs identify the operation of identifying one of the input signals on the basis of its belonging to the submedian or supramedian groups of signals (see, for example, AS USSR 13650995).

 A disadvantage of the known devices when used as a submedian-supramedian identifier is hardware redundancy in the number of analog keys used.

 The closest in the set of features to the proposed solution is a relational multi-threshold functional converter (AS USSR 1621054, G 06 G 7/25, Fig. 3), which, when combining its outputs into two groups (sub-median output and super-median output) reproduces identifications information signal on the basis of its belonging to the submedian or supramedian subgroups of a given set of analog signals.

 The prototype uses the smallest possible number of relators and fewer keys compared to known devices, but it remains redundant in terms of the number of keys used during its operation in the submedian-supramedian identification mode.

 The essence of the invention is to reduce hardware costs through the use of the minimum required number of analog keys.

 The specified technical result in the implementation of the invention is achieved by the fact that in the prototype with an even number of n driving signals, n-1 relators are used, each relator contains 2i (i = 1, 2, ..., n-1) switching channels, inverting the inputs of all comparators the relators are combined and form the information input of the device, to which one of the signals of the master set of analog signals (information signal) is supplied, and the remaining signals of the master set, outputs of which of each previous relator are connected respectively to the switching inputs of the subsequent relay, the outputs of the last relay are the outputs of the device, and the combined inputs of the switching channel of the first relay are the identifying input of the device.

 The technical result in the implementation of the invention is achieved by the fact that the (0.5n + 1) -th input relay of the multiplexer contains i-1 switching channels, and in each subsequent relay the number of channels is reduced by one until the output relay of the multiplexer reaches one switching channel, in the middle the outputs of each i-th relay of the multiplexer, the even outputs of the previous (j-1) -th switching channel are connected to the odd outputs of the subsequent j-th switching channel of the relator, each (j-1) -th middle outputs of the output the demultiplexer relay is connected respectively to the jth switching input of the first multiplexer relay (i = 0.5n + 1), the first outputs of all multiplexer relators (i = 0.5n + 1, 0.5n + 2, ..., n-1 ) and the output relay of the demultiplexer (i = 0.5n) are connected and form the submedian output of the relator processor, the last outputs of all relators of the multiplexer and the output relay of the demultiplexer are connected and form the supramedian output of the relator processor, and in the demultiplexer the switching inputs of the first relay (i = 1) are combined and form an identity iruyuschy relator switching input processor.

The electrical circuits of the relational processors with an even number of driving signals x ₁ , x ₂ , ..., x _l , ..., x _n when choosing one of them (x _l = x) as the information are shown in FIG. 2 (n = 4), FIG. 3 (n = 6) and FIG. 4 (n = 8).

 Relatory processors are built on n-1 relators 1,2, ..., i, ..., n logic elements that reproduce the elementary operations of the predicate algebra of choice.

аналоговых однополюсных ключей, состояние которых (замкнут, разомкнут) управляется выходным напряжением этого же компаратора (выход компаратора K соединен с управляющими входами ключей S_j и

). Зачерненными кружками на фиг. 1-4 обозначены входные выводы размыкающих ключей. Незачерненными кружками обозначены инвертирующие входы компараторов K реляторов RL_i, которые являются инвертирующими компараторными входами реляторов. Неинвертирующие входы компараторов являются неинвертирующими входами реляторов.Each relator (Fig. 1) contains a comparator K and a group of closing S _j and opening

analog single-pole keys, the state of which (closed, open) is controlled by the output voltage of the same comparator (the output of the comparator K is connected to the control inputs of the keys S _j and

) The black circles in FIG. 1-4 indicate the input terminals of the disconnecting keys. The open circles indicate the inverting inputs of the comparators K of the relators RL _i , which are the inverting comparator inputs of the relators. Non-inverting inputs of comparators are non-inverting inputs of relators.

) разнотипных ключей (замыкающий S_j, размыкающий

) образуют j-й переключательный канал j_i, релятора RL_i, где i есть порядковая нумерация реляторов, j - порядковая нумерация каналов в j-м реляторе RL_i. Входные и выходные выводы каждой пары (S_j,

) ключей являются соответственно входами и выходами j-го переключательного канала i-го релятора RL_i. Реляторы в процессоре разделяются на две последовательно соединенные группы: входная демультиплексорная D (реляторы 1, 2,..., 0,5n) и выходная мультиплексорная M группа (реляторы с нумерацией (0,5n+1, 0,5n+2,..., n-1), которые содержат соответственно 0,5n, и 0,5n-1 реляторов.Each pair (S _j ,

) different types of keys (closing S _j , opening

) form the jth switching channel j _{i of the} relator RL _i , where i is the ordinal numbering of the relators, j is the ordinal numbering of the channels in the jth relator RL _i . Input and output outputs of each pair (S _j ,

) keys are respectively the inputs and outputs of the j-th switching channel of the i-th relay RL _i . The relators in the processor are divided into two series-connected groups: the input demultiplexor D (relators 1, 2, ..., 0.5n) and the output multiplexor M group (relators with numbering (0.5n + 1, 0.5n + 2 ,. .., n-1), which respectively contain 0.5n, and 0.5n-1 relators.

In the relator processor, the inputs of each j-th switching channel of the i-th relay RL _i with i = 1,2, ..., n-1 are combined and form the switching inputs of the relators. In this case, the output terminals of the switching channel keys are the outputs of all processor relators.

All switching channels of the relays of the processor are made according to identical schemes, coinciding with the switching channel 1 ₁ (Fig. 1). For n = 2 (Fig. 1), the demultiplexer D contains one single-channel relator (0.5n = 1), and the multiplexer is absent (0.5n-1 = 0), i.e. the processor at n = 2 degenerates into a single-channel relator, for which the submedian x ^(m-1) and supramedian x ^{(m + 1)} values of the information signal coincide with the minimum and maximum values of the signal x on the binary set {x ₁ , x ₂ } signals.

 In the middle outputs of each i-th processor relay, the even outputs of the previous (j-1) -th switching channel are connected to the odd outputs of the subsequent j-th switching channel of this relay. In the demultiplexer from the first (i = 1) to the penultimate (i = 0.5n-1) relator, the first and last outputs of each previous relator are connected to the first and last switching inputs of the subsequent relator, respectively.

 The input relay of the multiplexer (i = 0.5n + 1) contains 0.5n-1 switching channels, and in each subsequent relay the number of switching channels decreases by one until a single switching channel is reached in the output relay of the multiplexer.

 Each kth median output of the last demultiplexer relay (i = 0.5n) is connected respectively to the kth switching input of the first multiplexer relay (i = 0.5n + 1).

 The first output of the output relay of the demultiplexer (i = 0.5n) and the first outputs of all the relays of the multiplexer are combined to form the submedian output of the relator processor, and the last output of the relay of the demultiplexer and the last outputs of all relators of the multiplexer are combined to form the supermedian output of the relator multiplexer.

 The switching input of the first relay of the demultiplexer (i = 1) is the identifying switching input of the relational processor.

The work of the relational processor is as follows. An identifying signal y is supplied to the processor switching input. One of n driving voltages x ₁ , ..., x _n , which is set as identifiable, is supplied to the processor information input.

Здесь x⁽¹⁾, x⁽²⁾,...x^(r'), x^(r''),...,x⁽ⁿ⁾ есть ранговые значения, которые может принимать идентифицируемый сигнал x на задающем множестве сигналов x₁,...,x,..., x_n (для фиг. 1-4 x=x_n);
r_i есть ранг (порядковый номер) i-й компоненты задающего (вектора) сигналов (x₁, . ..,x_n ), r'=m-1, r''=m+1; x^(m-1), x^(m+1) - субмедианное и супрамедианное значения сигнала x.The remaining n-1 driving voltages are randomly supplied to the non-inverting inputs of all relators. In this case, when operating in the identification mode by the submedian Z ₁ and supramedian Z ₂ outputs of the processor, the identification functions are reproduced

Here x ⁽¹⁾ , x ⁽²⁾ , ... x ^{(r ')} , x ^(r'') , ..., x ⁽ⁿ⁾ are the rank values that the identifiable signal x can take on a given set of signals x ₁ , ..., x, ..., x _n (for Figs. 1-4 x = x _n );
r _i is the rank (serial number) of the i-th component of the master (vector) signals (x ₁ , ..., x _n ), r '= m-1, r''= m + 1; x ^(m-1) , x ^{(m + 1)} are the submedian and supramedian values of the signal x.

For even n, the median value x ^{(m) of the} identified signal x does not exist and is mathematically defined as half-sum x ^(m) = 0.5 [x ^(m-1) + x ^{(m + 1)} ].

 When the relational processor is operating in the mode of selection of the information variable x, the identifying y and identifiable x signals are identified (y = x), which corresponds to the combination of these inputs when a signal x is applied to the combined input. In this case, the above expressions for identification functions are preserved when y is replaced by x.

To expand the scope of application, the rank processor can be used in the reverse signal transmission mode. To do this, the identifying signal y is simultaneously supplied to the outputs Z ₁ and Z ₂ (Fig. 1-4) of the processor (the outputs Z ₁ and Z _{2 are} combined), and the output signals in the processor are removed from the disconnected outputs of the switching channel of the first relay (i = 1) demultiplexer.

 The gain in reducing the total number of keys in the proposed circuit solution increases with increasing dimension n of the defining set of signals. In particular, with n = 4, 6, 8 in the prototype, it is necessary to use 6, 15 and 28 unipolar keys, respectively, and in the proposed circuit solution, 4, 9 and 16 keys are used, respectively.

Claims (1)

 A relatory processor for identifying an information signal based on its belonging to the submedian and supramedian subsets of the driving analog signals, containing the input demultiplexer and the output rank processing multiplexer of an even number of driving signals, the demultiplexer and the multiplexer containing relators, each of which contains a comparator, the output of which connected to the control inputs of the switching channels of the same relator, all inverting inputs of all to omparators are combined and form the information input of the relator processor, intended for one of the driving signals, the non-inverting inputs of all comparators are for the remaining driving signals, the switching channels of each relay of the demultiplexer consist of closing and disconnecting keys, the input and output outputs of which are the inputs and outputs of these channels, in each relay of the demultiplexer, the inputs of each switching channel are combined and form the switching inputs of the relators, in the demult the multiplexer in the relays from the first to the penultimate even output of the previous channel is connected to the odd output of the next channel of its relator, the first and last outputs of each previous from the first to the penultimate relay of the demultiplexer are connected respectively to the first and last inputs of the subsequent relay, characterized in that in each multiplexer in the subsequent relay, the number of channels decreases by one until the multiplexer reaches one switching channel in the output relay, in the multiplexer, starting from the second to the last but one, the even outputs of the previous switching channel are connected to the odd outputs of the subsequent switching channel of this relay, the outputs of the output demultiplexer are connected to the same switching inputs of the first relay of the multiplexer, the first output of the last relay of the multiplexer and the first outputs of all relays of the multiplexer are connected to the submedian output of the relator processor, the last output of the last demultiplexer relay and the last outputs of all mule relators tipleksora attached to supramediannomu relator output processor.

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