RU2126989C1 - Microprocessor - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has instruction execution unit and interface unit, which has terminals for connection to system bus. Goal of invention is achieved by introduced additional interface units, which are identical to existing one, and unit for system bus selection, which controls operations of interface units. This results in possibility to connect microprocessor to unlimited number of system buses and running information transmission in parallel for several system buses. EFFECT: increased efficiency. 3 cl, 3 dwg

Description

 The invention relates to computer technology, in particular to microprocessors.

 There are microprocessors, for example, "Information Processing Device" according to European application N 0241946, containing a command execution unit and having outputs for connecting to the system bus an interface unit, the inputs / outputs of which are connected by an internal information highway and a control line.

 The disadvantage of this microprocessor is its limited performance due to the fact that exchange operations on the system bus are performed strictly sequentially.

 The problem solved by the invention is to increase the performance of the microprocessor while maintaining the ability to use existing software.

 The fulfillment of this task is achieved by the fact that additional interface units identical to the existing one are introduced into the well-known microprocessor, as well as a system bus selection unit that controls their operation. The output of the command execution unit and the input of the system bus selection unit are connected by an information highway, the inputs / outputs are connected by a control line, and the resolution outputs of the system bus selection unit are connected to the resolution inputs of the interface units. The number of interface units corresponds to the number of system buses.

 The operation of the system bus selection unit is based on information transmitted through the information highway, which determines various versions of the microprocessor.

 In the case when data on the address is transmitted via the information highway, it is connected both to the input of the system bus selection unit and to the inputs of the interface units, while the data on the high-order bits are received only at the input of the system bus selection unit, the rest of the address goes to the inputs interface blocks and represents the physical address of the appeal on the system bus.

 In the case when data on the system bus number is received through the information highway, a block of system bus number registers is entered into the microprocessor, the input / output of which is connected by the information highway to the input / output of the command execution unit, and the number output by the information highway to the input of the system bus selection unit, the input / output of which is connected by a control line to the input / output of the command execution unit, whose control output is connected to the control input of the block of registers of the system bus number.

 The proposed solution to the problem allows to obtain a technical result expressed in the fact that due to the presence of additional interface units in the microprocessor, it is possible to connect to an unlimited number of system buses and, therefore, conduct exchange operations on them simultaneously, in parallel mode.

где n - количество операндов.In existing microprocessors with the ability to connect to only one system bus, bus exchange operations occur strictly sequentially. For example, when working with a memory unit, in particular, when processing data arrays, a sufficiently large number of operands is possible for each instruction, while the total execution time of the instruction T _{s is the} sum of the sampling time of the instruction T _к , the decryption time of the code T _d , the sampling time of the operands T _i (where i is the operand number), the processing time of the operands T _about . and the time of recording the result T _s

where n is the number of operands.

 Code decryption and operand processing operations occur inside the microprocessor, and since the time to execute them is much less than the time of exchange operations on the system bus, in this case it can be ignored, i.e.

Таким образом, учитывая, что время выполнения операций обмена по системной шине одинаковое, т.е. T_к=T_i=T_з, а количество операндов примем например равным 10 (n=10), то
T_с = T_к+10•T_i+T_з = 12•T_i.

Thus, given that the execution time of exchange operations on the system bus is the same, i.e. T _to = T _i = T _s , and the number of operands is taken to be equal to, for example, 10 (n = 10), then
T _c = T _k + 10 • T _i + T _s = 12 • T _i .

 When using the proposed microprocessor, each memory area in which one of the necessary operands is located is connected to the microprocessor through a separate system bus, which makes it possible to work simultaneously with all operands, i.e.

при этом T_с=T_к+T_i+T_з = 3•T_i, т.е. производительность в данном случае увеличивается пропорционально числу операндов.

in this case T _c = T _k + T _i + T _s = 3 • T _i , i.e. performance in this case increases in proportion to the number of operands.

Up to fifty percent of all instructions are instructions with one operand of type MOV A1, A2 (transfer operation). To execute such a command (comparing single commands) the performance of the existing and proposed microprocessor is the same and equal to T _c = 3 • T _i , but if we consider a sequence of n commands, where n is a number other than one, then for the existing microprocessor the execution time of this sequence ∑T _c is
∑T _c = 3 • n • T _i ,
while the proposed microprocessor, since the instruction is selected on one bus, the operand is selected on the other, and the result is recorded on the third, due to combining the exchange cycles on the system buses of different commands, the execution time of the sequence of commands is
∑T _c = n • T _i + 2 • T _i .
For example, for n = 10, the execution time ∑T _c of an existing microprocessor is
∑T _c = 30 • T _i ,
and the proposed
∑T _c = 12 • T _i .
Figure 1 shows the functional block diagram of the microprocessor, figure 2 is the same when controlled by the upper digits of the address, figure 3 is the same when controlled by the contents of the registers of the system bus number.

 The microprocessor 1 contains a command execution unit 2, consisting of a control device, an operation unit, auxiliary memory and interrupt units (not shown in the diagram), the inputs / outputs of which are connected by internal information lines 3 and control lines 4 to the inputs / outputs of interface units 5 having conclusions (not shown) for connecting to the system buses 6 and resolution inputs connected by permission lines 7 to the resolution outputs of the system bus selection block 8 (made for example as a combinational circuit), inputs / outputs the board and information inputs of which are connected to the control inputs / outputs and information outputs of the command execution unit 2 by the control line 9 and the information highway 10, which, if information about the address passes through it, is also connected to the address inputs of the interface units 5 (see Fig. 2) , and in case of transferring through it the contents of the registers of the register block of the system bus number 11 (see Fig. 3), the information comes from the output of the number of this block, the information input / output and control input of which is connected to the information magic page 12 and line 13 with information input / output and control output of the command execution unit 2.

 This device operates as follows, after initialization, the microprocessor 1 starts to select and execute commands from a fixed system bus starting from a fixed address. The command execution unit 2 supplies information and control signals to the input of the system bus selection unit 8 through the information highway 10 and control line 9, on the basis of which it generates auxiliary control signals, which are sent via line 9 to the input of the command execution unit 2, the system bus number and transmits an enable signal via the corresponding line 7 to the enable input of the corresponding interface unit 5, which, when activated, captures the corresponding system bus 6 (if the microprocessor does not work with it exclusively) mode), having received the address and control signals from the command execution unit 2 at the input via the internal information highway 3 and control line 4, expose them to the system bus 6 and receive information on it, which transmits via the internal information highway 3 simultaneously with the synchronization signal on line 4 to the command execution unit 2, where it is interpreted as a command code on the basis of which the operand addresses of the current command and the address of the next command are generated, as well as information and control signals, which are informational highways 10 and control lines 9 are transmitted to the input of the system bus selection block 8, which on their basis generates the system bus numbers of the operands of the current command and the bus number for selecting the next command and transmits auxiliary control signals to the input of the command execution block 2 and 9 along lines 9 and 7 enable signals to the inputs of the respective blocks 5, activating them. The activated blocks of interface 5 capture the corresponding system buses 6 and, after accepting the addresses and control signals 4 as input to the internal information lines 3 and control lines 4, transmit them to the corresponding system buses 6, then the actions on the selected operands prescribed by the current command are performed, and the received code is decrypted next and the cycle repeats.

 When using the address of the address as information for selecting the system bus, it is transferred from the command execution unit 2 via the information highway 10 to the inputs of the system bus selection unit 8 and interface units 5, while only the oldest part of the address corresponding to the input of the system bus selection unit 8 the system bus number, and the younger part of the interface block inputs, representing the physical address of the call, the further operation of the microprocessor corresponds to the above.

 The source of information about the system bus number can be the registers of the block of registers of the system bus number 11. In this case, the command execution unit 2, in parallel with the formation of the address in it, issues control signals via line 13 to the control input of the block of registers of the system bus number 11, respectively, to which it displays the contents of certain registers of the system bus number included in it, along the information line 10 to the input of the system bus selection block 8, where control signals are sent along the control line 9 the control outputs of the command execution unit 2. The contents of the registers of the register block of the system bus number 11 can be changed and read when the microprocessor 1 executes certain commands, while the command execution unit 2 sends control signals to the input of the register block of the system bus number 11 and accordingly to them on the information highway 12 reads information from a specific register of this block or writes to it. Further, the microprocessor operation process corresponds to the above.

Claims (3)

 1. A microprocessor containing an execution unit and having outputs for connecting to the system bus an interface unit, the inputs / outputs of which are connected by an internal information highway and a control line, characterized in that additional interface units and a system bus selection unit, input / output, are inserted into it the control and information input of which are connected by the control line and the information highway to the control input / output and information output of the command execution unit, and the permission outputs are connected to the inputs of Permissions interface units, whose number equals the number of system buses.  2. The microprocessor according to claim 1, characterized in that the output of the command execution unit is connected by an address line to the inputs of the system bus selection unit and interface units, while only high-order information is supplied to the input of the system bus selection unit, and comes to the inputs of the interface units the rest of the address.  3. The microprocessor according to claim 1, characterized in that a block of system bus number registers is inserted into it, the input / output of which is connected by an information line to the input / output of the command execution unit, and the number output is connected by a line to the input of the number of the system bus selection unit, when This control input is connected to the control output of the command execution unit.

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