CA1091359A - Unidirectional looped busses microprocessor - Google Patents

Abstract

UNIDIRECTIONAL LOOPED BUSSES MICROPROCESSOR ARCHITECTURE
Abstract A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit, a plurality of working registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one or more input/output devices; and a multiplexed cycle steal and interrupt request common poll bus.
The storage and input/output devices communicate with and are controlled by the central processing unit over a looped, or unidirec-tional bus and control channel including a bus in, which is returned as a bus out, a six-bit code bus, and a plurality of control lines.
Bus out is operated to address the executable control store and main storage, and to provide data to the input/output devices and the local storage registers. Bus in is shared by the input/output devices and all storage devices and registers for transferring data and control information to the central processing unit. Bus in is also used by main storage to receive data from the input/output de-vices and from the local storage registers. The six-bit code bus addresses the input/output devices and the local storage registers, thus enabling overlapping of device or local storage data transfers with the accessing of executable control storage and main storage, and with instruction execution.
The arithmetic and logic unit is time shared for data and input/
output processing, register/register and storage/register transfers, shift operations, byte manipulations address modifications, and pro-gram counter incrementing.
Both cycle steal and interrupt requests are received by the central processor on the common poll bus.

Description

1~9:1359 l Cross Reference To Related Application Microprocessor Architecture with Integrated Interrupts and Cycle Steals Prioritized Channel, Canadian Patent Application No. 288,240, filed October 6, 1977, by George Bohoslaw Marenin and commonly assigned herewith.
4. BACKGROUND OF THE INVENTION
4.1 Field of the Invention This invention relates to digital computer memory systems and other data processing systems.
The invention further relates to a unidirectional or looped bus architecture for transmitting data, instructions and other informa-tion between a central processing unit and a plurality of storage and input/output devices.
4.2 Description of the Prior Art State of the art microprocessor designs provide three or four basic and separate functional components. First is the ROS (sometimes RAM) microinstruction address register with its incrementing, branch-ing and linking hardware. Second is the central arithmetic and logic - unit (ALU) with its associated registers and data paths. Third is the addressing and data interconnection with the main storage, that is , .
usually treated as input/output (I/O) unit, and is architecturally combined with other system I/O devices. If the microprocessor is , sophisticated enough, it will also include a fourth separate section of registers and data paths, usually defined as a channel, for per-forming priority nested interrupts switching, and optionally, priority multiplexed or burst mode cycle steal control (sometimes referred to as direct memory access, or DMA.) ; Current microprocessors can be classified into two approaches that divide the above noted functions into a multi-chip set. The first approach allocates different functions to separate chips such as an ALU chip, a control chip, an address chip, an I/O chip, and ROS/RAM (sometimes ~?
~' 1 with address control) storage chips. The second approach distributes processor functions through a number of identical chips: this approach is known as the "bit slice technique,"
and usually requires separate I/O control chips.
Either approach requires extensive chip interconnection, which is limited by the available I/O pins and, consequently results in duplication of logic, and also delays through the ' required off-chip drivers and receivers. If the data or address busses are bidirectional, no signals may be sent or received until an all off and then an all on control state is established between each chip's drivers and receivers; this causes additional delays. Also, each of these bidirectional busses require I/O pins and off chip drivers, resulting in a larger chip layout and, even worse, a higher chip power dissipa-tion. To overcome this drawback, some architectures combine the address and data busses into one time multiplexed "Unibus", compounding further the controls and handshaking delays.
Consequently, a microprocessor architecture which ; minimizes the number of drivers and receivers and which can ~; 20 be packaged on a single chip having about 68 pin connections is needed to optimize cost and performance.
5. SUMMARY OF THE INVENTION
In accordance with this invention there is provided a looped bus architecture for a fully integrated microprocessor which requires sufficiently few input/output line connections so that the microprocessor may be packaged on a single integrated circuit chip. The number of channel drivers required is minimized, yet throughput is maximized by permitt-ing pipelining and overlapped operations.
The invention provides a bus architecture for a computing system including a central processor means having an arithmetic and logic unit, the associated operand registers, and instruc-tion decoding and execution SA9-75-071 _3_ 3sg 1 means and further including local storage registers means, main storage means, executable control store means, and one or more input/output device means.
In accordance with this invention, unidirectional bus means, including a bus in and a bus out, and an auxiliary mini address bus means, are provided for enabling communication between the various storage and input/output means and the central processor means. The bus out is operated to address - the executable control store means and the main storage means, and to provide data to the input/output means and the local - storage register means. The bus in is operated to provide instruction and information to the central processing means, and from the input/output means and the local storage register - means to the main storage means.
In accordance with a further aspect of the invention, timing means are provided to establish an instruction execution cycle period of two parts for permitting overlapped operation.
During one part, the executable control store means is accessed - with the address on the bus out; and during the other part, - 20 the bus out is operated to send data to the local storage ` register or to the input/output devices.
In accordance with a further aspect of the invention, the timing and the decoding and execution means are operated to provide a double cycle period for the execution of an instruc-tion requiring access to the main storage means. During the first cycle, the address to be accessed in main storage is computed, and during the second cycle that address is held on the output bus. Data received on bus in may be loaded into any internal operand register, or passed through the ALU to bus out to be received by an input/output device.
In accordance with a further aspect of the invention, the bus in is operated to transmit data from an input/output device .~` " 1~1359 ;1 or local storage register to the central processor, while ~`the bus out is operated to address the executable storage means for the next instruction to be . ~ .

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" ` 1t~1359 1 executed.
In accordance with a further aspect of the invention, the central processor is controlled to commence execution of a second instruction during a first portion of an instruction ` execution cycle, and then, during a second portion of that execution cycle, data from a first instruction execution is placed on the bus out for transfer to the input/output device and/or the local storage register location addressed by the ` auxiliary address bus.
In accordance with a further aspect of the invention, the local Storage register means is operated to store at a reserved .- . - .
address an image of data appearing on the bus out during each instruction execution cycle for selectively loading onto the bus in during the next execution cycle. In addition, data appearing on the bus out as the result of modifying any internal operand register may be optionally saved in a selected local storage register specified as a third operand during the current instruction. Data is transferred to the main storage means from the central processor means through the local storage register means in one instruction specifying the indirect image register in the local storage register means as the data source.
In accordance with a further aspect of the invention, there is provided in the central processor a first register means for holding the output of the arithmetic and logic unit, and a second register means buffering the output of said first register means onto said output bus means.
In accordance with a further aspect of the invention, the arithmetic and logic unit is operated to execute a second instruction with respect to data received on said input bus, while the results of the execution of a first instruction are being held on the output bus.

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1 Brief Description of the Drawings Figure 1 illustrate the manner in which Figures la, lb, and lc are related; Figures la, lb, and lc show a logic diagram of the micro-computer architecture of the invention.
Figures 2a, 2b, 3a, 3b, 3c, 4a, 4b and 4c are timing diagrams illustrating the execution of a basic instruction set adaptable to the microcomputing system architecture of the invention. Figures 2, 3, and 4 illustrate the relationship between these timing diagrams.
Figure 5 is a more detailed logic diagram illustrating the inte-- 10 grated cycle steal and interrupt prioritized channel.
Description of the Preferred Embodiments Referring now to the drawings, particularly FIG. 1, the architec-ture of the computing system of the invention will be described. The four major physical units of the system shown in FIG. 1 are the --~ following:
1. Central processing unit (CPU) 9, including the arithmetic and ~ Logical Unit 22, a channel (including Bus In 10, Bus Out 20, ;~ Address Bus 21, Common Poll Bus 53, and Control Lines 15,) :, - a plurality of working registers, and control logic.

2. Local Storage Registers 14.

3. Main Storage 12.
~ 4. Read Only Storage (ROS) 16, sometimes referred to as Execu-- table Storage 16 or Microprogram Store 16.
. CPU 13 may be implemented, for example, as a single LSI chip, `i mounted in today's technology into a package requiring less than 70 module I/O pins. This CPU package may be mounted, in currently avail-';
able technology, on a card together with one Read Only Store 16 module, one Local Store 14 module (having, say, 32 registers), two modules for support drivers 18, and an oscillator (shown by output line 59.) A
; 30 small portion of Main Storage 12 may also be mounted on this card.
However, it is expected that, utilizing currently available circuit technology9 Main Storage 12 would be mounted for the most part on a - second card.

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~, l Data, Instructions, and Input/Output (I/O) commands are transferred 2 between CPU 9 and other units by way of two unidirectional busses, I/O
3 Common Bus In 10, and I/O Common Bus Out 20. I/O Common Bus In 10

4 receives data from the input/output devices (not shown), Main Storage 12 over Bus ll, Read Only Storage 16 over Bus 17 and Local Storage Register 6 14 over Bus 13. Data on Bus la is fed to Program Register 30 and directly 7 to Arithmetic and Logic Unit 22. It is particularly important to note 8 that data and information on bus 10 is fed in one direction with respect 9 to CPU chip 9, no drivers being provided for transferring data off of CPU chip 9 along Bus In 10. Main Storage 12, Local Storage Register 14, ll and Read Only Storage 16 have the drivers provided or sufficient power lZ to place data on I/O Common Bus 10. In addition, Main Storage 12 has 13 the facility to take data off of bus 10 pla^ed thereon by Local Storage 14 Register 14 or any input/output device over bus 13. Bus Out 20 presents the contents of Output Buffer Register 26 to Read Only Storage 16, Main 16 Storage 12, Local Storage Register 14, and the I/O devices (not shown.) 17 For Read Only Storage 16 and Main Storage 12, Common Bus Out 20 serves 18 the function of an address bus, while for Local Storage Registers 14 and 19 the I/O devices, Bus Out 20 is used as a data bus. I/O devices are addressed by a set of 6 Local storage Code Out (LCO) lines 21, which, in 21 this embodiment, permit direct addressing of up to 64 Local Storage ~ 22 Registers 14 or 63 I/O devices. As previously mentioned, Bus In 10 :''.
23 brings micro-instructions or data from the Input/Out devices or storage.
24 Source or destination of Bus Out 20 and Bus In 10 transfers are selected by control lines 1;, which after 'eing driven by driver 18 appear as 26 control and clock lines 19. These lines include Local Storage Register 27 select, Read Only Storage select, Main Storage select, Write high byte 28 and Write low byte. An I/O device is selected 'vy the combination of a 29 valid device address and Local Storage Register select not being active.
30 Validation of Bus Out 20 data transfers is timed by preceeding clock one 10~L359 :`

1 pulses (one of lines 15). Sample Out signals indicate that LCO and 2 select codes are valid. Sample In is a response to Sample Out to validate 3 bus in data transfers to the microprocessor 13 or command responses from 4 the devices. These signals together with Hold Clock In, which a~lows Input/Output devices to inhibit the CPU clock advance, permit totally 6 asyncronous I/O operation.
7 Following is a list of the input/output interface lines 19, 20, 21, 8 10, and 31, including a brief note as to their function.

9 Bus Out 20 provides, herein, 18 lines for I/O device and Local - 10 Storage Register 14 data out, Main Storage 12 address out, and Read Only 11 Storage 16 address out.
12 Bus In 10 provides, herein, 18 lines for micro-instruction Erom 13 Read Only Storage 16, data in from the I/O devices and Local Storage L4 Registers 14, and Main Storage 12 data in and data out. Poll Bus In 53 provides 7 multiplex cycle steal or 7 interrupt level request linPs, to 16 be further explained hereinafter. Poll cycle steal out 77 is one of lines 17 19 and is used for requesting cycle steal poll on Poll Bus In 53, in 18 place of interrupts, by clearing poll bus in 53 interrup~ priorities, 19 and requesting cycle steal priorities. LSR Code Out (I,CO) Line 21 provides, herein, 6 lines for addressing the up to 64 locations in Local 21 Storage Register 14, for signaling the cycle steal level, or for addressing 22 Up to 63 input/ output devices.
23 LSR Select Out includes 5 of control and clock lines 19, including 24 LSR Select, Storage Select, ROS Select, write high byte, and write low 25 byte. (If no high or low write specified, then a read operation is 26 implied.) `: 27 Sample Out is one of lines 19 for indicating.that a command or LSR
28 Code Out signals are valid which will be the case during clocks 3-4 and 29 9-14, as will be described more fully hereinafter. Sample In (not shown) includes one common line for a selected device to respond to .' 1~ 59 -1 Sample Out, validating data which it has placed on Bus In 10, or responding 2 to a command.
3 Any Cycle Steal In line 68 is used by an I/O device on the signal rise 4 to request a cycle steal poll, and on the signal fall to indicate. that its priority is valid on Poll Bus In 53.
6 Any Interrupt In line 70 indicates that one or more devices 7 have an interrupt pending on Poll Bus In 53, with the priorities indicated 8 on Poll Bus 53. Oscillator In line 59 provides a continuous square wave ; 9 clock signal.
Reset In (not shown) provides a system reset and power on reset 11 input.
12 Clock 1 or 9 Out is one of lines 19 for continuous timing validating 13 previous Output Buffer Register 28 data on Bus Out 20. Clock 6, 7 Out, - 14 or Clock 14, 15 Out (for double cycle instructions), is one of lines 19 providing a continuous timing, which falls to indicate an instruction 16 ending.
17 Inhibit Storage High Byte is originated by the device to write only 18 the low byte in Main Storage 12. Inhibit Storage Low Byte is originated 19 by the device to write only the high byte in Main Storage 12. If the device raises both Inhibit Storage High and Low, then a Main Storage 21 read operation is implied.
22 Storage data select allows Main Storage 12 data to appear on Bus In 23 10. By inhibiting Storage Data Select, a device can provide its data (which may be the Main Storage Address) on Bus In to be written into Local Storage Register (cycle steal address register.) 26 Control LSR Write is originated by the device to chain data tables 27 in Main Storage or to prevent incrementing the Local Storage Register 14 28 address.
29 Local Storage Register Code Out lines 21 addresses 0-63, together with LSR Select Line 19, Addresses Local Storage Register 14 locations B

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` l~}g~359 1 0-63. Locations 16-23 are used for interrupts, and locations 24-31 for 2 cycle steals. LC0 21 addresses 1-63 without LSR Select Line 19, address - 3 I/0 devices 1-63, with address 0 reserved for channel functions.

4 Referring now to Central Processing Unit 9, I/O Col~mon Bus In 10 is fed to Alu 22 and Program Register 30. The output of Program Regis~er -6 30 is fed along lines 33 to ALU 22 and to instruction decoder 62. The `- 7 address portion of an instruction stored in the P register is also fed 8 along line 31 to LSR Control Ou~ Register 40 and to Decrement Register 9 38. The output of Decrement Register 38 is fed along line 39 back to P

register 30 and Current Condition Register 48 and Count Register 50.
11 The output of Count Register 50 is fed along line 51 to Decrement Register 12 38 and LSR Code Out Register 40. The output of Current Condition Register ~, . . .
13 48 is fed along line 49 to the preserved Condition Code Register 42.

14 The outputs of both Current Condition Register 48 and Count Register 50 are also fed along line 43 to ALU 22. The data flow of CPU 19 includes 16 16 bit ALU 22 and the following operand registers:

17 Accumulator Register 34, which can be gated along line 35 to either 18 side of ALU 22.

19 Accumulator Extension Register 36, which can be gated to either side of ALU 22 along line 37.

21 Total register 24 is the output buffer for ALU 22 and is loaded by 22 Bus 23. Program Register 30, as previously noted, holds the micro-23 instruction for decoding at Decoder 62 and execution. The contents of 24 Program Register 30 can also be gated into ALU 22, this along Bus 33.

Microinstruction Address Register 32 may have its contents gated to ALU

26 22 along line 29 for address modification or branch and link operations.

27 Count Register 50 is used for shift counting and for the indirect addressing 28 of Local Store Register 14. Its contents can be gated to ALU 22 along 29 line 43 for performance of various operations to be described hereinafter.

Output Buffer 26 holds data presented on Bus Out 28, which after being lR
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lO~ S9 1 driven at drivers 18 appears as I/O Common Bus Out 20.
Specific instructions to be described later save the contents of Output Buffer 26 in Local Storage Register 14 position zero which can then be inputed to ALU 22 along Bus In 10 for various operations. The output of Total Register 24 appears on Bus 25 and is gated under control of instruction decoder 62 to load Microinstruction Address Register 32, Accumulator Register 34, Extension Register 36, Error Register 46, Interrupt Mask Register 44, Count Register 50, Current Condition Register 48, and Output Buffer Register 26.
The output of Interrupt Mask Register 44 is fed along lines 45 and 43 to ALU 22 and along line 45 to interrupt gate 52.
The output of Error Register 46 is fed along lines 47 and 43 to ALU 22. In addition, the output of Total Register 24, the four lower bits, may be gated along line 27 to the higher order four bits of Instruction Address Register 32.
Multiplexed cycle steal and interrupt requests Common Poll Bus 53 is fed to interrupt gate 52 and priority encoder 54, the latter for cycle steals which have priority over interrupts. The output of interrupt gate 52 is fed along lines 69 to priority encoder 54. The output of priority -encoder 54 is fed along lines 55 to Current Interrupt Level Register 56, to higher level interrupt test circuit 58, and to LSR Control Out Register 40. The output of higher level interrupt test circuit 58 appears on line 63 as the force higher level interrupt signal. The output of Current Interrupt Level Register 56 is fed along lines 57 to higher level Interrupt Test circuit 58 and to LSR Control Out Register 40.
- Clocking signals on line 59 from a single phase oscilla-tor are fed to four phase generator 60, the output of which is fed along line 61 to clock 66 and auxiliary clock 64 the outputs of which are used in connection with instruction lq~ S9 1 decoder 62 to control the operation of CPU 9, including the ~> gating of the buses to the various operand registers and controlling SA9-75-071 -lla-10~359 .

1 the time sharing of the various buses and registers.
2 Referring now to Pigure 5 a more detailed description will be given 3 of the cycle steal and interrupt channel of the invention. Where possible, 4 the same reference numbers as for elements in Figure 1 are used. In this figure, by way of example, a more detailed description is given of - 6 the various controls and latches for implementing the integrated cycle 7 steal and interrupt prioritized channel. As will be apparent to those y skilled in the art, similar and more detailed descriptions of the controls ~ -9 could be provided for the remainder of the system architectures set 10 forth in Figure 1. However, such is not essential to the understanding -~
11 of the invention which relates more specifically to the architecture, `
12 the detailed controls are readily within the skill of those practicing 13 in the art and can be provided without undue experimentation from the 14 description of the architecture and of the timing diagrams provided. In Figure 5, Poll Interrupt/Cycle Steal lines 530-536 represent the individual 16 lines in Common Poll Bus 53 of Figure 1, in negative logic. Mask 44 has 17 as it's outputs lines 450-456. Poll Cycle Steal Only Latch 75 includes 18 as an output Reset line 80. In Interrupt Gate 52, line 450 (pertaining 19 to the zero bit of Mask Register 44) is ANDED with Poll Cycle Steal Only Latch Reset line 80 and the result Nor'd with line 530, representing the 21 zero bit position of Poll Bus 53; the result appears on line 520. In 22 similar fashion, bits 1-6 of Mask Register 44 on lines 451-456 are ANDED
23 with Poll Cycle Steal Only Latch Reset line 80 and the results Nor'd 24 with bit positions 1-6 of Poll Bus 53 on lines 531-536, with the results :~ 25 on lines 521-526. Line 520 is fed to NOR circuits 86, 94, and 95. Line 26 521 is fed to NOR circuits 86, 90, and 95. Line 522 is fed to NOR
27 circuit 86 and AND circuit 91. Line 523 is fed to NOR circuits 86 and 28 90. Line 524 is fed to AND circuits 86 and 92. Line 525 is fed to AND
29 circuit 88 and NOR circuit 90. Line 526 is fed to AND circuit 93. The output of NOR circuit 86 appears as -4 Priority line 544 and is fed to .

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_~ _ ` ~0~359 1 AND gates 87, 88, and 92, to Current Interrupt Code 56 (position 4), to Greater Test 48, and to AND gate 82. The output of NOR circuit 95 appears on -2 Priority line 542 and is fed to AND gate 91, to Current Interrupt Code circuit 56 (position 2), to Compare Greater ~; Test circuit 58, and to AND gate 82. The output of NOR circuit 90 is fed to AND gate 93. In NOR circuit 95, the output of AND gates 87 and 88 are NOR'd with lines 520 and 521. In NOR circuit 94, the outputs of AND gates 91-93 are NOR'd with line 520, and appear on line 541, which is fed to Current Interrupt Code Circuit 56 (posi-` tion l), Compare Greater Test Circuit 58, and to AND gate 82.
- Minus Any Cycle Steal Request ~ine 68 is inverted and fed to set Poll Cycle Steal Only latch 75. The set output of Poll Cycle Steal Only latch 75 is fed along lines 77 to set Cycle Steal Acknowl-edge latch 76. The reset output of Poll Cycle Steal Only latch 75 is fed along line 80 to inhibit the AND gates in Gate 52 and to degate , Switch Interrupt levels Latch 84, the output of which appears on lines 79 and is used to control Load New Interrupt Level line 72 and set Current Interrupt Level line 57. Negative Any Interrupt Request line 70 is fed to Cycle Steal Acknowledge latch 76 and inverted to ` 20 Switch Interrupt Levels latch 84. Positive logic Enable Interrupt - line 71 is fed to Switch Interrupt Levels latch 84. Minus Any Cycle Steal Request line 68 is also fed to Cycle Steal Acknowledge latch 76. The set output of Cycle Steal Acknowledge latch 76 appears as Cycle Steal Acknowledge line 55, which is ANDed at 89 with a clock pulse on line 85. Line 78 from AND 89 is fed to AND gate 82 and to the high order input bit lines 834, 835 to force into those lines a predetermined code.
Lines 310-314 represent the low order bit positions of the address portion of Program Register 30, shown as lines 31 of Figure 1. Lines 310-314 are fed through AND gates 83, where each one is individually ANDed with Set Microinstruction control line 74 to appear as output lines 831-B
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19~59 1 835, respectively, and thence to LSR Code Out Address Register 40.
The outputs of AND gates 82 are dot OR'd to lines 831-833, the low order bit positions at the input of LCO Register 40. In addition, the output lines from AND gates 81 are also dot OR'd to the low order lines 831-833 into LCO Register 40. The outputs of Current Interrupt Code Register 56, appearing on lines 561, 562, and 564 are individually ANDed in AND 81 with Set Current Interrupt Level line 73, and also fed to Compare Greater Test circuit 58. Set Current Interrupt Level line 73, which gates the Current Interrupt Code Register 56 contents to the three low order input lines of LCO

Register 40 also forces the high order input lines 834, 835, in a man-ner similar to that of line 78, except to a different code, so as to place on lines 41 at the output of LCO Register 40 an address to a different Local Storage Register 14 location.
Cycle steals have priority over interrupts and Any Cycle Steal Request 68 instantly cancels the normally continuous interrupt poll-ing by setting the Poll Cycle Steal Only latch 75 requesting all devices to place their cycle steal priorities on Poll Bus 53 lines 530-536 and withdraw their interrupt requests. The disappearance of Any Interrupt Request line 70 signals microprocessor 9 that all ~` devices have removed their interrupt priority bits on Poll Bus 53, and the disappearance of Any Cycle Steal Request 68 together with Poll Cycle Steal Only latch 75, guarantees Cycle Steal Priority 54 output lines 541, 542, 544 are ready to be set into LCO Address ; Register 40 together with cycle steal modifier bits formed by lines 1 78 in high order positions 834-835, and signals Cycle Steal Acknowl-edge 55 to the I/O devices. The cycle steal LSR in LSR 14 being addressed by lines 41 provides the indirect Main Storage address on Bus 13 that also may be incremented through ALU 22 to either fetch or store data from the device. The lowest priority cycle steal level requires no priority bit and its forced device Address part will . : ~

1 be zero to allow all binary device addresses. Early in thecycle steal cycle, Poll Cycle Steal Only latch 75 is reset to revert to the continuous interrupt polling or sequential micro-instruction execution; or the Poll Cycle Steal latch 75 may be set again, because it must be first reset to allow the devices to set Any Cycle Steal Request 68 again, if sequential burst mode cycle steals are required. Interrupt Mast Register 44 is always degated when Poll Cycle Steal Only latch 75 is set. Asynchronous device cycle steal requests can be con-trolled by microprocessor clock gating or by latching thepoll bus so that the priority circuitry can be stabilized.
Having described the overall architecture of the system of the invention, a more detailed explanation of the char-acteristics of the various components, their operation and interaction will be given.
Input/Output Unidirectional Bus Organization The internal ALU closed loop connection of the external input and output unidirectional busses provided by this invention allows internal processing and external I/O data modification, interrupt level switching and cycle steal address incrementing functions for sophisticated multiple level interrupts and cycle steals to share the existing ALU
and data path with minimum control logic hardware and without any additional buffering registers.
This is accomplished by employing a unidirectional bus that goes in and out of CPU chip 9. Data and address are mixed on the same output bus. I/O Common Bus In 10 is the only data input bus to CPU chip 9. Main Storage 12 attaches to this bus, as does Local Store 14. While conserving the unidirectional function of Bus In 10 with respect to CPU 9, Main Store 12 uses Input Bus 10 for reading or writing data, while Output Bus 20 holds the Main Store 12 address.

., 1~53L359 1 Input Bus 10 also acts as an external input to one side . of Arithmetic Logic Unit (ALU) 22, the output from which is set in temporary hold .~ .
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1 Total Register 24. Total Register 24 has one common Output Bus 25 that goes to every operand register inside CPU chip 9. Bus 25 is connected to Output Buffer Register 26, and from there comes out from CPU chip 9 to form I/O Common Bus Out 20, which in this example is a two byte bus. Output Bus 20 supplies data to Local Store Register 14 and also to a number of I/O devices (not shown). On a .~ time shared basis, Bus 20 is also the address bus for Read Only Storage 16 (or whatever writable control store may be attached, in which the instructions to be executed are stored.) Bus 20 is also the address bus for Main Storage 12. The invention thus provides a unidirectional looped busses architecture which is hybrid in nature, containing a mixture of data and address on Bus Out 20 and data and i~
instructions on Bus In 10.
The absence of a direct processor chip data path to Main Stor-age 12 is solved by optional processor set result images in LSR 14 and the usage of the unidirectional input bus in the reverse direc-tion with respect to Main Storage 12 from LSR 14. Thus, Input Bus 10 is kept unidirectional with respect to processor chip 9 by allowing Output Bus 20 on every internal data modification micro-instruction to optionally set the result in the selected LSR 14 without any additional instruction or time. This innovation allows pipelining and concurrent operations on both busses, permitting Bus Out Register 26 to access the next microinstruction out of ROS 16, while the previous microinstruction is being executed with data on Input Bus 10 in overlapped mode. Similarly, Bus Out Register 26 is used to access Main Storage 12 directly and between these two addressing modes, a narrow data window transfers data to LSR 14 or I/O devices addressed by a separate six (6) bit mini address bus 21, which also signals the respective cycle steal acknowledges or switches interrupt levels. By reserving one of the 64 LSRs as a bus Out image register, the processor chip internal data flow can . be arranged around a common Arithmetic and Logic Unit (ALU), with total Register 24 feeding all the 1~91359 :, 1 other internal data and addressing registers and the outside world through Bus Out Register 26, which also remains preserved for program 3 use as a fourth operand in the LSR 14 image buffer. In this manner any ".- . .
4 outside I/O device may share ALU 22 with internal processing.
The external unidirectional looped busses also permit total processor 6 chip internal transparency for interrupt level switching and direct 7 memory channel accessing (cycle stealing) with automatic storage address 8 incrementing through the common ALU and data path.
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9 The looped bus architecture of thé system permits instruction execution overlapping and pipelining, examples of which will next be 11 described, 12 In the first example, pipelining occurs whenever ROS instructions 13 are on Bus In 10, which is usually at the end and the beginning of each 14 microinstruction cycle, when at the same time I/O common Bus Out 20 starts sending data to an I/O device.
16 In a second example, an overlapped operation occurs when data is 17 coming in on Bus In 10 from I/O devices or from Local Store 14, and is 18 being processed internally through ALU 22. At that time, I/0 Bus Out 20 19 contains the ROS 16 address, so the next sequential instruction is being accessed.
21 A third example, of overlapping, is when data from execution of a 22 previous instruction`is still to be stored in LSR 14, and execution of a 23 new instruction has already commenced. LSR 14 will be loaded during 24 clock 1 of the new instruction cycle while the new instruction execution started at clock 0. The six lines of LSR Code Out (LCO) Register 40 26 form an auxiliary address bus 21, 41 that is used to address 64 half 27 words of Local Store Register 14, or up to 63 I/O devices on I/O common 28 Bus Out 20, depending on what type of an instruction is being executed.
29 The combination of this auxiliary mini address bus and the looped In/Out Bus 10, 20 allow operations to be done in one cycle. An I/O device can . .

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1 place data on Bus In 10, have that data processed through ALU 22, and see the arithmetically or logically modified data on Bus Out 20 during the same instruction, while the device is being addressed by Mini Bus 21. This is an advantage over prior art channels which require 3 instructions to do even a simple I/O data transfer without an ALU operation, as follows: First, the processor would have to send an address out on one common I/O bus. Then the device would have to respond through a demand/response interface to signal that it has recognized its own address. A second instruction would be needed for the processor to send out a command specifica-tion which would be responded to by the device. Having completed that, the processor would have to then perform a third instruction, read or write depending on which direction the data is to flow.
The I/O Common Bus Out 20, is multiplexed so that for every instruction that is executed, an overlapped operation occurs. Overlapped means that the next instruction from Instruction Store 16 is accessed, while at the same time, the processor is executing internally the current instruction.
This is accomplished over the common busses by allowing, say five clock periods of the eight clocks instruction cycle for ; addressing ROS 16, and the other 3/8 of the instruction cycle for sending data, either to Local Store Register 14 or to the I/O devices.
Main Storage 12 Main Storage 12 provides addressable and updateable memory for storing data by both the microcomputer and the I/O
devices for subsequent retrieval. Data is transferred in both the read and write mode over bus 11, with respect to I/O Common Bus In 10. Lines 19 provide clocking and controls, and the address is provided by I/O Common Bus Out 20.

Whenever access is made to Main Store 12, an additional cycle is added, to make the instruction a double cycle instruc-tion. As will be described hereinafter, during the first . cycle an increment, decrement, or other address modification is done on the Main Store 12 address ,.

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1 pointer obtained from LSR 14 or B Register 35. (This gives .
the ability of a stacked operation even though a stacked pointer is not used, as an automatic increment/decrement system for addressing equates to the same power as stacking pointers.) The Main Storage read or write is performed during the second cycle, after the Main Store 12 address pointer has been up-dated to obtain the effective new address. The address is held in Output Buffer 26 for the whole second cycle, herein-after referred to as the main storage memory cycle, providing a 8 clocks to address Main Storage 12.
~- Main Storage 12 is operated in a pipelining mode, as follows: During a main storage fetch operation, data is obtained from Main Storage 12 on Bus In 10 and loaded into one of the internal registers in Microcomputer 9. At the end of the fetch operation, at clock 0, when the next instruction is about to begin, the data that has been fetched on Bus In 10 from the Main Storage 12 is gated through ALU 22 and set i in Total Register 24 and thence transferred to Output Buffer Register 26. The setting of that data in Buffer 26 destroys the current Main Storage address.
Read Only Storage (ROS) 16 Sometimes referred to as executable control store means, ROS 16 stores the executable instructions comprising the micro-computer control program. These instructions are loaded onto Bus In 10, buffered in Program Register 30, and decoded at Instruction Decoder 62--which, together with the timing ; circuits, controls the gates, registers, and operating circuits to execute the various instructions, in a manner explained -~ more fully hereinafter in connection with Figures 2-4.
ROS 16 is operated in a pipelining environment. Thus, at clock 0, which is usually the beginning of each micro-instruction, the instruction is set to Program Register 30 :: ' 1 from Bus In 10. At the same time, clock 0, data is set into the Output Buffer Register 26.

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SA9-75-071 -19a-; .

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1 Thus, data from Executable Storage 16 addressed on Bus Out 20 is taken from Bus In 10, while at the same time the address on Bus Out 20 is destroyed. Because of the inherent delays in the circuitry ~including the drivers and logic stages,) pipelining occurs with these operations taking place, simultaneously.
Local Storage Register 14 Local Storage Register ~LSR) 14 comprises a plurality of addressable and modifiable register locations. Data is written into LSR 14 from Bus Out 20 and read out onto Bus In 10, as addressed by LCO lines 21. Data placed on Bus In 10 may be directed to Main Storage 12 or to CPU Chip 9.
;Location 0 in LSR 14 is reserved for saving Buffer 26 data, under conditions to be described hereinafter.
Arithmetic Logic Unit 22 -;Arithmetic and Logic Unit (ALU) 22 is shared on a time multiplexed basis for processing data, microinstruction address incrementing, displacement branching, subroutine linking, main storage addressing, address modification, data fetching or storing, priority nested interrupt processing, and cycle stealing.
This is accomplished by integrating Address Register 32 with the ALU 22 data flow, and by the use of LSR 14. Address Register 32 (a simple non-incrementing polarity-hold register) time shares ALU 22 on alternating half-cycles to increment or otherwise modify the ROS 16 instruction address. Plus or minus displacement branching and linking is facilitated by this single data path into ALU 22. Since ALU 22 outputs to ;Output Bus 20, micro-addresses may be stored in LSR 14 as return ; 30 pointers from interrupts. By the same token, since LSRs 14 gate onto Input Bus 10 and through ALU 22 to Address Register 32, new interrupt routine pointers can be loaded or previously 1~9~359 , .
1 interrupted routine pointers restored, allowing a priority ` nested and expandable interrupt structure to be included within the basic ALU 22 data flow. One LSR 14 location :, .

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SA9-75-071 -20a-1 (location 0) is reserved to save and restore the Output Bus Regis-ter 26 contents.
Microprocessor 9 fetches data from Main Storage 12 through In-put Bus 10 and ALU 22 for storing in its internal operand registers while Output Bus Register 26 holds the Main Storage 12 address from the selected LSR 14 or operand register (such as ~xtension Register 36) for simultaneous accessing and updating. Microprocessor 9 data to be stored in Main Storage 12 as the result of execution of a pre-vious microinstruction is first sent to a selected LSR 14 register through Output Bus Register 26. The write MS microinstruction gates the LSR 14 data onto Input Bus 10 to enter Main Storage 12.
In addition, certain LSR 14 locations can also act as indirect - Main Storage 12 addresses for direct I/O Device cycle steal operations, one LSR 14 register being assigned to each priority level. The I/O
Devices include their own data length counter. The MS 12 address regis-ters in LSRs 14 are automatically incremented through ALU 22 on the way to Bus Out 20, to address MS 12 for writing therein the I/O data on Input Bus 10, or for reading out MS 12 data, which by way of Input Bus 10 passes through ALU 22 to be made available to the I/O devices on Bus Out 20. The I/O devices receive microprocessor 9 data on Bus ; Out 20 and send data to microprocessor 9 on Bus In 10.
~ Shared ALU 22 is used in decoding emulated instructions. The op-: eration code of the instruction being emulated is added by ALU 22 to i the current instruction address in Address Register 32 to obtain adisplacement pointer to a table in ROS 16 just below the current in-struction being executed. In this manner, a 256 way branch is ob-tained to the ROS 16 instructions for executing the emulated instruction.
By sharing of Instruction Address Register 32, interrupt switching is accomplished through the same data path that exists for basic in-struction execution. The instruction address value which is in Address Register 32 is stored in Local Storage Register 14 through ALU 22, Total Register ~ B`

1 24, Internal Bus 25, Output Buffer 26, and Bus Out 20. Thus, when an :~ 2 interrupt occurs, the pointer to the next instruction that would have3 been executed on the current program priority level is preserved in LSR
4 14. Next, the highest level that is to be executed is determined by . . .
using the priority code which is developed in Priority Encoder 54 to 6 generate an address at LCO Register 40. LCO Register 40 addresses the 7 Local Storage Register 14 location that contains the pointer for the ROS
8 16 subroutine for that interrupt level. That pointer is read from Local - 9 Store Register 14 over I/O common bus 10 and into microcomputer chip 9 through ALU 22 to be set in Total Register 24 before being stored in 11 Address Register 32 and Output Buffer Register 26 to address in ROS 16 12 the subroutine for the interrupt level that is to be executed. When the 13 interrupt has been serviced, the current interrupt subroutine pointer is 14 stored in LSR 14, and the address pointer for the interrupted program is ' 15 fetched therefrom.
-~ 16 Program Register 17 Program Register 30 is a buffer for the current instruction and 18 holds the instruction operation (Op) code that is being executed by 19 microcomputer chip 13.
The count or address field of instructions stored of Program Register ; 21 30 may be gated directly to Decrement Register 38 and to LCO Register 22 40.
23 Total Register (T) - 24 Total Register 24 is set with the output of ALU 22, and loads Bus ~ 25 25, at least twice during each instruction execution cycle--once with,~; .
26 the addresc of the next instruction to be executed, and once with the 27 ALU results upon execution of the instruction specified function.
28 As data from Arithmetic Logic Unit 22 is .emporarily held in Total 29 Register 24 and then is buffered in Output Buffer 26, one function can be performed on Bus In 10, while at the same time another function is ~;~

` ' 16~9~3S9 :' 1 being finished on Bus Out 20. This two stage buffering in the 2 loop permits overlapped operations and pipelining.
3 Instruction Address Register 4 Instruction Address Register 32 is modified during execution of each instruction by ALU 22 to derive the address in ROS 16 of the next ` 6 instruction to be executed.
7 Accumulator Re&ister and Extension Re~ister 8 The two working registers are Accumulator Register 34 and Extension g Register 36. Herein, these registers ~are each 16 bits, giving the capability of 32 bits for instructions that use shifting, such as shift 11 arithmetically, shift logically left or right, shift left and count or 12 rotate left or right.
13 These registers, together with Count Register 50 and Output Register 14 26 are the internal registers, and are directly addressable by the microinstructions to perform internal arithmetic and logical computations.
16 They can also be modified with one of the external Local Store Registers 17 14, or vice versa, with the result stdred in one of the internal registers ; 18 or in Local Store Register 14.
19 Output Buffer Register Output Buffer Register 26 performs a dual function. Being an ALU
21 22 operand register it holds data that the microprogram directs to it.
22 Also, an interrupt that forces the transfer of address pointers or any 23 Direct Memory Access (DMA) cycle steal accesses, have to allow both the 24 address and the data to flow through Output Buffer register 26. So that Buffer Register 26 does not loose data placed there by the microprogram 26 Local Storage Register 14 location 0 is reserved as an image for Output 27 Buffer 26 whenever the microcomputer changes instructions addresses and 28 data, whether under interrupt control or during a cycle steal operation.
29 Subsequently, the Buffer 26 value stored in LSR 14 location 0 as an ALU
22 operand value can be recalled. In this manner, no back-up is required .-~

l on microcomputer chip 9 for Buffer Register 26.
Power Drivers As Bus 28 leaves chip 9, it flows through power drivers 18, the output of which is Bus Out 20. In a Large Scale Integration (LSI) chip, each driver can only drive one load.
Therefore, as Bus Out 20 is a common bus going to a number of units (or loads), it has to be repowered. (In doing this repowering, an expansion on the number of channel lines developed is accomplished by coding the existing lines for an up or down level during different clocks periods of each : microinstruction cycle of eight clocks.) ,.
Decrement Register Decrement Register 38 is used for counting in all shift, ,:
multiply, divide instructions and in the decrement, test and branch instructions. Decrement Register 38 has inputs from Program Register 30 whenever a shift operation calls for a direct shift of up to 32 positions and stores the decremented ` value in Program Register 30. In indirect shifts, where Count Register 50 becomes the shift count value, the same decrement ; 20 by one is used as in direct shifts and Decrement Register 38 ~-holds the decremented value before it is returned to Count i Register 50.
Since the maximum shift operation that is performed in this implementation is 32, a five bit Decrement Register 38 is sufficient. However, for doing field length operation, Count Register 50 is also used as a field length count. For - this operation it requires a full 8 bit decrement function.
This is accomplished by cycling the 5 bit Decrement Register 38 twice, taking a four bits character from Count Register 50 first, decrementing it and storing the carry into the high - order 5th position. The stored carry, if there is a carry, together with the high order 4 bit character from Count 1~9~L3S9 1 Register 50 are decremented to form the full 8 bit decremented ~- value for loading back into Count Register 50.
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SA9-75-071 -24a--, .: . , ... , .. ~

16)~ 3S9 1 LSR Code Out (LCO) Register .
LSR Code Out (LCO) Register 40 addresses the I/O device or the LSR Register 14 location with respect to which data is to be transferred.
Current Condition Register The upper four bits of Current Condition Register 48 hold the four condition codes, and the lower four bits hold four - programmable flags; these bits form the non-connected high byte of Count Register 50. On every arithmetic operation, the four conditions codes are set, for subsequent field linked operations. The four conditions are binary carry;
twos complement overflow; twos complement minus; and the non-zero indicator-which is cumulative. The non-zero indicator, once set in any field length, will remain set until changed by ` a microinstruction.
Count Register The secondary ALU operand register is Count Register 50.
Additionally, it may serve as a shift counter. The shifting count originally stored in Count Register 50 is decremented for each shift of Accumulator Register 34, or of Extension Register 36, individually, or of both, when connected together for a double precision shift operation. In a shift left and count instruction, as soon as the high order bit is found, shifting is terminated and the value remaining in Count Register 50 indicates how far the shift has progressed.
Therefore, in many operations that value becomes an indirect address pointer to ROS 16 or LSR 14. Thus, Count Register 50 can be loaded from internal Bus 25, and can be modified through ALU 22 with the result loaded in LCO Register 40 for addressing Local Storage 14 on Bus 21 or Input/Output devices on Bus Out 20.
For indexing address computations and for calculating effective addresses, Count Register 50 is used as a positive 1 or negative displacement that is combined with data by ALU
22. The result is stored in Local Storage Register 14, or in any internal register on chip 9.
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1 Preserved Condition Code and Current Condition Code Registers The output of Current Condition Register 48 is selec-tively buffered in Preserved Condition Code Register 42. The basic condition codes, set as a result of ALU operations, are:
` overflow, carry-borrow, cumulative not zero, minus. The current condition codes reflect the result of the most recent arithmetic microinstruction execution. All shift-left high-order bits shift into the current carry indicator. On shift left and count, the high-order bit may set the current carry indicator. Loads, stores, moves, logicals, increments, decrements, jumps and branches do not change the condition codes. Codes in registers 42 and 48 can be separately cleared, and can be individually tested by Jump instructions. In addition to these condition codes, there are four program controlled flag bits, which in combination with the current condition codes form Condition Register 48. When a micro-instruction is being emulated, the correct current microlevel code is transferred to the Preserved Condition Code Register 42 to preserve the microIevel condition code of the language being emulated at the microlevel.
Interrupt Register Interrupt Mask Register 44 contains the current mask status of the interrupt levels allowed. Interrupt Register 44 can also be modified through ALU 22, stored away in LSR 14, or restored therefrom.
- Error Register The low order bits of Mask Register 44 comprise the one byte Error Register 46, which controls and logs errors.
Examples of machine check errors which can be logged are:
a parity error on an instruction being fetched from ROS 16;
a data error from Local Store Register 14; a Main Storage 12 ;

1 parity error detected by a parity check on Bus In 10; a S parity error on data being received from any one of the Input/Output devices; a channel hung condition, where an ; Input/Output device does not ,' ' ~
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- SA9-75-071 -26a-. .

1 "handshake" nor allow the microcomputer to proceed to the next microinstruction; or time out errors, such as occur when an - I/O instruction is issued to an Input/Output device that does `` not exist and the address, therefore, is non-detectable.
~ These errors can be set in Error Register 46 and modified, !.~ ' saved, tested, or stored in LSR 14. Any one of these errors .~ .
being set automatically by the hardware forces the highest : (level 7) interrupt in the microcomputer to go to a subroutine that can either retry the operation or terminate the current function and provide signal to the operator's console.

4 Phase Generator and Clocks 60, 64, 66 A Single phase oscillator 59 is the input to four phase generator 60 that runs two clocks: Basic clock 66 and Auxil-iary shifting and timeout clock 64. Basic clock 66 is a 2 phase clock that can be stopped every second clock position, ; with eight clock decode positions provided out of 4 overlapp- -ing latched states. Basic clock 66 runs through the eight positions every microinstruction cycle. Basic clock 66 also :i-provides a high latch position that is used whenever the micro-instruction being executed requires a double cycle, which takes place whenever Main Storage 12 is accessed; then clock 66 runs through the same eight positions, except this time the presence of the high position flipflop codes the clock 66 output as clocks 8 through 15. Auxiliary clock 64 decode provides four distinguishable time slots together with a high position flipflop which is used whenver the clock goes . ~
, through a repeat cycle to indicate the maximum timeout of 2 runs through the clock, which is equivalent to one whole instruction execution cycle. Auxiliary clock 64 is used whenever a shift, multiply, or divide operation is required.

During these instructions main Clock 66 is stopped at its 7th position. This permits cycle steals to proceed in the 1~ 3S9 1 middle of shift, multiply, or divide extended operations.
Auxiliary clock 64 is also used for timeouts when I/O
devices are not responding or for handshake operations SA9-75-071 -27a-,, .
`:
l whenever an I/O device is found to be on Bus lO and is trying to inter-2 change data. If the timeout exceeds the time allocated, then Auxiliary 3 clock 64 times out and sets indicators in Error Register 46 to initiate 4 the highest level, or machine check, interrupt.
Integrated Cycle Steal and Interrupt Prioritiz~d Channel 6 Referring to Figure 5 in conaection with Figure 1, the cycle steal 7 and interrupt functions are accomplished by Common Poll Bus 53, which 8 provides for 8 cycle steal levels or 7 interrupt request levels.
g Herein, Poll Bus 53 is 7 bits wide to contain the requests for 7 inter-rupt levels above the current executable program level, a total of 8 11 interrupt levels. Any I/O device can be attached to any of the 7 prioritized 12 interrupt request lines. Polling for interrupts is continuous, except 13 when Poll CS Only Latch 75 is set, and the cycle steal function takes 14 placè. As soon as an I/O device requires service from microcomputer 9, it places its request on the ass gned priority bit 530-536 of Poll Bus 16 53. Multiplicity of requests will go through Priority Encode logic 54 17 where the highest level request is encoded into a 3 bit code (on ]ines ~i 18 541, 542, 544) specifying one of the 8 different priority levels. The - l9 priority of interrupts is also controlled by Interrupt Mask Rcgister 44.
If Mask 44 is set to allow the interrupt, then the AND circuits in 21 intarrupt gate 52 allow that interrupt to pass on to Priority Encoder 54 22 50 as to set the code of the currently requesting priority. This 23 interrupt priority is compared in comparator 58 to the current level 24 stored in 3 bit Current Interrupt Level Register 56. Current Level 56 is continuously compared with any new level from Priority Encoder 54 to ?6 see whether thc new code is higher than the current one. If it is, 27 then, the next instruction in the current chain will not be executed.
28 Instead the current address pointer in Instruction Address Register 32 29 is transferred to the Local Store Register 14 location for the current level. The ..ew, or higher, level pointer is then brought out from the . .

B
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1 Local SeOre Register 14 and put into Instruction Address Register 32.
2 The address for the interrupt routine in Local Storage Register 14 3 (one oE the 8 possible interrupt pointers,) is derived as follows: the 4 low order 3 bits (on lines 561, 562, 564) from Current Interrupt ~egister 56 are transferred under control of Gate 81 onto LCO Register 40 input 6 lines 831, 832, 833. Set Current-Interrupt Level 73 loads the high 7 order lines 834, 835, with the remaining bits of the LCO 40 address for 8 storing the interrupted pointer in LSR 14. The new pointer to the g interrupt registers in LSR 14 is similarly loaded into LCO 40 on the high order input lines 834, 835 by Set Current Interrupt Level 73 and on 11 the low order lines 831 833 into LCO 40 from Interrupt Register 56 after ~ -12 Load New Interrupt Level 72 has transferred the new Priority 54 into 13 Current Interrupt Register 56. This changes the new LCO 40 address to that for the LSR 14 location containing a pointer to the ROS 16 subroutine for executing the interrupt for the selected level, with the address 16 pointer arriving on Bus Out 20 and at Instruction Address Register 32 from ; 17 Local Store Register 14 through AL~ 22 and Total Register 24. At the 18 end of execution of the subroutine of the new interrupt level, a-Branch 19 Out instruction is issued. This instruction restores the pointer of the originally interrupted program. Since the subroutine that serviced the 21 interrupt also resets the interrupt, the request for the same interrupt 22 should not be present. If another interrupt comes up on the same level 23 or a higher level, the program will not return to the original program 24 position, but will continue on to handle the newer interrupt priority request. This provides for a full nesting of up to 8 interrupt levels.
26 In addition, for each level, there can exist a multiplicity of sublevels.
27 Once a given interrupt level is detected, an InteFrupt Level Status Word 28 (ILSW) instruction is issued to all I/O devices, and one of the 16 29 devices, currently requesting service on any particular interrupt level, must identify itself. (In this manner 16 sublevels can be obtained for 1~91359 l each one of the 8 levels for a total 128 sublevel interrupts.) The Interrupt Level Status Word that is received into one of the Microcomputer registers can be used to determine which of the 16 devices on that level is requesting service. This is done by one Shift Left and Count instruction. The first bit in the highest order position will stop the Shift Left and Count instruction and the remaining count in Count Register 50 will indicate the position of the subroutine for that par-- ticular device.
Common Poll Bus 53 is also used for cycle stealing.
However, it first has to be cleared of all interrupt requests.
Any Cycle Steal Request line 68 is set to a negative logic ~,; level by a device that is requesting a cycle steal. Once that line sets Poll Cycle Steal only latch 75, immediately Poll Cycle Steal Request line 77 is brought up, the devices r~` are required thereby to remove their interrupt requests from Poll Bus 53 until the cycle steal function has been concluded.
As soon as common Interrupt Request line 70 and Any Cycle Steal Request line 68 are dropped by all the devices, CS
Acknowledge latch 76 is set at the next clock 0, indicating that Poll Bus 53 contains the cycle steal priority for the requesting device, which goes directly into the Priority Encoder 54 (bypassing Interrupt Mask gate 52.) This produces 3 bits of an LCO Priority address out of Priority Encoder 54, which is gated at AND 82 by AND 89 line 78 (the clocked ~- output of Latch 76) into LCO register 40--together with the fixed higher order bits addressing pointers in LSR 14 for the cycle steal level which is used as a Main Storage 12 address, to either obtain or store data into Main Storage 12 under full control of the I/O Device-even to the extent of just setting the upper or lower byte (instead of the two ; bytes in the halfword mode.) Current Interrupt Level Register 56 in this mode stays undisturbed because the interrupt . level (whether it is the program level or any higher level being executed) is just delayed by that one cycle steal : instruction breakin. As just described, a memory access is initially addressed by a ~;

SA9-75-071 -30a-r ~ .

' l pointer from LCO register 40, including three low order bits signifying 2 which of the 8 cycle steal levels is currently acknowledged, and the 3 high order bits giving a displacement to the local store 14 halfword 4 register holding the indirect memory address. This address reads out from Local Store 14 onto Bus In lO, and is incremented through ALU 22 before being set into Buffer Register 26. During Main Storage 12 memory 7 access time, the incremented address on Bus Out 20 can be written back 8 updated into its Local Storage Register 14 cycle steal register or - 9 prevented to be written by the acknowlédged I/O device so as to preserve the cycle steal address unchanged. After an access time, data is read 11 out from memory 12 on Bus In 10 if the I/O device allows the readout 12 selection of Main Storage 12 and inhibiting the write pulses which are 13 control pulses 19 out of the microcomputer. The I/O device can 14 place its own data on Bus In 10 to be written into Main Storage 12.
Thus the device has full control of the increment or non-increment 16 function through the integrated ALU and full control of the read or 17 write mode of the operation. In write mode, once that operation has 18 been completed the Input/Output device can still see its own data on Bus l9 Out 20 during the following clock 1. In read mode~ the data read out on Bus In 10 flows through ALU 22 into Total Register 24 and Output Buffer 21 26 to be available to all of the devices on Bus Out 20. The only I/O
; 22 device that will pick up that data in the read mode is the device that 23 will recognize the cycle steal level code on the six LCO address lines 24 21. The processor then reverts back to its normal instruction execution or to the interrupt routine handling that had been suspended for this 26 one DMA (or cycle steal) cycle.
27 Description of Timings 28 Referring now to Figures 2-4, a brief description will be given of 29 the timings for executing the microinstructions. As all instructions have similar execution timing characteristics, a general description is ,~ .

1 first given, and will be followed by a more detailed descrip-tion of each instruction type.
The clocking cycle is divided into eight different times known as clocks 0 through 7. Clocks 8 through 15 are repeats of clocks 0 through 7, and the only time that these clocks appear is during a Main Storage 12 operation, including DMA. The basic instruction time of eight clocks is divided into two parts for utilization of ALU 22. During clock 7 through clock 2, ALU 22 is devoted to incrementing or other-wise modifying instruction Address Register 32. Clocks 3through 6 are utilized for processing by all the micro-- instructions. In this manner, ALU 22 is used continuously --., .
on a 50% basis for instruction execution and 50% for instruc-' tion pointer update. The basic window during which the address for ROS 16 appears on Bus Out 20 starts at clock 3 when the computed new address pointer is loaded from ALU 22 into Total Register 24 and transferred to the Output Buffer Register 26. This address stays unchanged until the following clock zero when Buffer Register 26 is changed to contain the ' 20 data for either Local Storage Register 14 or any I/O device on I/O common Bus Out 20.
Clock 0 starts every microinstruction by loading the instruction from Read Only Storage 16 into Program Register 30. This buffering in Program Register 30 permits execution ` of that instruction while the ROS 16 address is changed at `!' clock 3, as described previously, to access the next micro--~ instruction.
Total Register 24 is set at clock 2 with the instruction address and at clock 6 with the data processed by ALU 22 in executing the instruction. During clock 3, the next instruction address is set into Buffer 26 for loading on Bus Out 20.

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1'~359 1 If the microinstruction requires that data be written into Local Storage Registers 14, it is written during clock 1 of the instruction following which that data was computed, and it is written from Output .'' ~.

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lV~s~359 1 Buffer 26 through Drivers 18 directly into the Local Storage 14 location selected by the six LCO 40 lines. In the same manner data can be transferred to an I/O device by loading it into Output Buffer 26 at clock 0 and with a signal 19 during clock 1 indicating that the data on Bus Out 20 is valid. This data changes at the beginning of clock 3 when the Read only Storage 16 address appears in Output Buffer Register 26. Any data that is coming into CPU 9 on Bus In 10 for storing or modification has to arrive and be valid at ALU 22 during clocks 3, 4, 5 and 6--this being the time during which the ALU performs the process specified by the instruction being executed. For the same reason data from LSR 14 is placed on Bus In 10 for processing by CPU 9 at clock 2. At clock 3, which allows for signal delay, the data is available for the ALU function.
Data from Local Storage Registers 14 is placed on Bus In 10 starting at clock 2. It is not gated into ALU 22 until the beginning of clock 3, because from clocks 7 through 2 ALU
22 is used for updating Instruction Address Register 32.
At the beginning of clock 7, ALU 22 is transferred back to - the address incrementing function, having completed its basic microinstruction processing function.
Referring to Figure 2, for microinstructions dealing with the Main Storage 12, particularly fetching data from Main Storage 12 into one of the registers of CPU 9, the second cycle (clocks 8-15) has a slight variation in that the next microinstruction is fetched from ROS 16 during clock 8 even though execution of the current instruction continues through clock 15 and into the following clock 0, at which time data from Main Storage 12 is finally set into the specified reg-ister of CPU 9 or sent to an I/O Device. In this case (following every instruction accessing Main Storage 12) 1 a new instruction is not gated into Program Register 30 on the following clock 0 as it has already been trapped at the previous clock 8 of the Main Storage 12 instruction. Also, the window for updating Instruction Address Register 32 is shortened and does not start in '. ' ..
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SA9-75-071 -33a-~ .

1 equivalent clock 15, but two clocks later at clock 1 and only lasts through clock 1 and clock 2, as that update is just a direct transfer through ALU 22 without any modifica-tion (as that has already taken place during clocks 7-10 of the previous Main Storage instruction.) The Main Storage write instruction writes the data into Main Storage 12 during the second phase of the instruction ` during clocks 13 through 15.
Referring to Figure 3, for decimal arithmetic, during the first four clocks, ALU 22 performs the binary equivalent function and stores the intermediate carries for each of the packed decimal digits. A repeat ALU 22 pass is then taken for another four clocks (controlled by auxiliary clock 64) for "six" correct to obtain the pure decimal result.
Referring to Figure 4, whenever a branch is performed, where the branch address is loaded at clock 7 (such as the branch-on-condition, a multiway table branch in decoding an Op-code from a target language which is being emulated, or when a branch and link is returned by restoring the original address from Local Storage Register 14 into Instruction Address Register 32) then an additional four clock cycles of Auxiliary Clock 64 are added to allow time for ROS 16 access-ing, since in each of these cases a branch has changed the precomputed look ahead address from the previous instruction.
In shift operations, Auxiliary Clock 64 takes two clocks for each single bit shift in either Accumulator Register 34 or Extension Register 36; or, it takes 4 clock periods (which is half as much as the basic microinstruction execution time) for shifting one position of the double precision Accumulator and Extension Registers 34 and 36: these are logically connected together as one double precision register by alternatively cycling through ALU 22.
SA9-75-071 ~34-1~9~359 , ...
~: 1 For jump operations the basic ALU 22 processing time (clocks 3 through 6) perform the test for equals, greater, or test under mask; the ~.

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SA9-75-071 -34a-1~3~)~3S9 ` 1 result of the test is not known until the beginning of clock 7, and at that time a jump decision is made. If no jump is to ; take place then the next instruction that has been accessed continues without any delay. If a jump condition is met and one instruction is to be skipped, the basic microcomputer clock takes another dummy microinstruction cycle during which it increments for the next microinstruction without executing the microinstruction jumped.
The branch unconditional is a very fast instruction because no conditions need to be tested, therefor no auxiliary clock delays are present. Furthermore, the 12 bit branch address is directly passed through ALU 22 and loaded into Total Register 24 at clock 2. From Total Register 24 it passes to Instruction Address Register 32 and Buffer Register 26 at clock 3, thus synchronizing with the normal look ahead accessing of instructions.
Instruction Set The basic machine instructions are optimally designed for emulation, and are stored in ROS 16. Often called micro-instructions, they may be referred to simply as instructionsin the following discussions, except perhaps when a distinc-tion between the emulated target machine instructions and the microprocessor instructions is to be emphasized.
- Common to all instructions are a parity bit in the most significant bit position (bit 0) and a 3-bit operation code (bits 1-3). The remaining bits are subdivided into fields of varying lengths, the nature and function of which depends ~' on the type of instruction. Since there are only eight , distinct operation codes, some of the instruction types are distinguished by decoding additional modifier bits. Most of the instructions are highly encoded and specify or imply a large variety of distinct operations, many of which are 1 performed sequentially. These sequential operations are coordinated by a very tightly designed set of timing patterns as set forth in Figures 2-4.
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SA9-75-071 -35a-1~1359 . .

1. Referring now to Figures 2-4, the 11 basic instruction categories 2. will be described. The symbols used in the timing charts to refer to 3. the registers are as follows:
4.Symbol Registers

5. A Accumulator

6. B Extension

7. T Total

8. P Program

9. U Instruction Address

10. N Count (Shift Count) ll. M Output Buffer (Bus~Out) 12. I/O Input/Output Device 13. E Error .
14. I Interrupt Mask 15. C Current Condition Code 16. PCC Preserved Condition Code 17. L Local Storage Register 18. Each of the instructions may be defined by a 16 bit, including l 19. parity bit, instruction code. Bits 1-3 define the operation code, and ., 20. these codes are listed below together with the instruction category;
, Operation 21. InstructionsM~emonic Code - 22. Control CO 000 23. Logical Wri.e LW 001 24. Logical Shift LS 001 25. Logical Move Count LM 001 ; 26. Modify Data MD 010 27. Modify OperandMO 010 28. Fetch Storage FS 011 29. Immediate Modify IM 100 30. Jump Conditional JC 101 31. Branch Conditional BC 110 32. Branch Unconditional BU lll :

~9~359 1 Control Instructions Referring to Figure 3C, the timing diagram for the control instructions is set forth. Control instructions may be provided, for example, for the following operation: for transferring data, for indirect execution, for setting the interrupt mask, for setting paging, for table branching, for optional mode ` selections, for operation on preserved condition code and current condition code, for program flags and for I/O transfers.
By way of introduction, a number of uses of the control instruc-tions will be described.
A number of the control instructions relate to interrupt processing. One such instruction enables an interrupt to take place after the completion of every microinstruction, while another provides for an interrupt window during which any pending interrupts will be honored and the interrupt switch made. After that, the interrupts are disabled until the window is encountered again.
Other control instructions relate to ROS I/O paging.
The four bit ROS 16 page is an internal page specified within Instruction Address Register 32. This page register is used whenever direct branching across the 4K boundaries of directly addressable ROS 16 instructions locations is required. ALU 22 will increment past the 4K boundaries all the way through 64K
halfwords of ROS 16. Also, the interrupt switching pointers provide full 16 bit addressing, and not merely 12 bits.
Therefore, it is also capable of addressing full 64K comple-ments of instructions.
other control instructions control the four flag bits.
They are the lower four bits of C Register 48, that together with the four condition codes form the nonconnected upper byte of Count Register 50. The flag bits can be set by the program-mer for different indications and can be used as switches in - SA9-75-071 _37_ 1~9~3S9 1 the subroutine. The flag bits can be stored or restored together with the condition codes and the lower byte Count ~' i :!~

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SA9-75-071 -37a-s9 1 Register 50 into and out of LSR 14 on interrupt switching.
The remaining control instructions deal with the condition code. There are two levels of condition codes, each having four bits indicating binary carry, twos complement overflow, two complement high order minus bit, and cummulative non-;~ zero. The Current Condition Code Register 48 upper four bits change on every arithmetic operation as well as on a shift left logical, shift left and count, multiply, and divide. For other instructions of the logical nature, the registers them-selves can be tested for zero or non-zero, ones or mixed ones and zeros. The Preserved Condition Code Register 42 stores the same four bits as Current Conditions Code 48, except it ; is under microprogram control for transferring and accumulat-; ing the equivalent of condition codes of the macro language being emulated.
b~ By way of example, the following control operations are ` used in the embodiment of the microcomputer system of the - invention.
Control operation load immediate data (KBUS) operates to load the data field of the instruction into the Output Buffer 26 high order bit positions. Local Storage Registers 14 register 0 data bits 0-4 are loaded into the low order bit positions of Buffer Register 26, and the contents of Buffer Register 26 are written into Local Storage Registers 14 register 0.
Control Operation Transfer LSR Data to I/O Device (KLSR) provides a four bit field for addressing Local Storage Register 14 registers 0-15. Data from the addressed Local Storage Register 14 is transferred to Output Buffer 26 and onto Bus Out 20. A six bit field of the KLSR instruction provides a device address, which is loaded into LCO register 40 for addressing Input/Output devices 1-63.

: 1 Control instruction Transfer Immediate Data to I/O Device . (KLCO) loads part of Output Buffer Register 26 with immediate . data from the instruction code, with the remainder loaded . from selected Local Storage ~ .

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SA9-75-071 -38a-.:
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1 Register 14 register 0 bits. Data in other bit positions of - the instruction code are loaded to LCO Register 40 for the - device address. The contents of Output Buffer Register 26 are loaded into Local Storage Register 14 register 0.
- Control operations Set Interrupt Mask (KILM) provides the interrupt mask bits for Register 44, with a one in a bit position enabling an interrupt for the corresponding level.
One bit in the instruction code specifies whether to save -or set the interrupt mask bits.
Control operations are provided for setting paging of Read Only Storage 16. KLAP has a field for specifying pages 0-15, and KRAP specifies page 16. Each page represents 4,096 half words.
Control operations for table branching specify the register or register portion to be added or Exclusive OR'd to Instruc-tion Address Register 32 to yield the next sequential address in ROS 16 for execution. These are set forth below:

1~ 359 .

Mnemonic Add to IAR 32 2 KIAL Accumulator Register 34 low byte 3 KIXL Extension Register 36 low byte 4 KIBL Output Register 26 low byte KIEL Bus In 10 low byte 6 KIAH Accumulator Register 34 low hex 7 KIXH Extension Register 36 low hex 8 KIBH Output Register 26 low hex 9 KIEH Bus In 10 low'hex KIAZ . Accumulator Register 34 low zone

11 KIXZ Extension Register 36 low zone

12 KIBZ Output Register 26 low zone ~ 13 KIEZ Bus In 10 low zone - 14 KIAS Accumulator Register 34 low six bits KIXS Extension Register 36 low six bits : 16 KIBS Output Register 26 low six bits.
KIES External Bus In 10 low six bits 18 Control operations branch out (KILB), transfers the current Instruction 19 Address Register 32 contents to the Local Storage Register 14 register : 20 for the current interrupt, resets the current interrupt, samples for a 21 new interrupt, and transfers to Instruction Address Register 32 the 22 contents of the Local Storage Register 14 location for the new interrupt 23 level.
24 Control operation KSIE provides three 2 bit fields (II, EE, and SS) 25 for specifyin~ the interrupt code (enabling an interrupt or sampling the : . 26 interrupt and then disabling ~urther interrupts,) specifying error mode, 27 and specifying Main Storage 12 byte address (no change; reset, or set 28 byte mode.) 29 Code 01 in one or more of each of the interrupt code (II), error ; 30 mode (EE), and Main Storage byte address (SS) Eields of the KSIE control .~ .

SA975071 -~0-.. .. .

` lt`~359 . .

~` 1 operation are reserved to specify additional control operations, in 2 which the interrupt code, error mode, or main storage byte address mode 3 characteristics of the KSIE control instruction are preserved or replaced as set forth in the table below. If the control code shows II, EE, or SS, then the KSIE control instruction defines the operations specified 6 by the interrupt code, error mode, or main storage byte address byte 7 mode, respectively:
8 Mnemonic Instruction Code Field Description g KPIE IIEE01 ~ Reset preserved condition code (not overflow) 11 KPSI IIOlSS Reset preserved condition - 12 code (all)

13 KCSE 01EESS OR current condition

14 code to preserved condition code and - 16 reset current condition 17 code.
18 KTPI II0101 Reset current condition ` 19 code and preserved condition code (not 21 overflow) 22 KCPS 0101SS Transfer current 23 condition code to 24 preserved condition code and reset current . 26 condition code - 27 KCPE OlEEOl .Transfer current condition 28 code to preserved 29 condition code (except , 30 OR overflow) and reset current condition code.

.~ SA975071 -41-, . .
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. 1 Control operation KNTC performs the function for KTPI. In addition, 2 controls are set to perform a KCSE following the next. inStruCtiQnS if it is 3 an arithmetic operation. Flag 4 is also reset "even" or set "odd" on the 4 result.
Control instruction KPCC performs a direct transfer of the preserved 6 condition code to the current condition code.
7 Control instruction KFCC specifies whether Current Condition Code 8 Register 48 ~s to be saved or set, and specifies the positions to be saved - g or set: carry-borrow, overflow, minus, cumulative, not zero, or flags l through 4.
ll Main Storage Instructions 12 The Logical Write (LW) and Fetch Storage (FS) instructions comprise 13 the mai~ storage instruction grouping. With these instructions, described 14 in Figure 2B, data can be read from Main Storage 12 and placed into the : 15 four basic internal data registers: Accumulator Register 34, Extension ; 16 Register 36, Count Register 50, and Output Buffer Register 26.
17 Data that is fetched from Main Storage 12 is addressed by Extension 18 Register 36, or by one of the Local Storage Registers 14, as specified l9 in the instruction address. The address can be initially updated with an increment or a decrement to provide a continuously moving pointer to 21 Main Storage 12 on Common I/0 Bus Out 20, or it can be oscillated at an 22 effective address by adding to a specified pointer the N Register block 23 50 displacement (positive or negative.) 24 The halfword or byte addresslng mode can be specified for the storage instructions. The IBM*1130 addresses its main storage data in a 26 halfword mode. The IBM*360/370 and the IBM~System/3 use the byte addressing 27 mode, even so, it may fetch one or two bytes in a,ny one access. Since 28 the architecture of the System/3 instruction set allows the instructions 29 to be either 3, 4, 5, or 6 bytes, the instructions themselves are not aligned on the halfword boundaries. Therefore for ease of emulation, *Registered Trade Mark of International Business Machines Corporation ~ .

1~ 3S9 l the microcomputer of this invention provides halfword alignments by byte. 2 twisting the data from Main Storage 12 in ALU 22 so as to align any 3 specific byte in one position, such as, for example, the instruction 4 oper.:~ion code to always appear in the low order byte.
Logical Write Instruction .~ .
6 As previously noted, there is no direct path for data from CPU 9 to 7 Main Storage 12. This is because Bus Out 20 is used as the Main Storage 8 address bus and therefore is not available for data. Bus In 10 is ; g bidirectional only with respect to Main Storage 12. The reason for no~
`lO permitting it to be bidirectional with respect to CPU chip 9 is to ll conserve area on CPU chip 9, since the output drivers required to place 12 data onto Bus 10 would use up a large amount of area and power on chip 13 13, and consequently, are not included.
14 The four Logical Write instructions select halfword, low byte, or

15 high byte modes; and store in Main Storage 12 data taken from an Addressed ~-

16 Local Storage Register 14 location or from an I/0 device.

17 Logical Wri~e from LSR
, 18 In the first Logical Write instruction, data from Local Storage l9 Register 14 location l is written into the Main Storage 12 location ~; 20 addressed by one of Local Storage Register 14 positions 0-63. An LSR 14 21 register 1-63 i~ selected and the contents incremented or decremented by 22 one, or left unchanged, before setting Output Buffer Register 26 to .` 23 address Main Storage, with the updated address being rewritten into the 24 above slected Storage Register 14 location 1-63. Specification of Local Storage Register 14 location 0 as the address source selects Count 26 Register 50 as the indirect address of the Local Storage 14 register to 27 be used as the source for the address for Main Stprage 12. A storage ` 28 write cycle is performed with the data obtained from Local Storage 29 Register 14 position 1 that has been switched on to Bus In 10. As an option, the address modification code (two bits of the op code), if set , .

10~359 1 to 10 will select low byte or high byte only to be written into Main 2 Storage 12. If a Control Instruction has previously set byte storage 3 addressing mode, all plus or minus address updates will function as plus 4 or minus 2 and the high byte selection will force a -1 address update (low byte does not modify the address) with the resulting address, even 6 or odd storing the high or low byte, respectively. Also, the original 7 Output Buffer Register 26 contents will be selected from Local Storage 8 Register 14 location 0.
g Logical Write from LSR 0-63 Addr ssed by Extension Register 36 ; 10 The second instruction is similar to the first one, except that the 11 data to be written into M2in Storage 12 is obtained from a selected 12 Local Storage Register 14 (position 0-63) and the Storage Address for 13 ~ain Storage 12 is obtained from Extension Register 36. The low or high 14 byte operations described above are also available.
Logical Write from I/O_Device 0-63 Addressed by same LSR 0-63 16 The third instruction is similar to the first logical write instruction 17 described, except that the same LSR 14 (0-63) code that selects the

18 address register also selects the I/0 device (0-63), to provide the data

19 on Bus In 10 to be written into Main Storage 12.
Logical Write from I/0 Device 1-63 addressed by Extension Register 36 21 Ihe fourth instruction is similar to the second Logical Write 22 Instruction, described above, except that the data to be written into 23 Main Storage 12 is provided by the selected I~0 device (1-63) on Bus In 24 10.
Fetch Storage ':` 26 The Fetch Storage (FS) instructions are designated for halfword 27 mode. For setting storage byte addressing in place of halfword addressing, 28 see the Control instructions. (Current Condition 48 + Count 5C or 29 Interrupt Mask 44 + Error 46 are always used together in byte mode and the upper byte ls not zeroed on a Fetch Storage Command.) 10~L359 .

1 Load from Storage to CPU 9_~ isters with LSR 14 Address (Halfword 2 Address Mode):
3 An LSR 14 register (1-63) is selected and the contents modified by 4 0, ~ 1 or OR 1 before setting Output Buffer 26 (not LSR 14 location 0) Register to Address Main Storage 12. If modification was ~1 the Output 6 Buffer Register 26 contents are updated into the selected register in .: .
7 LSR 14. A storage read cycle is now performed and Storage 12 data out 8 is switch onto Bus In 10 to be set into the Accumulator 34, Extension 9 36, Buffer 26, or Count 50/Error 46 operand registers selectively.
Interrupt 44 + Error 46 registers may be selected by KSIE Control 11 Instruction in place of Condition 48 + Count 50 registers. (Count 12 50/Error 46 register has only the low byte.) LSR 14 location 0 selects 13 indirect addressing of LSR 14 from operand Count Register 50 low-order 14 6 bits. Also, the original Output Buffer 26 data will be selected from , 15 LSR 14 location 0.
16 With_BUS Operand Address (Halfword Address Mode):
-~ 17 This instruction is similar to the next instruction described 18 except that Output Buffer (meaning LSR 14 location 0) Register 26 is 19 used in place of Extension 36 Addressing Register and the auxiliary Bus Out 20 address transfer acts as a halfword move of Buffer 26 to LSR 14 '. 21 locations 1-63 or the Bus Out 20 address update into LSR 14 location 0.
22 With XTN Operand Address (Halfword Address Mode):
23 Extension Register 36 contents are modified by 0, ll, or by adding 24 the Count 50 operand displacement before setting the Output Buffer 26 (not LSR 0) Register to address Main Storage 12. Th~ Buffer Register 26 26 updated value is rewritten into Extension Register 36. A read Main 27 Storage 12 cycle is started. An auxiliary transfer is performed (before ~ . .
28 the Main Storage 12 data is available) provided that LSR 14 selection is 29 from 1 eo 63, not zero. Optionally, the Address Register 32 contents , 30 are written into the selected LSR 14 reglster. Finally, the Main Storage .

1~ 359 1 12 data is switched onto Bus In 10 to be set into Accumulator 14, Extension 2 36, Output Buffer 26, or Count 50/Error 46 operand registers, selectively, 3 as in the first FS instruction. Also, the original Output Buffer 26 4 data will be selected from LSR 14 location 0.
Load from Storage to I/O Devices (~alfword Address Mode):
6 This instruction is similar to the one above except that Address 7 Register 32 can be selected from Extension Register 36 or the LSR 14 8 location equal to the Input/Output device selected and updated. The g Main Storage 12 data is set into Buffer Register 26 (not LSR 0), from where it is sent to the selected Input/Output device (1-63) with a 11 Sample Out pulse, and no auxiliary transfers take place. Device O
12 selects indirect addressing of the device from the operand Count Register 13 50 low-order 6 bits. Also, the original Buffer 26 data will be selected 14 from LSR 14 location 0.
Arithmetic and Logical Instructions ~ 16 Referring to Figure 3 the arithmetic and logical instructions are -- 17 modify data (MD) and modify operand (MO). The arithmetic include add 18 with or without carry, and substract. They can be performed in binary 19 twos complement or decimal packed (unsigned one-digit in every hex 4 ; 20 bits of data.) The arithmetic functions can be performed within the - -21 microcomputer between the internal registers (Accumulator Register 34, . .
22 ~xtension Register 36, Count Register 50, and Output Buffer Register 23 26.) In addition, Accumulator Register 34 or Extension Register 36 can 24 be arithmetically combined with one of the 64 Local Store Registers 14 with the result stored either in one of Local Store Registers 14 or in 26 Extension Register 36. All the arithmetic instructions performed within 27 microcomputer 9 registers can be performed in halfword mode, upper byte 28 alone mode, lower byte mode, or low order 4 hex bits mode. The other 29 bits in each of these configurations remains unchanged.

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1 The logical instructions include AND, OR, and Exclusive-OR. These - -~- 2 operations, when performed on the internal registers alone, as in the 3 arithmetic mode, can be performed in the hex low four bits, the low 4 byte, the high byte, or the halfword mode. Similar functions can also be performed with Local Store Register 14, except all these external-to-` 6 internal or internal-to-external logical functions can only be carried ` 7 out in the halfword mode.
8 Modify_Data g By the Modify Data command Accumulator Register 34 or Extension Register 36 can be modified in place with the contents of a Local Storage 11 Register 14 that remains unchanged. Also, a specified Local Storage 12 Register 14 can be modified with the contents of Extension Register 36, 13 with the Extension Register 36 remaining unchanged and the result set 14 in the selected Local Storage Register 14. In addition, any Input/Output ' 15 device can be selected to supply data on Bus In 10. This data can be 16 modified with the data in Extension Register 36 and the result returned ~ 17 to the same Input/Output device by setting data into Output Register 26 i~ 18 (not LSR 0, and thence to Bus Out 20 and also into Local Storage Register 19 14 position 0. If the address portion of the modified data instruction is set at 0, 0 data is produced on Bus In 10. By using the OR function, 21 a move is made from Extension Register 36 to Output Register 26. By 22 using the AND function, Output Register 26 is set to all zeros.
23 The modifying functions that can be specified by the Modify Data 24 instruction are: add binary with or without carry or decimal packed with carry, subtract binary or decimal packed with borrow (subtraction 26 cannot be from a selected Local Storage Register 14 or InputJoutput 27 device, except in reverse), AND, OR, and Exclusive OR. Specifing Local 28 Storage Register 14, position 0 selects indirect addressing of the Local 29 Storage Register 14 or Input/Output device from the low order 6 bits of Count Register 50.
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10~359 :`' 1 Modify Operand With the Modify Operand (MO) instructions, Accumulator Register 34 can be modified in place with Extension Register 36, or Extension Register 36 can be modified in place with Accumulator Register 34, that ~ remain unchanged. Also, Accumulator Register 34 or Extension Register : 36 can be modified in place with Count 50/error 46 Register. Also, Extension Register 36 can be modified in place with Output Buffer Register 26. With Extension Register 36 zero, an OR function in place with LSR 14 location 0 (Output Buffer Register 26) produces an Output Buffer Register 26 move to Extension Register 36 and also to LSR 14 (position 1-15).
The modify functions are the same as in the Modify Data (MD) instructions except that Move functions between any combination of Accumulator 34, Extension 36, or Count 50 and Error 46 operand regis-ters are added, and subtraction cannot be from Count 50/Error 46 operand registers except in reverse. In addition, all the above func-tions can be performed in either halfword, high byte only, low byte only or low hex digit only, except that the high byte of Count 50/

; Error 46 operand register does not exist. After each of the above functions are completed, an auxiliary halfword result (high byte of Count 50/Error 46 = Current Condition 48/Interrupt Mask 44) move can be performed to a selected LSR 14 location 1-15.
Logical Shift Referring to Figure 4, Shift operations can be executed either left or right, one bit at a time. The length of the shift depends on the length of the register. Accumulator Register 34 and Exten-sion Register 36 each can be shifted from one to sixteen positions.
For multiply and divide, when double precision is required, Accumu-lator Register 34 becomes the high order register of Extension Regis-ter 36, and together they form a coupled 32 bit register that can be shifted from 1 to 32 positions in any of the following modes: shift right arithmetic, shift left and count, shift left logical, shift ' : B

93~359 right logical, shift left and rotate, and shift right and rotate.Faster operations which are equivalent to a rotate of the 16 bit registers eight positions, otherwise known as ., ~ .

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~ SA9-75-071 -48A-~ ~1 byee twists, can be performed in one microinstruction cycle.
2 Immediate ~odify 3 The Immediate Modify (IM) instructions are illustrated in Figure 4 3C.
A byte of data from Program Register 30 (op bits 8-15) is combined 6 with the low order byte of Accumulator Register 34, Extension 36, or 7 Count 50/Error 46, selected by a previous KSIE Control instruction. For 8 the Accumulator 34 or Extension 36 operand registers, combining functions g are Subtract, Load, OR, AND, XOR, ADD.- Any carry or borrow generated by ADD or Subtract is propagated into the high-order byte. For the Count 11 ;O/Error 46 register, combining functions are OR, AND, LOAD, ADD. For 12 Add or Subtract functions the immediate byte data is incremented or 13 decremented by one, and any incoming carries will be ignored with a new - 14 condition code set.

Jump Conditional 16 Referring to Figure 4B, the Jump instruction is performed whenever 17 a test is false. The tests, performed against a mask byte in the instruction 18 on the low order 8 bits of a selected register, are as follows: mask 19 equals the low byte, mask is greater than the low byte, mask bits are tested for on bits in the low byte and the remaining non-selected bits 21 are ignored, or mask is tested for the OFF bits in the low byte and the 22 remaining bits are ignored. Condition Register 48 can be tested under 23 mask with ON/OFF bits selection and a jump on any combination of conditions.

24 Condition Register 48 has 4 condition codes and 4 program controlled flag bits. If the test is false, the next instruction is skipped.

26 Also, the high hex zone digits in Accumulator 34 or Extension 36 operends 27 can be tested for all zeros.

28 Branch Operations 29 The branch operation~ are Branch Conditional and Branch Unconditional.
They can be performed to any 4K range of Executable Storage 16. By -~ SA975071 -49-- ' ~ -1~1359 .

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storing the Current Instruction Address Register 32 plus 1 lnto one of 2 Local Store Registers 14 before taking the branch unconditional a branch 3 and link operation is performed. The reverse, taking the address so 4 stored in Local Store Register 14 and moving that address pointer back -~
into Instruction Address Register 32, performs the return to the subroutine ' 6 from which branch and link was originally taken.
7 A second grouping of branch instructions performs the multiway ; 8 table branching which can be done on the low order 4 hex bits in the 9 microcomputer registers, on the next four which are the zone 4 bits while ignoring the low order 4 or 6 bits, or on the total 8 bits, thus 11 providing a full 256 table branch from which the 8 bit Op-code can be 12 decoded by a Branch Unconditional instruction out of the table.
13 A third group of branch instructions provides signed displacement ~ L4 branching on 16 different conditions; such as: register zero or not i 15 zero, register negative or not negative. Displacement branching is :~ .
16 performed by taking the 8 bit displace~ent from the instruction and 17 adding it a~ a signed 16 bit number to Current Instruction Address 18 Register 32.
19 Other instructions allow displacement branching based on Count Register 50 being decremented by 1 or by 16 and branches taken if the 21 result is all zeros or not all zeros, if the low order 4 bits are all 22 zeros or not all zeros, if the low order 4 bits are all ones or not all 23 ones, if the high order 4 bits are all ones or not all ones, and so ~-24 forth~
Logical Move Count 26 Referring to Figure 3B, Logical Move Count (LM) instructions selectively 27 move the contents of a specified register 1-63 in.Local Storage Register 28 14 and to the Instruction Address Register 32, Accumulator Register 34, 29 Extension Register 36, or the Combined Current Condition and Count ., .
Registers 48, 50. During this transfer, the value may be modified by .

`~' 1 Q, -1, or +1, (except for moves of single bytes into Accumulator Register 2 34 or Extension Register 36), and the value as modified is written back into the selected register 1-63 of Local Storage Register 14. Conversely, 4 the specified register (Instruction Address Register 32, Accumulator Register 34, Extension Register 36, or the combined Current Condition 6 and Count Registers 48, 50) may be moved into the selected location 1-63 7 of Local Storage Register 14 with modification by 0, +1, or -1 (except 8 for moves of single bytes of data from Accumulator Register 34 or Extension g Regsiter 36.) The byte moves can spec,ify either the high or low byte of Accumulator Register 34 or Extension Register 36, but no modification is 11 performed on moves between Accumulator Register 34 or Extension Register 12 36 and the specified register in Local Storage Register 14. The Instruction 13 Address Register 32 value is composed of the 16 bit address for Read 14 Only Storage 16. The Current Condition Register 48 can only be selected ~-as the upper byte of the combined Current Condition and Count Registers 16 48, 50 if no increment or decrement is spècified. Also, Interrupt 17 Register 44 and Error Register 46 will be substituted for the Current 18 Condition and Count Registers 48, 50 if set by the KSIE control instruction 19 previously described. When the Logical Move Count Instruction specifies Location 0 in Local Storage Register 14, indirect addressing of Local 21 Storage Register 14 is selected from the low order 6 bits of Count 22 Register 50, except selection of the Current Condition and Count Registers 23 48, 50 as the destination or the source register for the move operation ~- 24 will move data to or from Current Condition and Count Registers 48, 50 from or to Local Storage Register 14 Location 0.
26 Input/Output 27 There is no distinct I/O instruction as such; direct-program-28 controlled transfers of data or control messages to or from an I/O
29 device are performed by the following instructions: Fetch Storage, Logical Write Storage, Modify Data, and Control.

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-~ l The Fetch Storage instruction transfers data from MS 12 to an I/0 2 device via the internal data path of buses 23, 25, 28: The Logical 3 Write instruction transfers data directly from an I/O device to MS 12 4 via Bus In 10 without passing through processor 9, utilizing the address from Extension Register 36 or any of the LSR 14 registers. The Modify -6 Data instruction brings data from an I/O device, performs an ALU 22 7 operation on it with Extension operand 36, and returns the result to the 8 I/0 device through Output Buffer Register 26. A Control instruction can - 9 be used to output data to a device eit,her from a specified LSR 14 (0-15) or from an immediate data field in the instructioD. Other Control ll Instructions can transfer data from any I/O Device to Accumulator Register 12 34, Extension Register 36, or LSR 14 Registers 0-15.
- 13 In all cases, the device address, specified by the instruction L4 either directly in the address field or indirectly as the contents of Count Register 50, is transmitted to the I/0 device by LC0 40 lines 21, 16 41, which are also used to address LSR 14. The transfer is synchronized 17 by a pair of handshaking signals, Sample In and Sample Out. These 18 signals together with Hold-Clock-In permit asynchronous operation of the l9 I/O transfers, independent of line length and device operation delays.
While the invention has been described with respect to preferred 21 embodiments thereof, it is apparent that the foregoing and other changes 22 m-y be e~de ~hereeo wlehOut departing frot the lnvention.

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Claims (6)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Apparatus for communicating information signals with respect to a computing chip, comprising first unidirectional bus means;
second bus means which is unidirectional with respect to said computing chip;
driver means for selectively loading information and address signals from said chip onto said first bus means during respective portions of an instruction execution cycle;
receiver means on said chip for receiving information signals from said second bus means;
first information storage means which is in bidirectional con-nection with respect to said second bus means and responsive to address signals on said first bus means during a first portion of said execution cycle for selectively loading information signals onto and receiving information signals from said second bus means;
third bus means; and second information storage means responsive to address signals placed on said third bus means from said chip for loading information signals received during a second portion of said execution cycle from said first bus means onto said second bus means for communication to said first storage means.

2. The apparatus of claim 1, wherein said second information stor-age means selectively receives data signals from said first bus means for communication to said first storage means.

3. The apparatus of claim 1, further comprising:
third information storage means responsive to address signals on said first bus means for loading control signals onto said second bus means for communication to said computing chip.

4. Apparatus as defined in claim 1 wherein said first bus means selectively communicates address and data signals from said computing chip to a plurality of input/output and storage devices;
said second bus means selectively communicates data and control signals to said computing chip from said plurality of devices; and said third bus means communicates address signals from said com-puting chip.

5. The apparatus of claim 4, further comprising third storage means responsive to third address signals on said first bus means for loading control signals onto said second bus means.

6. The apparatus of claim 4, further comprising input/output means addressed by said third bus means for loading data signals onto said second bus means and for receiving data signals on said first bus means.