CH623946A5 - Microprocessor arrangement. - Google Patents

Description

The invention relates to a microprocessor arrangement 45 according to the preamble of claim 1.

The prior art includes microprocessors with three or four separate basic functional components (see Microprocessors, Electronics “Book Series”, 1975, in particular pages 2 to 6). The first component is a fixed value 50 microinstruction address register for increasing, branching and connecting individual machine elements. The second component is the central arithmetic / logical unit, hereinafter called ALU, with its associated registers and data paths. The third component is the 55 addressing and data connection to the main memory, which is generally treated as an input / output unit and is combined in architecture with other system input / output devices. If the microprocessor is sufficiently refined, a fourth part consisting of registers 60 and data paths is present, generally called a channel. This is used to perform priority-based interruption switching and as an option for priority-controlled multiplex cycle allocation (sometimes also called direct memory access or DMA). 65 Today's microprocessors can be divided into two groups, which distribute the functions described above over a set of several chips. The different functions are separated in the first group

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Assigned chips, for example an ALU chip, a control chip, an address chip, an I / O chip and ROS / RAM chip (sometimes with address control). In the second group, the processor functions are distributed over a number of identical chips. This technique is called "bit-disk technology" and usually requires separate I / O control chips (see above publication, pages 29 to 34, 35 to 40 and 93 to 104).

Both of the solutions described above require extensive connections between the chips, which are however limited by the number of available I / O pins and consequently lead to a doubling of the logic and also to delays due to the required drivers and receivers outside the chips. If the data * or address bus are bidirectional, signals cannot be sent or received until an overall turn-off state and then an overall turn-on state is established between the drivers and receivers of each chip. This leads to further delays. In addition, each of these bidirectional bus lines requires off-chip I / O pins and drivers, which results in a larger layout and higher chip power dissipation. To overcome these disadvantages, certain architectures combine the address and data bus to form a time-divisional bus. However, this principle increases the delays.

In addition, processors on only one chip are known from the publication mentioned, pages 22 to 27, but their performance in terms of data flow width, logical and arithmetic computing power is limited by the pin and bus line problem as well as the timing and timing.

The invention has for its object to provide a microprocessor architecture for a microprocessor on only one semiconductor chip with an improved bus system and improved timing for performing the internal operation to increase the performance of the microprocessor and the number of drivers and thus the power loss and the required Reduce pins per chip.

The achievement of the object according to the invention results from the characterizing part of patent claim 1.

The fact that a unidirectional ring bus system has been found for a microprocessor integrated on a semiconductor chip, which requires only a few connections for input / output lines, has also significantly reduced the number of channel drivers and input circuits required. The performance of this microprocessor was increased by combining the new bus system with a new time control or timing device, which enables a two-part execution cycle for the instructions with overlapped and successive operations.

An embodiment of the invention is illustrated in the accompanying drawings and is described in more detail below.

Show it:

1 shows a map of the FIGS. 1A, 1B and IC, which show the structure of a microprocessor in a circuit diagram,

Fig. 2A, B, C, 3A, B, C, 4A, B, C in time diagrams the execution of a basic instruction set, which is adapted to the architecture of the microcomputer system and FIGS. 2, 3 and 4 the relationship of these timing diagrams to each other.

The four main units of the system shown in Figure 1 are:

1. a central processor (CPU) 9, with the arithmetic and logic unit 22 (hereinafter referred to as ALU), a channel with the input bus 10, the output bus 12, the address bus 21, the common call line 53 and control lines 15 and several working registers and a control circuit ,

2. local storage register 14,

3. a main memory 12,

4. A read-only memory (ROS) 16, also called execution memory or microprogram memory.

The central processor 9 can e.g. be implemented on a chip that, in today's technology, is assembled in a package that requires fewer than 70 I / O pins per module. This CPU package can be on a card together with a module for the read-only memory 16, a module for the local memory registers 14 (e.g. comprising 32 registers),

two modules for the auxiliary drivers 18 and an oscillator (represented by the output line 59). A small part of the main memory 12 can also be mounted on this card or on a second card.

Data, instructions and input / output commands are transmitted between the CPU 9 and other units via two unidirectional bus lines, namely the input bus 10 and the output bus 20. The input bus 10 receives data from the input / output devices (not shown), the main memory 12 via the main memory bus 11, from the read-only memory 16 via the read-only memory bus 17 and from the local memory registers 14 via the bus 13. Data on the input bus 10 are fed to the program register 30 and directly to the arithmetic / logic unit 22. What is important above all is the fact that data and information are fed in one direction to the CPU 9 on the input bus 10. Drivers for the transmission of the data from the chip of the CPU 9 via the input bus 10 are not required. Drivers whose power is sufficient to put data on the input bus 10 are provided for the main memory 12, the local memory registers 14 and the read-only memory 16. The main memory 12 can also take data from the input bus 10 which has been put on the line by the local memory register 14 or an input / output device via the bus 13. The output bus 20 routes the contents of the output buffer register 26 to the read only memory 16, main memory 12, local memory register 14 and the I / O devices (not shown). The output bus 20 serves as the address bus for the read-only memory 16 and the main memory 12 and for the local memory registers 14 and the I / O devices as the data bus. The I / O devices are controlled via six address lines in the bus 21, so that up to 64 local memory registers 14 or up to 63 I / O devices can be controlled directly. As I said,

the input bus 10 introduces microinstructions or data from the I / O devices or memory.

Source or destination for the transmissions on the bus lines 10 and 20 are selected via the control lines 15. These control lines 15 are excited by the auxiliary driver 18 and leave it in the illustration in FIG. 1A as control and clock lines 19. These include the selection lines for the local memory register 14, the read-only memory 16, the main memory 12, and the write lines for the high and low bytes. An I / O device is selected if the selection line for the local storage

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register 14 is not active and a valid device address is specified. The validity of the data transmissions on the output bus 20 is timed by previous one clock pulses on one of the control lines 15. Outgoing interrogation signals indicate that the local memory output code LCO and the selection code are valid. Incoming interrogation signals are a response to the outgoing interrogation signals to determine the validity of the data transfers on the input bus 10 to the processor 9 or command responses from the devices. Together with the clock input hold signal, which the input / output devices can use to prevent the CPU clock from continuing, these signals allow completely asynchronous I / O operation.

The input / output bus lines 10, 19, 20, 21 and 31 and their function are then briefly described.

The output bus 20 comprises 18 lines for the data output of the I / O devices and local memory register 14 and for the address output of the main memory 12 and the read-only memory 16.

Input bus 10 includes 18 lines for microinstructions from read-only memory 16, data input from I / O devices and local memory registers 14, and data input and output from main memory 12. Common call line 53 includes seven multiplex cycle allocation lines or seven interrupt level request lines . The cycle assignment call line is one of the lines 19 and is used for the cycle assignment call instead of interruptions on the common call bus 53. Clear interrupt priorities and request cycle mapping priorities. The address bus 21 here consists of six lines for addressing up to 64 locations in the local memory registers 14, for signaling the cycle allocation stage or for addressing up to 63 input / output devices.

The selection output for the local memory registers includes the five lines LSR selection, memory selection, ROS selection, "write high byte" and "write low byte", the control and clock lines 19. (If "write high or low Byte »is not specified, it is a read operation.)

A signal on the query output line of one of the control and clock lines 19 indicates that the LSR code output signals or a command are valid during clocks 3 through 4 and 9 through 14. The polling input includes a common line on which a selected device can respond to a polling output and can validate the data that it has placed on the input bus 10 or can respond to a command.

An I / O device requests a cycle association call when the signal rises on a cycle map input line, and when the signal falls, it indicates that its priority on the common call line 53 is valid.

A signal on an interrupt input line indicates that there are 53 interrupts pending for one or more devices on the common call line. The priorities are specified on the common call line 53. The oscillator output line 59 continuously provides a rectangular clock signal.

A signal on the reset input line resets the system in general and after the power is turned on.

The output line for clock 1 or 9 is one of the control and clock lines 19 for continuous clocking on the output bus 20 of the data that was previously on the buffer register output line 28. The clock output signals 6, 7 or 14, 15 (for instructions for a double cycle) on the lines 19 ensure the continuous clocking; their drop indicates the end of an instruction.

A lock signal for the high memory byte is generated by the device if only the low byte is to be written into the main memory 12. A lock signal for low memory bytes is issued by the device if only the high byte is to be written into main memory 12. If the device raises both signals at the same time, the main memory should be read.

The memory data selection can result in data from the main memory 12 on the input bus 10. By disabling memory data selection, a device can put its data (e.g., a main memory address) on the input bus so that it is written to the local memory address registers (address registers for cycle mapping).

The control signal LSR write is issued by the device in order to concatenate data tables in the main memory or to prevent an increase in the address in the local memory register 14.

Local memory register output code (LCO) lines 21, addresses 0 to 63, together with LSR select line 19, address the local memory register 14, positions 0 to 63. Positions 16 to 23 are used for interruptions and positions 24 to 31 for cycle assignments. LCO 21 addresses 1 to 63 without LSR select line 19, address I / O devices 1 to 63, whereby address 0 is reserved for channel functions.

In the central processor 9, the input bus 10 runs to the ALU 22 and to the program register 30. The output of the program register 30 is conducted via lines 33 to the ALU 22 and to the instruction decoder 62. The address portion of an instruction stored in the program register is also passed through line 31 to the LSR output control register 40 and the degradation register 38. The output of the degradation register 38 is fed back via line 39 to the program register 30, the current condition register 48 and the count register 50. The output of the count register 50 is passed on line 51 to the decrement register 38 and the LSR output control register 40. The output of register 48 is provided via line 49 to register 42 for the reserved condition code. The outputs of register 48 and count register 50 are also sent to ALU 22 via line 43. The data flow of the CPU 9 16 bit for the ALU 22 and the following operation registers:

The accumulator register 30, the content of which can be routed via line 33 to each side of the ALU 22. The accumulator expansion register 36, the contents of which can be routed via line 37 to either side of the ALU 22.

The total register 24 is the output buffer for the ALU 22 and is loaded by the bus 23. Program register 30 holds the macro instruction that is to be decoded by instruction decoder 62 and then executed. The contents of the program register 30 can also be routed to the ALU 22 via the bus 33. The contents of the microinstruction address register 32 can be routed to the ALU 22 via line 29 for address modification or for branching and connecting operations. With the count register 50, shifts are counted and the local memory registers 14 are addressed indirectly. The contents of the count register 50 can be routed to the ALU 22 via line 43 to perform various operations.

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The output buffer 26 holds data given on the buffer register output line 28. After the auxiliary driver 18, this buffer register output line 28 appears as an output bus line 20. Special instructions to be described save the content of the output buffer register

26 into the local memory register 14, item 0, where they can then be input into the ALU 22 via the input bus 10 for various operations. The output of the total register 24 appears on the bus 25 and is passed under control of the signals from the instruction decoder 62 to load the following registers: the micro-instruction address register 32, the accumulator register 34, the accumulator expansion register 36, the error register 46, the interrupt mask Register 44, the count register 50, the current condition register 48 and the output buffer register 26. The output of the interrupt mask register 44 is fed to the ALU 22 via lines 45 and 43 and to the interrupt gate 52 via line 45. In addition, the output of the total register 24 consisting of the four lower bits can be carried out via the line

27 the high-value bits of the microinstruction address register 32 are supplied.

The common call line 53 multiplexed for cycle assignments and interrupt requests is connected to the interrupt gate 52 and the priority encoder 54. The connection to the priority encoder 54 is for cycle assignments that have a higher priority than interruptions. The output of interrupt gate 52 is routed to priority encoder 54 via lines 69. Its output is passed over lines 55 to the interrupt pending register 56, an interrupt test circuit 58, and the LSR output control register 40. The output of interrupt test circuit 58 appears on line 63 for forcing a higher level interrupt enforcement signal. The output of register 56 is passed on lines 57 to interrupt test circuit 58 and to LSR output control register 40.

The clock signals on line 59 from a single-phase oscillator are fed to the 4-phase generator 60, the output of which runs on line 61 to the clock generator 66 and the auxiliary clock generator 64. The output signals of these clock generators and the output signals of the instruction decoder 62 control the operation of the CPU 9 including the connection of the bus to the various operand registers and the time division of the various bus lines and registers.

The cycle assignment and the interrupt channel are described in more detail in connection with FIG. 5. Wherever possible, the same reference numbers will be used as for the elements in FIG. 1. Lines 530 to 536 in FIG. 5 represent the individual lines of common call bus 53 in FIG. 1 in negative logic. Lines 450 to 456 are the output lines of interrupt mask register 44. Call cycle allocation latch 75 has an output reset Line 80. In interrupt gate 52, the signals on line 450 (belonging to the O bit of interrupt mask register 44) are ANDed with the signals on output reset line 80 and the result with the signals on line 530 which represent the O bit position of the common call line 53, NOR-linked. The result appears on line 520. Similarly, bits 1 through 6 of interrupt mask register 44 on lines 451 through 456 are ANDed with the signals on output reset line 80 and the results with bit positions 1 through 6 of FIG common call line 53 on lines 531 to 536 NOR-linked.

The results appear on lines 521 through 526. Line 520 is routed to NOR gates 86, 94 and 95. The line 521 leads to the NOR gates 86, 90 and 95, the line 522 to the NOR gate 86 and to the AND gate 91. The line 523 leads to the NOR gates 86 and 90, the line 524 to the NOR gate 86 and to AND gate 92. Line 525 leads to AND gate 88 and NOR gate 90. Line 526 leads to AND gate 93. The output of NOR gate 86 appears as -4 priority line 544 and leads to the AND gates 87, 88 and 92, to the register 56 for the current interruption (item 4), to the interrupt check circuit 58 and to the AND gate 82. The output of the NOR gate 95 appears on the -2 priority line 542 and becomes the AND gate 91, the register 56 for the current interruption (Pos. 2), the interruption test circuit 58 and the AND gate 82 fed. The output of the NOR gate 90 goes to the AND gate 93. In the NOR gate 95, the outputs of the AND gates 87 and 88 are linked to the signals on lines 520 and 521. In NOR gate 94, the outputs of AND gates 91, 92 and 93 are linked to the signals on line 520 and appear on line 541, which leads to register 56 for the current interruption (item 1), to interrupt check circuit 58 and leads to the AND gate 82.

With the inverted signal on the assignment request line 68, the call cycle assignment lock 75 is locked. The energizing output of this latch on lines 77 latches the cycle map confirmation circuit. The reset output of the polling cycle assignment latch 75 on the output reset line 80 latches the AND gates in the interrupt gate 52 and disables the interrupt stage switch latch 84. Its output on lines 79 controls the charge line for a new interrupt stage 72 and energizes line 57 for the current interrupt stage. The negative signal on interrupt request line 70 is fed to cycle map acknowledge circuit 76 and inverted for interrupt stage switch latch 84. The negative signal on the assignment request line 68 is also sent to the cycle assignment confirmation circuit 76. The switch-on output appears on line 55 and is linked in AND gate 89 with a clock pulse on line 85. The signal on line 78 runs to AND gate 82 and to the high bit input lines 834, 835 to force a predetermined code into them.

Lines 310 to 314 represent the lower-value bit positions of the address part of program register 30 and are shown in FIG. 1 as line 31. Lines 310 through 314 are routed to AND gates 83 where their signals are individually linked to the signals on microinstruction turn-on line 74. They then run to the LSR output control register 40 via the output lines 831 to 835.

The outputs of the AND gates 82 are connected via a DOT-OR link to the signals on lines 831 to 833, the low-order bit positions of the input to the LSR output control register 40. The output lines of the AND gates 81 with the low-value lines become the same 831 to 833 connected to the LSR output control register 40. In the AND gate 81, the output signals of the register 56 for the current interruption appearing on the lines 561, 562 and 563 are combined with the signals on the switch-on line for the "current interruption" stage 73 and the interruption test circuit 58. The switch-on line for the «Current

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Interrupt »stage 73, which directs the contents of register 56 for the current interruption on the three lower-value input lines to LSR output control register 40, also forces on high-value input lines 834, 835 similarly to line 78 a certain but different code, this time so as to put an address on the output lines 41 of the LSR output control register 40 which points to another location in the local memory register 14.

Cycle assignments have priority over interruptions. Signals on the cycle map request line 68 immediately override the normal continuous interrupt call by locking the call cycle map lock 75, thereby requesting all devices to set their cycle map priorities on the common call line 53, lines 530-536, and to withdraw their interrupt requests. If the signal on the interrupt request line 70 is no longer present, this indicates to the microprocessor 9 that all devices have taken their interrupt priority bits from the common call line 53. When the signal on map request line 68 disappears and the polling cycle map latch 75 is latched, it is ensured that the output lines 541, 542, 544 of the priority encoder 54 can be switched to the LSR output control register 40, along with the cycle map modification bits on the Lines 78 in the high positions 834 and 835. In addition, signals on the cycle mapping confirmation lines 55 are given to the I / O devices. The cycle mapping register in the local memory registers 14, which is addressed by signals on the output line 41, supplies the indirect main memory address to the bus line 13, which can also be increased by the arithmetic / logic unit 22 to fetch or store data from the device . The lowest priority cycle mapping level does not need a priority bit and its forced device address portion is zero to allow all binary device addresses. At the beginning of the cycle mapping cycle, call cycle mapping latch 75 is reset to return to the continuous interrupt call or sequential execution of the microinstruction. The call cycle map lock 75 can also be locked again because it first has to be unlocked so that the devices can energize the map request line 68 when sequential cycle maps are needed. Interrupt mask register 44 is cleared whenever call cycle assignment latch 75 is latched. Asynchronous cycle mapping requirements of the devices can be controlled by microprocessor clocking or by locking the call bus so that the priority circuit can be stabilized.

Organization of a unidirectional manifold for input / output

The connection of the unidirectional external input and output busbars internally in a closed loop with the arithmetic / logic unit 22 allows the internal processing and external modification of I / O data, the interrupt level switching and the increase of the cycle allocation address so that several stages of interruptions and cycle mappings can share the existing arithmetic / logic unit 22 and highway with a minimum of control logic and without additional buffer registers.

For this purpose, a unidirectional bus line is used, which leads from and to the CPU chip 9. Data and address are mixed on the same outlet manifold. The

Input bus 10 is the only data input bus to CPU chip 9. Main memory 12 is terminated to this bus as well as local memory registers 14. While the unidirectional function of input bus 10 with respect to CPU chip 9 is maintained, input bus 10 becomes main memory 12 is used for reading and writing data while the output bus 20 holds the address of the main memory 12.

The input bus 10 also acts as an external input for one side of the arithmetic / logic unit 22, (ALU), the output of which is temporarily placed in the total register 24. The total register 24 has an output bus 25 which leads to each register in the CPU chip 9. The bus 25 is connected to the output buffer register 26 on one side and comes from there out of the CPU chip 9 and forms the output bus 20, which in this example has a data flow width of two bytes. Output bus 20 provides data to local storage registers 14 and a number of I / O devices, not shown. On a time divider basis, the output bus 20 also functions as an address bus for the read-only memory 16 and for the main memory 12. In the hybrid structure of the bus lines according to the invention, data and addresses are thus contained on the output bus 20 and data and instructions on the input bus 10.

Since there is no direct data path from the CPU chip 9 to the main memory 12, the CPU places the results in the local memory registers 14. Then the unidirectional input bus between the local memory registers 14 and the main memory 12 is used in the opposite direction. Relative to the processor chip 9, the input bus 10 is thus kept unidirectional in that the output bus 20 can, if desired, put the result into the selected local memory register 14 for each internal microinstruction for data modification without additional instruction or time unit. This enables sequential and simultaneous operation on both bus lines. Output buffer register 26 may address the next microinstruction in read only memory ROS 16 while the previous microinstruction is executing in overlapped mode with the data on input bus 10. Similarly, the main memory 12 is driven directly via the output buffer register 26 between these two types of addressing. A narrow section of data transfers data to the local storage register 14 or I / O device which is addressed by a separate six bit address bus 21 which also signals the appropriate cycle allocation confirmations or interrupt level switches. By reserving one of the 64 local memory registers as the bus output register, the internal data flow on the chip 9 can be arranged around a common arithmetic / logic unit 22. The total register 24 feeds all other internal data and addressing registers as well as the output buffer register 26, which also remains reserved for program use as a register for the fourth operand in the buffer of the local memory register 14. In this way, any external I / O device can share the ALU 22 with internal processing. The external unidirectional bus lines also allow total internal transparency of the CPU chip 9 for the interruption level switchover and direct memory channel addressing (cycle allocation). The memory address is automatically increased via the common ALU 22 and a data path. The architecture of the system's manifolds also allows over 5

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lapped and sequential execution of instructions, examples of which are given below.

In a first example, when ROS instructions are on the input bus 10, serialization occurs usually at the beginning and end of each microinstruction cycle, and at the same time the output bus 20 begins to send data to an I / O device.

In a second example, there is overlap when data on the input bus 10 comes from I / O devices or the local memory registers 14 and is processed internally by the arithmetic / logic unit 22 and at the same time the output bus 20 contains the next address of the ROS 16, so that the next following instruction is addressed.

In a third example of the overlapped operation, data from the execution of a previous instruction is still to be stored in the local memory register 14 and the execution of a new instruction has already started. Local memory register 14 is loaded during clock 1 of the new instruction cycle, while execution of the new instruction started at clock 0. The six lines of the LSR output control register 40 form an additional address bus 21, 41 for addressing 64 half-words of the local memory register 14 or up to 63 I / O devices on the output bus 20 depending on the type of instruction being executed. The combination of this additional mini address bus and the input bus 10 and the output bus 20 allows operations to be performed in one cycle. An I / O device can put data on the input bus 10 during the same instruction, have it processed by the ALU 22, and receive the arithmetically or logically changed data on the output bus 20 while the device is being addressed by the address bus 21. This is an advantage over conventional channels, which require three instructions for simple I / O data transmission without an ALU operation. To do this, the processor must first send out an address on a common I / O bus. Then the device must respond via a request / response interface to indicate that it has recognized its own address. The processor needs a second instruction to send out a command to which the device can respond. The processor must then execute a third instruction and read or write depending on the desired data flow direction.

The output bus 20 is multiplexed so that an overlapped operation occurs for each instruction executed. Overlapping means that the next instruction is addressed by the read-only memory 16 while the processor is simultaneously executing the current instruction internally. The common manifolds use e.g. five clock periods of the eight clock period instruction cycle to address the ROS 16 and the remaining three clock periods to send data to either the local memory registers 14 or the I / O devices.

Main memory 12

Main memory 12 forms an addressable and writable memory for storing data by both the processor and the I / O devices for later reuse. Data is transmitted in read and write operation via the main memory bus 11 from and to the input bus 10. The control and clock lines 19 supply the clock and control signals and the address is routed via the output bus 20.

When accessing the main memory 12, the instruction becomes an additional cycle to a double cycle instruction. During the first cycle, the address on the address pointer to main memory 12 is incremented, decremented, or otherwise changed. This address pointer comes from the local memory register 14 or from the B register 36. (This gives the possibility that batch processing, even if no batch pointer is used, since the system of automatically increasing / decreasing the address acts in the same way as the stack pointer.) The main memory becomes read or written in the second cycle after the address pointer to main memory 12 has been updated to the effective new address. The address is held in output buffer register 26 for the entire second cycle. This second cycle is called the main memory cycle below and comprises eight clocks for addressing the main memory 12.

The main memory 12 is operated in series as follows: During a main memory call, data is fetched from the main memory 12 onto the input bus 10 and stored in one of the internal registers of the processor 9. At the end of the polling operation at clock time zero, when the next instruction is to begin, this data is passed through the ALU 22, placed in the total register 24 and transferred from there to the output buffer register 26. The current main memory address is destroyed by this data transfer into the output buffer register 26.

Read-only memory (ROS) 16

The read only memory 16 stores the instructions to be executed which contain the microcomputer control program. These instructions are loaded onto the input bus 10, buffered in the program register 30 and decoded at the instruction decoder 62. Together with the clock circuits, the switching elements, registers and circuits are linked to one in connection with FIGS. 2 to 4 explained in more detail controlled so that they carry out the various instructions.

The ROS 16 is operated in series and so the instruction from the input bus 10 is placed in the program register 30 at clock time zero, the usual start of each microinstruction. At the same time, data is placed in the output buffer register 26. Thus, data addressed by the ROS 16 on the output bus 20 is taken from the input bus 10 and at the same time the address on the output bus 20 is destroyed. Because of inherent delays in the circuitry including the drivers and logic gates, these operations occur sequentially.

Local Storage Register (LSR) 14

The local memory registers 14 consist of several addressable and changeable register locations. Data is written from the output bus 20 to the LSR 14 and read out to the input bus 10, addressed via the address bus 21. Data set on the input bus 10 can be passed directly to the main memory 12 or the processor 9. The zero position in the LSR 14 is reserved under conditions to be described for saving data from the output buffer register 26.

Arithmetic / Logical Unit (ALU) 22

On a time divider basis, the arithmetic / logic unit 22 is used jointly for data processing, increasing the microinstruction address, branching in the case of relative addressing, connecting subroutines, main memory addressing, changing the address, retrieving and storing data, processing the priority

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knotted. Interruptions and used for cycle allocation.

For this purpose, the address register 32 is integrated into the data flow of the arithmetic / logical unit 22 and the local memory register 14 is used. The address register 32 (a simple non-increasing polarity holding register) uses the ALU 22 in alternating half cycles to increase or otherwise change the instruction address in the ROS 16. The positive or negative branching and connection of the relative address is simplified by this simple data path to the ALU 22. Since the ALU 22 outputs its output to the output bus 20, micro addresses can be stored in the local memory registers 14 as return pointers of interruptions. This also allows new interrupt routine pointers to be loaded and previously interrupted pointers to be restored since the local memory registers 14 pass their values onto the input bus 10 and into the address register 32 via the ALU 22. In this way, a priority-linked expandable interrupt structure is made possible, which can be included in the basic data flow within the ALU 22. The zero position in the LSRs 14 is reserved for saving and restoring the content of the output buffer register 26.

Processor 9 fetches data from main memory 12 via input bus 10 and ALU 22 for storage in its internal operand registers. The output buffer register 26 holds the address of the main memory 12 from the selected LSR 14 or the operand register (such as the accumulator expansion register 36) for simultaneous addressing and updating. Processor 9 data that is to be stored in main memory 12 as a result of the execution of an earlier microinstruction is first sent to a selected LSR 14 via output buffer 26. The microinstruction for writing to main memory 12 routes the data in LSR 14 to input bus 10 and then to main memory 12.

In addition, certain locations in the LSR 14 can also act as indirect addresses of the main memory 12, in direct cycle assignment operations for an I / O device, with each priority level being assigned an LSR 14. Each I / O device contains its data length counter. The address registers of main memory 12 in LSRs 14 are automatically incremented via ALU 22 on output bus 20 to write I / O data on input bus 10 to main memory 12 or to read data from main memory 12. This data runs through the ALU 22 via the input bus 10 and is made available to the I / O devices on the output bus 20. The I / O devices receive data from processor 9 on output bus 20 and send data to processor 9 on input bus 10.

Emulated instructions are also decoded in the ALU 22. The operation code of the emulated instruction is added by the ALU 22 to the current instruction address in the micro-instruction address register 32 and thus results in a relative address pointer to a table in the ROS 16 just below the currently executed current instruction. In this way, a branch is obtained in 256 ways to the instructions in the ROS 16 for executing the emulated instruction.

By sharing the microinstruction address register 32, there is a switch between interruptions on the same data path that also exists for the execution of the basic instruction. The instruction address value resulting in the microinstruction address register 32 is stored in the local memory register 14 via the ALU 22, the total register 24, the bus 25, the output buffer 26 and the output bus 20. In the event of an interruption, the pointer to the next instruction that would have been executed at the current program priority level is saved in the LSR 14. Next, the higher level to be performed is determined using a priority code that is generated in the priority encoder 54 and that generates an address in the LSR output control register 40. This address is used to control the location in the local memory register 14 which contains the pointer to the relevant subroutine in the read-only memory 16 for the interrupt stage concerned. This pointer is then transferred from the local memory register 14 to the processor 9 via the input bus 10 ALU 22 is given and placed in the total register 24 before it is stored in the microinstruction address register 32 and the output buffer 26. From there the subroutine which is to be executed for the interrupt stage is actuated in the read-only memory 16. If the interrupt has been operated, the current interrupt subroutine pointer is stored in LSR 14 and the address pointer for the interrupted program is fetched from there again.

Program register 30

The program register 30 is a buffer for the current instruction and holds the op code of the instruction that is executed by the processor 9.

The count field or address field of instructions stored in the program register 30 can be passed directly to the decrease register 38 and the LSR output control register 40.

Total register (Tj 24

The output of ALU 22 is placed in total register 24 and bus 25 is loaded from it at least twice during each instruction execution cycle. The address of the instruction to be executed next is loaded once and the execution results of the function specified in the instruction are loaded by the ALU.

Since data from the arithmetic / logic unit ALU 22 is temporarily stored in the total register 24 and then buffered in the output buffer 26, one function can be carried out on the input bus 10 and another can be ended on the output bus 20 at the same time. This two-stage buffering in the loop allows overlapped operation.

Instruction Address Register 22

The content of the microinstruction address register 32 is changed during the execution of each instruction by the ALU 22 so that the address in the ROS 16 points to the next instruction to be executed.

Accumulator register 34 and expansion register 36

The two working registers are the accumulator register 34 and the accumulator expansion register 36, each with a capacity of 16 bits. As a result, 32 information bits can be shifted, for example arithmetically or logically to the left or right. In addition, a left shift and counting or a rotation to the left or right is possible.

Together with the count register 50 and the output buffer 26, these registers are the internal registers that can be directly addressed by the microinstructions for internal arithmetic and logical calculations. Their content can also be changed using an external local storage register 14 or vice versa. The result can be stored in one of the internal registers or in one of the local storage registers 14.

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Output buffer register 26

The output buffer register 26 has two functions. As an operand register for the ALU 22, it holds data controlled by the microprogram. In addition, addresses and data must pass through the output buffer register 26 in the event of an interruption which forces the transfer of address pointers or in the case of direct memory accesses. In this way, the output buffer register 26 does not lose data used by the microprogram. The zero position in local storage registers 14 is reserved for the contents of output buffer register 26 whenever processor 9 changes instruction addresses and data, whether under the control of an interrupt or during a cycle mapping operation. Afterwards, the value of the output buffer register 26, which is stored in position zero of the LSR 14, can be called up again as the operand value of the ALU 22. In this way, no recourse storage for the output buffer register 26 is required on the chip for the processor 9.

Driver 18

When the output line 28 leaves the processor 9, it runs to the auxiliary drivers 18, the output of which is the output bus 20. In a highly integrated chip, each driver can only drive one load. Since the output manifold 20 leads to many units or loads, it must be driven again. (With this new power supply, the number of channel lines developed can be expanded by coding the existing lines for an upper or lower level during the different clock periods of each microinstruction cycle of the eight clocks.)

Humiliation Register 38

The humiliation register 38 is used to count in all instructions for displacement, multiplication, division, humiliation, testing and branching. The decrement register 38 has input signals from the program register 30 as soon as a shift operation requires a direct shift up to 32 positions, and stores the decremented value in the program register 30. For indirect shifts in which the count register 50 contains the shift number value, the same decrement is used by one as with the direct shifts. The decrement register 38 holds the decremented value before it is returned to the count register 50.

Since, in this exemplary embodiment, a maximum of 32 positions can be shifted, a decrease register 38 of five-bit capacity is sufficient. For field length operations, however, the count register 50 is also used as a field length counter. This requires a full eight-bit humiliation function. For this purpose, the content of the five-bit degradation register 38 is circulated twice.

The first time you take a four-bit character from the counting register 50, lower it and save the carry to the high fifth position. The stored carry that may be present is decreased together with the four high-value bit positions from the count register 50 and forms the full eight-bit decreased value which is reloaded into the count register 50.

LSR output control register 40

It addresses the I / O device or the location in the local memory registers 14 to which the data are to be transferred.

Condition register 48

The upper four bits of the current condition register 48 hold the four condition codes and the lower four bits four programmable marks. These bits form the unconnected high byte of the count register 50. With each arithmetic operation, the four condition codes are set for subsequent field-connected operations. The four conditions are: binary carry, two's complement overflow, two's complement minus, and the cumulative unequal O indicator. Once this unequal O indicator is set in a field length, it remains set until it is changed by a microinstruction.

Count register 50

The second operand register for the ALU 22 is the count register 50, which can also serve as a shift counter. The shift number originally stored in the count register 50 is reduced individually or for both for each shift in the accumulator register 34 or in the accumulator expansion register 36, if they are interconnected for a shift operation. In the case of an instruction “shift left and count”, the shift is terminated as soon as the value-high bit is found, and the value remaining in the count register 50 indicates how far the shift has progressed. In many operations, this value therefore becomes the indirect address pointer to the ROS 16 or the LSR 14. The count register 50 can be loaded by the bus 25 and its content can be changed via the ALU 22. The result is then loaded into the LSR output control register 40 to drive the LSR 14 via the address bus 21 or the input / output devices via the output bus 20.

For indexed address calculations and the calculation of effective addresses, the count register 50 is used to store positive or negative relative addresses combined with the data by the ALU 22. The result is stored in the local memory registers 40 or in an internal register of the processor 9.

Registers 42 and 48 for reserved condition code or for ongoing conditions

The output of the current condition register 48 is selectively buffered in the reserved condition code register 42. The basic condition codes resulting from ALU operations are: overflow, carry-over, cumulative not zero, minus. The current condition codes reflect the result of the last execution of an arithmetic microinstruction. All high-value bits shifted to the left are pushed into the current carry indicator. When shifting to the left and counting, the value-high bit can set the current carry indicator. The condition codes are not changed by the processes

Loading, saving, moving, logical links,

Raises, humiliations, jumps and ramifications.

Codes in registers 42 and 48 can be deleted separately and queried individually by jump instructions. In addition to these condition codes, there are four marker bits controlled by the program which, in combination with the current condition codes, form the content of register 48. When a microinstruction is emulated, the correct current micro level code is transferred to register 42 to obtain the micro level condition code of the emulated speech on the micro level.

Interrupt mask register 44

Interrupt mask register 44 contains the current mask state of the allowable interrupt levels. The contents of the interrupt mask register 44 can also

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changed via the ALU 22, stored in the local storage register 14 or retrieved from there.

Error register 46

The two lower-order bits of the mask register 44 form the 1-byte error register 46, which checks and registers errors. For example, the following machine errors are registered: a parity error on an instruction fetched by the ROS 16; a data error in data from the local storage registers 14; a parity error in main memory 12 that was discovered by a parity check on input bus 10; a parity error on data received from an I / O device; a channel hang condition in which an input / output device neither exchanges data nor allows the microprocessor to advance to the next microinstruction; or timeout errors, such as occur when an I / O instruction is given to an I / O device that does not exist and therefore the address cannot be recognized. These errors can be placed in the error register 46 and changed, saved, checked or stored in the LSR 14. If one of these errors is automatically set by the machine equipment, the highest interrupt level (level 7) in the microprocessor is forced to branch to a subroutine that can either retry the operation or end the ongoing function and signal the operator console.

Four-phase generator 60 and clock 64, 66

A single-phase oscillator 59 is the input to the four-phase generator 60, which feeds two clocks, namely the auxiliary clock 64 and the basic clock 66. The basic clock 66 is a two-phase clock that can be stopped in every other clock position. Four overlapping locked states result in eight clock decoding positions. The basic clock 66 cycles through the eight positions in each microinstruction cycle. The high lock position in the basic clock 66 is used in addressing the main memory 12 when the microinstruction being executed needs a double cycle. Then the basic clock 66 passes through the same eight positions again, but by switching on the flip-flop in the high position, the output of the basic clock 66 is coded this time as clocks 8 to 15. The decoding of the auxiliary clock 64 provides four distinguishable periods along with a flip-flop in a high position that is used when the clock goes through a repetition cycle. This shows the largest timeout section of two clock passes, which is equivalent to an entire instruction execution cycle. The auxiliary clock 64 is used for shifts, multiplications or divisions. During these instructions, master clock 66 is stopped in its seventh position. This allows cycle assignments to continue in the middle of shift multiplication or extended division operations. The auxiliary clock 64 also serves to time-out when I / O devices fail to respond, or when an I / O device is detected on the input bus 10 during data exchange operations and attempts to exchange data. When the timeout exceeds the assigned time, the time in the auxiliary clock 64 expires and sets indicators in the error register 46 so that an interruption of the highest level or a machine test is initiated.

Integrated channel for cycle allocation and priority break

FIGS. 5 and 1 show the cycle assignment and interrupt functions as they are carried out by the common call line 53. This has eight cycle assignment levels or seven interrupt request levels. The common call line 53 is seven bits wide here to accommodate the requests for seven interrupt levels above the currently executed program level, for a total of eight interrupt levels. Each I / O device can be connected to any of the seven priority request interrupt lines. Interruptions are continually polled, except when the polling cycle assignment lock 75 is locked and the cycle assignment is in progress. Once an I / O device requests service from processor 9, it places its request on associated priority bit line 530-536 of common call line 53. Several requests go through priority encoder 54, where the request with the highest priority is in a three-bit code on the lines 541, 542, 544 is encoded and designates one of the eight different priority levels. The priority of the interrupts is also controlled by the interrupt mask register 44.

If the mask in interrupt mask register 44 is set to allow the interrupt, then AND gates in interrupt gate 52 pass the interrupt signals to priority encoder 54 to set the code of the currently requesting priorities. This interrupt priority is compared in the interrupt check circuit 58 for a higher interrupt level with the current interrupt level, which is stored in the 3-bit interrupt register 56 for the current level. The content of register 56 is continuously compared with each new level by priority encoder 54 to determine whether the new code is higher than the current one. If so, the next instruction in the current chain is not executed, but instead the address pointer in instruction address register 32 is transferred to the current stage location in local memory registers 14. The new or higher level pointer is then set from the local memory registers 14 into the instruction address register 32.

The address for the interrupt routine in the local memory registers 14 (one of the 8 possible interrupt pointers) is derived as follows: The three least significant bits on lines 561, 562, 564 from the interrupt register 56 for the current stage are turned on under the control of the AND gate 81 the input lines 831, 832, 833 of the LSR output control register 40 are given. The current interrupt stage power-on line 73 loads the high-value lines 834, 835 with the remaining bits of the address in the LSR output control register 40 to store the interrupted pointer in the LSR 14. The new pointer to the interrupt registers in the LSR 14 is similarly loaded into the LSR output control register 40 on the high value input lines 834, 835 from the load line 72 for the new interrupt level and on the low value lines 831 to 833 from Interrupt register 56 for the current stage after the switch-on line 73 for the current interrupt stage has loaded the new content of the priority encoder 54 into the interrupt register 56 for the current stage. This changes the new address in the LSR output control register 40 to the address for the location in the LSR 14 that contains a pointer to the subroutine for executing the interrupt for the selected level in the ROS 16. The address pointer arrives on the output bus 20 from the instruction address register 32 and runs through the local memory register 14 through the ALU 22 to the total register 24. When the subroutine of the new interrupt stage is completed, one is executed

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Branch output instruction given and thereby the pointer is reset to the originally interrupted program. Because the interrupt serving subroutine also deferrals the interrupt, the request for the same interrupt should not exist. If another interrupt arrives at the same or a higher level, the program does not return to the original program position but deals with the newer interrupt request. This enables a full commitment up to 8 interruption levels. In addition, several sub-levels can exist for each level. Once a given interrupt level is recognized, an interrupt level status word (1LSW) is given to all I / O devices and one of the 16 devices currently requesting operation at a particular interrupt level must identify itself. (In this way, 16 sub-levels can be obtained for each of the 8 levels, for a total of interruptions to 128 sub-levels.) With the interruption level status word received in a register of the processor 9, it can be determined which of the 16 devices at the relevant level requests operation . This is done with the help of a left shift and counting instruction. The first bit in the highest value position stops this instruction and the remaining number in the count register 50 indicates the position of the subroutine for the device in question.

The common call line 53 is also used for cycle allocation, but must first be freed from interrupt requests. By means of a device requesting a cycle assignment, the assignment request line 68 is set to a logic negative level. Once a signal on this line has latched polling cycle lock 75, a signal on line 77 comes up immediately. This prompts the devices to take their interrupt requests from the common call line 53 until the cycle mapping function is complete. As soon as all devices have taken their signals from the interrupt request line 70 and the assignment request line 68, the cycle assignment confirmation lock 76 is locked in the next clock 0, indicating that the common call line 53 has the cycle assignment priority for the has requesting device that goes directly into the priority encoder 54 bypassing the interrupt gate 52. As a result, 3 bits of an LCO priority address come from the priority encoder 54 and are passed to the AND gate 82 via the line 78 (clocked output of the cycle assignment confirmation lock 76) into the LSR output control register 40, together with the fixed, higher-value address pointer bits in the LSR 14 for the cycle allocation level which is used as the address of the main memory 12. This stores or reads data in main memory 12 under full control of the I / O device to such an extent that only the upper or lower byte is set (instead of the 2 bytes in half-word mode). In this mode, the interrupt register 56 for the current stage remains undisturbed because the interrupt stage (program stage or a higher executed stage) is delayed by the interruption of this one cycle assignment instruction. Memory access is initially addressed by a pointer from the LSR output control register 40. It contains the 3 low-order bits, which indicate which of the 8 cycle allocation levels is currently being confirmed, and the high-order bits indicate a relative address for the half-word registers in the local memory registers 14, which contain the indirect memory address. This address is read from the local memory registers 14 onto the input bus 10 and incremented by the ALU 22 before being placed in the output buffer register 26. During the memory access time of the main memory 12, the increased address on the output bus 20 can be updated, written to the cycle map register in the local memory registers 14, or a write back can be prevented by confirming the I / O devices so that the cycle map address remains unchanged. After an access time, data is read from the main memory 12 onto the input bus 10 when the I / O device allows the readout of the main memory 12 and blocks the write pulses that appear on the control and clock lines 19 from the processor 9. The I / O device can put its own data to be written into the main memory 12 on the input bus 10. The device can thus fully control the increase function and the read or write operation via the integrated ALU 22. In the write mode, the device can still find its own data on the output bus 20 during the following clock 1 once the operation has ended. In read mode, the data read out on the input bus 10 flow through the ALU 22 into the total register 24 and the output buffer register 26 and are made available to all I / O devices on the output bus 20. The data is, however, only recorded in read mode by the I / O device, which recognizes the cycle assignment level code on the address bus 21. Processor 9 then returns to normal instruction execution or interrupt routine processing which has been suspended for that one cycle of direct memory access or cycle allocation.

Description of the timing

In connection with the FIGS. 2 to 4, the timing is initially described generally because all instructions have a similar timing for execution. This is followed by a detailed description of each type of instruction.

The clock cycle is divided into eight different times, clocks 0 to 7. The clocks 8 to 15 are repetitions of the clocks 0 to 7 and they only appear during an operation in the main memory 12 including the direct memory addressing. The basic instruction time of eight bars is divided into two parts for use by the ALU 22. During clock 7 through clock 2, ALU 22 increments or otherwise changes the contents of instruction address register 32. Bars 3 through 6 are used by all microinstructions for processing. In this way, the ALU 22 is used continuously 50% for the execution of the instruction and 50% for the update of the instruction pointer. The basic window, in which the address for the ROS 16 appears on the output bus 20, begins at the clock time 3 when the calculated new address pointer is loaded into the total register 24 by the ALU 22 and transferred to the output buffer register 26. This address remains unchanged until the following clock 0 when the content of the output buffer register 26 is changed so that the register then contains the data for either the local memory register 14 or an I / O device on the output bus 20.

The clock 0 begins each microinstruction by loading the instruction from the read-only memory 16 into the program register 30. This buffering in the program register 30 enables the instruction to be executed, while in clock 3 the address in the ROS 16 is changed as described above to include the next microinstruction to address.

The instruction address is loaded into the total register 24 at cycle time 2 and that of the ALU 22 at cycle time 6

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Data processed during the execution of the instruction. During clock time 3, the next instruction address is placed in the output buffer register 26 to then be placed on the output bus 20.

If data is to be written into the local storage registers 14 by the microinstruction, this data is written during clock 1 of the instruction after the instruction in which the data was calculated. The data is written from the output buffer register 26 via the auxiliary drivers 18 directly to the location of the local memory register 14 which was selected by the signals on 6 lines of the LSR output control register 40. Similarly, data can be transferred to an I / O device by loading it into output buffer register 26 at clock time 0. A signal on the control and clock lines 19 during the clock time 1 indicates that the data on the output bus 20 are valid. This data changes at the beginning of the clock time 3 when the address of the read-only memory 16 appears in the output buffer register 26. Data that arrive in the CPU 9 for storage or modification on the input bus 10 must arrive at the ALU 22 during the cycle times 3, 4, 5 and 6 and be valid. During this period, the ALU 22 carries out the processing indicated by the executed instruction. For the same reason, data from LSR's 14 is placed on input bus 10 for processing by CPU 9 during clock time 2. During cycle time 3, which provides for signal delay, the data is available for the ALU function.

Data from the local memory registers 14 are first placed on the input bus 10 at clock time 2 and are only forwarded to the ALU 22 at the start of clock time 3, because the ALU 22 is busy updating the content of the microinstruction address register 32 during clocks 7 to 2. At the beginning of the clock time 7, the content of the ALU 22 is transferred back to the address increment function after the basic processing function of the microinstruction has ended.

For microinstructions that fetch data from main memory 12 and place it in one of the registers of CPU 9, the second cycle (clocks 8 through 15) has a slight variation in that the next microinstruction during clock 8 is fetched by ROS 16, though the current instruction is executed up to bar 15 and further to the next bar 0 (see FIG. 2). At this time, data from the main memory 12 is finally put into the specified register of the CPU 9 or sent to an I / O device. In this case (after each addressing of the main memory 12 by an instruction), no new instruction is passed into the program register 30 in the following clock 0 since it was already recorded for the main memory 12 in the previous clock 8 of the instruction. The time period for updating the content of the microinstruction address register 32 is also shortened and does not begin in the equivalent clock 15, but two clocks later, namely at clock time 1. This time segment only comprises clocks 1 and 2, since this is the same Update is only a direct transfer by the ALU 22 without any modification (which already took place during bars 7 to 10 of the previous main memory instruction). The write instruction for the main memory 12 writes the data into the main memory 12 during the second phase, i.e. the clock 13 to 15, of the instruction.

FIG. 3 shows how the ALU 22 for the decimal arithmetic fulfills the binary equivalent function during the first 4 clock cycles and stores the intermediate transfers for each packed decimal number. Then another passage of the ALU 22 follows during a further 4 cycles (controlled by the auxiliary clock generator 64) for the correction of six in order to obtain the pure decimal result.

FIG. 4 shows how, in the case of a branch, a further 4 clock cycles are provided by the auxiliary clock generator 64 when the branch address is loaded at the clock time 7. This gives additional time for addressing the ROS 16, since the precalculated look-ahead address is changed by the previous instruction with each branch. Such branches are a conditional branch, a multi-way table branch when decoding an OP code from an emulated target language, or a branch and connection with return by restoring the original address from the local memory register 14 to the microinstruction address register 32.

In shift operations, the auxiliary clock generator 64 provides two further clock cycles for each single bit shift either in the accumulator register 34 or in the accumulator expansion register 36. 4-cycle periods can also be provided (equal to half the basic execution time of a microinstruction) for shifting the content of the two registers 34 and 36 by one position. These two registers 34 and 36 are logically linked to form a double register by having their contents run alternately through the ALU 22.

For jump operations, the basic processing time of the ALU 22 (bars 3 to 6) is checked for the same, larger or mask. The result of the test is only known at the beginning of bar 7 and a decision is then made about a jump. If there is no jump, the next addressed instruction continues without delay. However, if an instruction is skipped, the basic clock takes another pseudo-microinstruction cycle by advancing to the next microinstruction without executing the skipped microinstruction.

The unconditional branch is a very quick instruction because no conditions have to be queried and therefore there is no delay by the auxiliary clock generator 64. In addition, the 12-bit branch address is passed directly through the ALU 22 and loaded into the total register 24 at cycle time 2. From there it continues to the microinstruction address register 32 and at clock time 3 to the output buffer register 26. As a result, it is synchronized with the normal look ahead addressing of instructions.

Instruction set

The basic machine instructions are optimally developed for emulation and stored in the ROS 16. The instructions, which are often referred to as microinstructions, are also simply referred to below. The exceptions are cases in which a distinction is made between the emulated machine target instructions and the microprocessor instructions.

Common to all instructions is a parity bit in the highest bit position (bit 0) and a 3-bit operation code (bits 1 to 3). The remaining bits are divided into fields of different lengths, the type and function of which depend on the respective instruction. Since there are only 8 different opcodes, some types of instructions differ in the decoding of additional modification bits. Most instructions are up-coded and indicate many different operations, a number of which are performed in sequence. These successive operations are coordinated by a very closely developed set of time patterns, as shown in Figs. 2 to 4 are shown.

In connection with the FIGS. 2 to 4 are then described the 11 basic instruction categories.

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In the time tables, the registers are identified with the symbols as follows: <•

Symbols register

A accumulator

B extension register

T total register

P program register

U instruction address

N count register (shift counter)

M output buffer register (output bus)

I / O input / output device

E error register

I interrupt mask register

C Register for current condition code

PCC register for reserved condition code

L Local memory register

Each of these instructions can be defined by an instruction code comprising 16 bits including a parity bit. Bits 1 to 3 define the operation code and these codes are listed below together with the instruction category.

Instructions

Mnemonic

Operation code

control

CO

000

Logically write

LW

001

Logically push

LS

001

Move number logically

LM

001

Change data

MD

010

Change operand

MO

010

Get memory

FS

011

Change directly

IN THE

100

Conditional jump

JC

101

Conditional branching

BC

110

Unconditional branching

BU

111

Tax instruction

3C, the timing diagram for the control instructions is shown. Control instructions can e.g. The following operations are provided: data transfer, indirect execution, setting of the interrupt mask, setting of pages, table branching, selection of operating modes, operation on reserved condition code and current condition code, program identifier and I / O transfers.

A number of control instructions relate to interrupt processing. Such an instruction makes it possible to carry out an interruption after the completion of each microinstruction, while an interruption section is provided in the case of other instructions, in which all outstanding interruptions are accepted and switched to interruption mode. Then the interruptions are switched off until this section appears again.

Other control instructions relate to the I / O pages of the ROS 16. The 4 bit page in the ROS 16 is a page specified internally within the instruction address register 32. This page register is used as soon as it has to be branched beyond the 4K limits of the directly addressable instruction points in the ROS. The ALU 22 continuously increases up to 64K half-words of the ROS 16 beyond the 4K limits. The break switch pointers also provide full 16-bit addressing and not just the addressing of 12 bits. Therefore, full 64K complements of the instructions can be addressed.

Other control instructions control the four flag bits. These are the four lower bits of the current condition register 48 which, together with the four condition codes, form the unconnected upper byte of the count register 50. The programmer can set the flag bits for various displays and use them as switches in the subroutine. They can be stored in the LSR's 14 together with the condition codes and the lower byte of the count register 50 for interruption switching and can be restored from there.

The remaining control instructions concern the condition code. There are two levels of condition codes, each of which has 4 bits and cumulatively indicates non-zero binary carry, two's complement overflow, two's complement, and the high-value minus bit. The upper four bits in condition register 48 change with each arithmetic operation, with each logical left shift, left shift and count, multiplication and division. For other logical instructions, the registers themselves can be queried for zero or non-zero, ones or mixed ones and zeros. The reserved condition code register 42 stores the same four bits as the condition code register 48. However, the transfer and accumulation of the equivalence of the condition codes of the emulated macro language is controlled by the microprogram. The following are some examples of tax operations.

With the control operation “Load data directly” (KBUS), the data field of the instruction is loaded into the value-high bit positions of the output buffer register 26. The data bits in positions 0 to 4 of register 0 of local memory register 14 are loaded into the lower-value bit positions of output buffer register 26. Its content is written into register 0 of local storage register 14.

The control operation “Transfer LSR data to I / O device” (KLSR) provides a four-bit field for addressing registers 0 to 15 of local memory registers 14. Data from the addressed local storage register 14 is transferred to the output buffer register 26 and the output bus 20. A six-bit field of the instruction KLSR provides a device address which is loaded into the LSR output control register 40 for addressing the input / output devices 1 to 63.

The control instruction "transfer data directly to I / O device" (KLCO) loads part of the content of the output buffer register 26 with direct values from the instruction code, the rest being loaded by the zero bits of the selected local memory register 14. Data in other bit positions of the instruction code is loaded into the LSR output control register 40 for the device address. The content of the output buffer register 26 is loaded into the register 0 of the local storage register 14.

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The control operations "Set Interrupt Mask" (KILM) provides the interrupt mask bits for the interrupt mask register 44, with a one bit in an interrupt bit position turning on for the corresponding stage. A one bit in the instruction code indicates whether the interrupt mask bits are to be saved or set.

Control operations are provided to switch the page division of the read-only memory 16. KLAP has a field to designate pages 0 to 15 and KRAP designates the page in read-only memory 16. Each page represents 4096 half words.

The control operation for the table branch specifies the register or the register part whose content is to be linked exclusively or to the content of the microinstruction address register 32 or to be linked to the next address in the ROS 16 for execution. These instructions are listed below.

Mnemonic

Adders to IAR 32

KIAL

Accumulator register 34 lower byte

KIXL

Expansion register 36 lower byte

KIBL

Output buffer register 26 lower byte

KIEL

Input bus 10 lower bytes

KIAH

Accumulator register 34 lower hex.

KIXH

Extension register 36 lower hex.

KIBH

Output buffer register 26 lower hex.

KIEH

Input manifold 10 bottom hex.

KIAZ

Accumulator register 34 lower zone

KIXZ

Extension register 36 lower zone

KIBZ

Output buffer register 26 lower zone

NEIGHBOURHOOD

Input manifold 10 lower zone

KIAS

Accumulator register 34 lower six bits

KIXS

Expansion register 36 lower six bits

KIBS

Output buffer register 26 lower six bits

GRAVEL

Input bus 10 lower six bits

With the control operations output branch (KILB), the content of the instruction address register 32 is transferred to the local memory register 14 for the current interrupt, the current interrupt is put on hold, a new interrupt is queried and the content of the location for the new interrupt level in the local memory register 14 is transferred to the microinstruction address. Register 32 transferred.

The control operation KSIE supplies three 2-bit fields (II, EE and SS) and thus specifies the interrupt code (switching on an interruption or querying the interruption and then switching off further interruptions), the error mode and the byte address in the main memory 12 (no change; Reset or byte set mode).

The code 01 in one or more interrupt codes (II), in fault operation (EE) and in the main memory byte address fields (SS) of the KSIE control operation are reserved for specifying additional control operations in which the characteristic for the interrupt code operation, the fault operation or the main memory byte address mode of the

KSIE control instruction saved or replaced according to the table below. When the control code is II or EE or SS, the KSIE control instruction defines the operations indicated by the interrupt code operation, the 5 error operation, or the main memory byte address operation.

10 -

Mnemonic

Instructions code field

description

KPIE

IIEE01

Deferred reserved condition code (no overflow)

15

KPSI

HOISS

Deferred reserved condition code (all)

20th

KCSE

01EESS

OR code for current condition for the reserved condition code and reset of current 'condition codes

25th

KTPI

II0101

Resetting the current condition code and the reserved condition code (no overflow)

30th

KCPS

0101SS

Transfer the current condition code to the reserved condition code and reset the current condition code

35

KCPE

01EE01

Transfer the current condition code to the reserved condition code (except OR overflow) and reset the current condition code.

40

The control operation KNTC takes over the function of

KTPI. In addition, the controls are set to perform a KCSE function after the next instruction if it is an arithmetic operation. The 45 mark 4 is also reset to even in the result or to odd. The control instruction KPCC takes over a direct transfer of the reserved condition code into the current condition code. The control instruction KSCC specifies whether the content of the current condition code register 48 can be saved or is to be set and specifies the positions to be saved or set: carry-over, overflow, minus, cumulative, non-zero or flags 1 to 4.

55 main memory instructions

The instructions "Logical Write" (LW) and "Memory Retrieval" (FS) form the group of main memory instructions. With these instructions, data can be read from main memory 12 and set in four internal 60 data registers, accumulator register 34, accumulator expansion register 36, count register 50 and output buffer register 26.

Data retrieved from the main memory 12 is addressed via the accumulator expansion register 36 or one of the Io-65 cal memory register 14, as indicated in the instruction address. The address can be updated at the beginning with an increase or a decrease so that it is a continuously moving pointer

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to main memory 12 on output bus 20, or it can be generated at an effective address by adding the positive or negative relative address in count register 50 to a specified pointer.

Half-word or byte addressing can be specified for the storage instructions. Since the instructions are not always aligned with half-word boundaries, in the microcomputer according to the invention, for easier emulation, the half-word alignment by rotating the data from the main memory 12 in the ALU 22 is provided in such a way that each byte is aligned in one position, so that e.g. the instruction operation code always appears in the lower byte.

Instruction "Logical writing"

As has already been said, there is no direct data path from the CPU 9 to the main memory 12 because the output bus 20 is used as an address bus for the main memory 12 and is therefore not available for data. The input bus 10 is bidirectional only with respect to the main memory 12. With regard to the CPU 9, it is not bidirectional because space has to be saved on the chip. The output drivers with which data are to be put on the bus 10 require a lot of space and electrical power and are therefore not integrated on the chip.

The four "logical write" instructions effect half-word selection, lower or high byte operation and store in the main memory 12 data which come from an addressed location in the local memory registers 14 or from an I / O device.

“.Logical writing” from LSR

In the first logical write instruction, data is written from the local memory register 14, location 1 into the main memory 12 to the location which is addressed by one of the positions 0 to 63 of the local memory register 14. One of registers 1 through 63 in LSR 14 is selected and the content incremented or decremented or left unchanged before the output buffer register 26 is set to address main memory 12. The updated address is written back into the above-selected position 1 to 63 of the local memory register 14. If the position 0 in the local memory register 14 is specified as the address source, the count register 50 is thereby selected as the indirect address of the local memory register 14, which is used as the source for the address of the main memory 12. A memory write cycle is performed on the data received from the local memory register 14, position 1, which has been applied to the input bus 10. As an option, the address change code (2 bits of the OP code) can be placed on the input bus 10 and then it selects only the high or only the low byte for writing to the main memory 12. If a control instruction previously activated the byte memory addressing mode, all positive or negative address updates act as plus or minus 2. The selection of the high byte forces an address update of - 1 (the low byte does not change the address) and the resulting address stores the high or low byte even or odd. In addition, the original content of the output buffer register 26 is selected from position 0 of the local memory register 14.

Logical writing of LSR 0 to 63 addressed via expansion register 36

This second instruction differs from the first one in that the ones to be written into the main memory 12

Data from a selected local memory register 14 (position 0 to 63) the memory address for the main memory 12 come from the accumulator expansion register 36. The high or low byte operations described above are also available.

Logical writing of I / O device 0 to 63 addressed by the same LSR 0 to 63

The third instruction differs from the first logical write instruction only in that the same code of the LSR 14 (0 to 63) that selects the address register also selects the I / O device (0 to 63) that stores the data in the main memory 12 data to be written to the input bus 10 there.

Logical writing of I / O devices 1 to 63 addressed by accumulator expansion register 36

The fourth instruction differs from the second described above only in that the data to be written into the main memory 12 is supplied from the selected I / O device (1 to 63) to the input bus 10.

Memory retrieval

The memory fetch instructions (FS) are designed for half-word operation. How the half-word addressing is replaced by the memory byte addressing is described in the control instructions (current condition 48 + number 50 or interrupt mask 44 + error 46 are always used together in byte mode and the upper byte is not zeroed in the case of a memory recall command).

Loading memory into registers of CPU 9 with address LSR 14 (half-word address mode)

One of the registers 1 to 63 from the local memory registers 14 is selected and the content is changed by 0 ± 1 or OR 1 before the content of the output buffer register 26 (not LSR 14, position 0) is set in the address of the main memory 12. If the change was ± 1, the content of the output buffer register 26 in the selected register in the LSR 14 is updated. The main memory 12 is then read out in one cycle and the data is selectively fed via the input bus 10 into the accumulator register 34, the accumulator extension register 36, the output buffer register 26 or the counter register 50 / error register 46. The interrupt mask register 44 and the error register 46 can be selected by the KSIE control instructions instead of the condition register 48 and the count register 50. (The count register 50 / error register 46 has only the lower byte). The position 0 in the LSR's 14 selects the indirect addressing of the LSR 14 from the operand of the lower six bits in the count register 50. In addition, the original data from the output buffer register 26 is selected from the position 0 of the LSR 14.

With BUS operand address (half-word addressing)

This instruction differs from that described below in that the output buffer register 26 (ie position 0 in the LSR 14) is used instead of the accumulator extension register 36 and the additional address transfer on the output bus 20 as a half-word movement of the content of the output buffer register 26 into positions 1 to 63 of the LSR 14 or the address update on the output bus 20 in position 0 of the LSR 14 acts.

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With XTN operand address (half-word addressing)

The content of the accumulator expansion register 36 is changed by 0, ± 1 or addition of the relative operand address in the count register 50 before the content of the output buffer register 26 (not LSR 0) addresses the main memory 12. The updated value of the output buffer register 26 is written back into the accumulator expansion register 36. A read cycle for main memory 12 is then started. Before the data from the main memory 12 is available, an additional transfer is made, provided that the choice of the LSR is between 1 and 63 and is not 0. The content of the microinstruction address register 32 is written into the selected LSR 14. Finally, the data from the main memory 12 is switched to the input bus 10 in order to be placed in the accumulator register 34, the accumulator extension register 36, the output buffer register 26 or the count register 50 / error register 46, as in the first FS instruction. The original data from the output buffer register 26 are also selected from position 0 in the LSR 14.

Load from memory into I / O devices (half-word addressing)

This instruction differs from the above in that the microinstruction address register 32 can be selected from the accumulator extension register 36 or from the location in the LSR 14 that is the same as the selected and updated input / output device. The main memory data is placed in the output buffer register 26 (not LSR 0) and from there sent to the selected input / output device (1 to 63) with an output request pulse and no further transfers take place. The device 0 selects the indirect addressing of the device from the lower six bits in the count register 50. The original data in the output buffer register 26 are also selected from position 0 in the LSR 14.

Arithmetic and logical instructions

As shown in FIG. 3, the instructions “modify data” (MD) and “modify operand” (MO) belong to the arithmetic and logical instructions. The arithmetic instructions include «addition with and without carry» and «subtraction». They can be executed in two's complement form or in decimal packed form (unsigned single-digit in hex. 4 data bits each). The arithmetic functions can be carried out in the microprocessor between the internal registers (accumulator register 34, accumulator extension register 36, count register 50 and output buffer register 26). In addition, the accumulator register 34 or the accumulator extension register 36 can be combined arithmetically with one of the 64 local memory registers 14. so that the result can be stored in one of the local storage registers 14 or in the accumulator expansion register 36. All arithmetic instructions executed in the registers of the processor 9 can be in half word mode, on the upper bytes, the lower bytes, alone or on the lower 4 hex. Bits are executed. The other bits remain unchanged in every configuration.

The logical instructions include «AND», «OR» and «Exclusive-OR». If these operations are carried out on the internal registers alone, as in arithmetic mode, they can be entered in hex. lower 4 bits, the lower byte, the high byte or in half-word mode. Similar functions can also be performed with the local memory registers 14. All of these logical functions from the outside in or inside out, however, can only be carried out in half-word mode.

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Modify data

With the “Modify data” command, the content of the accumulator register 34 or the accumulator extension register 36 can be modified in its place with the content of the local storage register 14, which remains unchanged. A specified local storage register 14 can also be changed with the content of the accumulator expansion register 36, the content of the accumulator expansion register 36 remaining unchanged and the result 15 can be placed in the selected local storage register 14. In addition, each input / output device can be selected for the delivery of data to the input bus 10. This data can be modified 20 with the data in the accumulator expansion register 36 and the result returned to the same input / output device by putting the data in the output buffer register 26 (not LSR 0) and from there onto the output bus 20 and in position 0 of the local memory register 14. When the address portion of the modified 25 data instruction is set to 0, zero data is produced on the input bus 10. With the OR function, a shift is made from the accumulator extension register 36 into the output buffer register 26 and with the AND function the content of the output buffer register 26 is set to all zeros.

The following modification functions can be specified by the instruction "Modify data": add binary with or without carry or decimal packed with carry, subtract binary or decimal packed with borrow (35 cannot be subtracted from a selected local memory register 14 or an input / output device, except vice versa), AND, OR and exclusive-OR. If position 0 is specified in the local memory register 14, the indirect addressing of the local memory register 40 14 or of the input / output device is selected from the lower six bits of the count register 50.

Modify operand 45 With the instructions “Modify operand” (MO), the content of the accumulator register 34 with the content of the accumulator extension register 36 or the content of the accumulator extension register 36 can be modified with the content of the accumulator register 34, which remains unchanged. The content of the accumulator register 34 or the accumulator expansion register 36 can also be modified with the content of the output buffer register 26. If the content of the accumulator expansion register 36 is zero, an OR function 55 with LSR 14, position 0, (output buffer register 26) causes the contents of the output buffer register 26 to move into the accumulator expansion register 36 and in LSR 14, positions 1 to 15 triggered. The modification functions differ from those of the instructions for modifying 60 data (MD) in that additional movement functions are provided between each combination of the contents of the accumulator register 34, the accumulator expansion register 36, the count register 50 and the error register 46 and not from the count register 50 / Error register 46 can be subtracted 65, except in reverse. All of the above functions can be used in half-word mode, only with the high byte, only with the low byte or only with the hex. Digit, unless the high byte of the count

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registers 50 / error register 46 does not exist. After completion of each of the above functions, a half-word auxiliary result (high byte of the count register 50 / error register 46 = current condition register 48 / interrupt mask register 44) can be shifted into a selected position 1 to 15 of the LSR 14.

Logical shift

4 shows that the shifting operations can be carried out bitwise to the left or right. The length of the shift depends on the length of the register. The contents of the accumulator register 34 and its expansion register 36 can each be shifted between one and 16 positions. For multiplication and division, where double precision is required, the accumulator register 34 becomes the high value register of the accumulator extension register 36 and together they form a coupled 32-bit register, the contents of which are shifted between one and thirty-two positions in one of the following ways can be. The types are: arithmetic right shift, left shift and count, logical left shift, logical right shift, left shift and rotation and right shift and rotation. Faster operations equivalent to rotating 8 positions of the 16-bit registers, also called byte rotations, can be performed in a microinstruction cycle.

Direct modification

The direct modification (IM) instructions are shown in Figure 3C.

A data byte from the program register 30 (OP bits 8 to 15) is combined with the lower byte in the accumulator register 34, in the accumulator expansion register 36 or in the count register 50 / error register 46, which were selected by an earlier KSIE control instruction. For the accumulator register 34 or its expansion register 36, the combining functions are subtract, load, OR, AND, XOR and ADD. Any carry or borrower generated by an addition or subtraction is forwarded to the high value byte. For the count register 50 / error register 46, the combining functions are OR, AND, load ADD. For the functions add or subtract, the direct byte data is increased or decreased by one and incoming transfers with a new condition code set are ignored.

Conditional jump

As shown in Fig. 4B, the jump instruction is executed when a test is wrong. The checks carried out against a mask byte in the instruction on the lower 8 bits of a selected register are as follows: mask = lower byte, mask larger than lower byte, mask bits are checked for activated bits in the lower byte and other unselected bits are ignored or the mask is checked for the switched off bits in the lower byte and the remaining bits are ignored. The condition register 48 can be checked with selection on / off bits and a voltage or a combination of conditions. The condition register 48 has four condition codes and four program-controlled marker bits. If the test is wrong, the next instruction is skipped. The high numbers of the hex. Zones in the accumulator register 34 or the accumulator extension register .36 can also be checked for all zeros.

Branch operations

Branch operations include conditional and unconditional branching. They can be made for any 4K area of the read-only memory 16. If the contents of the microinstruction address register 32 + 1 are stored in one of the local storage registers 14 before an unconditional branch, a branch and connect operation is performed. Conversely, if one takes the address thus stored in the local memory registers 14 and resets this address pointer into the microinstruction address register 32, one returns to the subroutine from which the branching and connection originally started.

A second set of branch instructions include the multiple table branch. This can be based on the lower four hex. Bits in processor registers, on the next four zone bits ignoring the four or six lower bits, or on all eight bits. This gives a branch with 256 branches to a complete table, from which an eight-bit OP code can be decoded from the table by an unconditional branch instruction.

A third group of branch instructions provides the predetermined relative address branch under sixteen different conditions such as register 0 or not 0, register negative or non-negative. The branching with relative addresses takes place by taking the eight-bit relative address from the instruction and adding it to the content of the microinstruction address register 32 as a predetermined sixteen-bit number.

Other instructions allow the relative address branching to be branched based on the increment of the contents of the count register 50 by 1 or 16. If the result contains all zeros or not all zeros, if the four least significant bits are all zero or not zero if the four least significant ones Bits are all 1 or not all 1 if the four high bits are all 1 or not all 1, etc.

Logical movement of numbers

The logical move number (LM) instructions shown in Fig. 3B selectively move the contents of a specified register 1 through 63 in the local memory registers 14 into the microinstruction address register 32, the accumulator register 34, the accumulator expansion register 36, or the combined registers for the current condition 48 and the count register 50. During these transfers, the value can be changed by 0, -1 or +1 (movements of single bytes into the accumulator register 34 or the accumulator expansion register 36 excluded). The value modified in this way is written back into the selected registers 1 to 63 of the local memory register 14. Conversely, the content of a specified register (microinstruction address register 32, accumulator register 34, accumulator extension register 36 or condition register 48 and count register 50 combined can be moved into a selected position 1 to 63 of the local storage register 14 with a modification by 0, +1 or - 1 ( Movement of individual data bytes from the accumulator register 34 or the accumulator expansion register 36 is excluded. The byte shifts can indicate either the high or the low byte in the accumulator register 34 or the accumulator expansion register 36. When moving between these two registers and the specified register in the local ones No modification is made to memory registers 14. The value of microinstruction address register 32 consists of a sixteen bit address for read-only memory 16. Condition register 48 can only be used as the upper byte of combina5

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tion of the condition register 48 can be selected with the count register 50 if no increase or decrease is specified. Interrupt mask register 44 and error register 46 are also chosen to replace condition register 48 and count register 50 when turned on by a KSIE control instruction previously described. If the instruction for the logical number shift specifies the position 0 in the local memory registers 14, the indirect addressing of the local memory registers 14 is selected from the lower six bits of the count register 50. The exception is the selection of the condition register 48 and the count register 50 as the destination for the source register for the movement operation with which data is moved from or to these two registers from or to the position 0 of the local storage register 14.

Input / output

There is no direct input / output instruction as such. Direct program-controlled data transfers or control messages from or to an I / O device are performed by the memory fetch, memory write, modify data and executed by control instructions.

The memory fetch instruction transfers data from main memory 12 to an I / O device via the internal highway of bus 23, 25, 28. The logical write instruction transfers data directly from an I / O device to main memory 12 via input bus 10 without these run through the processor 9. The 5 address of accumulator extension register 36 or one of the LSR 14 is used. The instruction for data modification brings data from an I / O device, has the ALU 22 process the data with the operand in the accumulator extension register 36 and returns the result to the I / O device via the io output buffer register 26. With a control instruction, data can be output to a device either from a specified LSR 14 (0 to 15) or from a direct data field in the instruction. Other control instructions may transfer data from a 15 I / O device to the accumulator register 34, the accumulator expansion register 36 or one of the registers 0 to 15 in the LSR 14.

In any case, the device address, either specified directly in the address field by the instruction or indirectly 20 as the content of the count register 50, is transmitted to the I / O device via the address bus 21 and the output line 41, which are also used for addressing the LSR 14 . The transmission is synchronized by two exchange signals. These signals, together with the hold-25 clock input signal, allow the I / O transfers to operate asynchronously, regardless of the line length and the operating delays of the device.

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Claims (10)

623946 1. Microprocessor arrangement with a semiconductor chip on which an arithmetic unit, associated operand registers, an instruction decoding and execution circuit, and input and output circuits are arranged, and with connecting lines to a main memory, to registers and to input / output devices, in The following I / O devices, which are arranged outside the semiconductor chip, as well as with a bus system that connects the above-mentioned units and a clock and time control for timing the operations in progress, characterized in that a unidirectional one on the semiconductor chip (9) , i.e. bus line (23, 25, 28) transmitting in only one direction from the arithmetic logic unit (22) via a total register (24) to an output buffer register (26), that a micro-instruction address register (32) is also connected to this bus line in turn via an output line (29) for address modification or for branching and Connection operations with the arithmetic unit (22) is directly connected, that additional registers (34, 36, 44,46, 48, 50) are connected to said bus, under the control of an instruction decoder (62) which is connected via an input line ( 33) is fed by a program register (30), data or command signals are input into said registers, that in addition a multiplexed common call line (53) for cycle assignments and interrupt requests is connected to a priority encoder (54), and that control lines ( 15) are connected to drivers (18) for selecting the source or the destination for transmissions on input bus lines (10) and output bus lines (20) connected to the bus line, and also that an address bus line (41) on the one hand with an output control register (40) and on the other hand is connected to the drivers (18) in order to local memory registers located outside the semiconductor chip directly (14) or I / O devices. 2. Microprocessor arrangement according to claim 1, characterized in that the output bus (20) addresses a control memory (16) serving as a control memory and the main memory (12), which are arranged outside the semiconductor chip (9), and data to the E / A devices and the local memory register (14) delivers, while the input bus (10) data, addresses and instructions from the main memory (12) or the I / O devices and local memory registers (14) to functional units on the semiconductor chip (9) and outputs data from the I / O devices and the local memory registers (14) to the main memory (12). 2nd PATENT CLAIMS 3. Microprocessor arrangement according to claim 1 or 2, characterized in that the clock and time control defines a two-part execution cycle for the instructions for the purpose of overlapping operation, with part of the read-only memory (16) used as control memory having an address on the Output bus (20) is addressed and during the other part data is sent via this output bus (20) to the local storage register (14) or to the I / O devices. A microprocessor arrangement according to claim 1 or 2, characterized in that the execution of a second instruction begins during a first part of an instruction execution cycle and during a second part of this instruction execution cycle data is given to the output bus (20) are transmitted to an I / O device and / or a local memory register (14) which is addressed by an address auxiliary line. 5. Microprocessor arrangement according to claim 1 or 2, characterized in that the local memory registers (14) store data at a reserved address that appears on the output bus (20) during each instruction execution cycle to selectively open it during the next instruction execution cycle to load the input manifold (10). 6. Microprocessor arrangement according to claim 1 or 2, characterized in that the drivers (18) and the clock and time control circuits (60, 64, 66) on the half io conductor chip (9) are arranged. 7. The microprocessor arrangement as claimed in claim 1 or 2, characterized in that the drivers (18) serve as the control memory (16), the main memory (12) and the local memory registers (14) and their 15 data lines (11, 13, 17) are arranged on one or more additional semiconductor chips. 8. Microprocessor arrangement according to claim 1 or 2, characterized in that the collecting line (25), which with the arithmetic unit (22) connected downstream total 20 register (24) is connected while each instruction execution cycle is loaded at least twice, once with the address of the instruction to be executed next and on the other hand with the execution results of the function specified in the instruction. 25th 9. A microprocessor arrangement according to claim 1 or 2, characterized in that data from the arithmetic logic unit (22) are temporarily stored in the downstream total register (24) and then time-controlled in the output buffer register (26), which leads to a line (10) on the input collector Operation can be performed while another is overlapping and terminating on the output manifold (20). 10. A microprocessor arrangement according to claim 1, characterized in that the following are provided as additional registers connected to the unidi-35 rectional collecting line (23, 25, 28): an accumulator register (34), an accumulator extension register (36) Error register (46), an interrupt mask register (44), a count register (50) and a register (48) for recording the current condition.