RU2108685C1 - Device compensating for difference in sensitivity of elements of matrix of photodetectors - Google Patents

Abstract

FIELD: optico-electron instrumentation, digital multichannel photometers. SUBSTANCE: device compensating for difference in sensitivity of elements of matrix of photodetectors has matrix of photodetectors 1, first matching amplifier 2, analog-to-digital converter 3, computer 4, clock pulse former 5, first and second multiplexers 6, 7, address counter 8, storage 9, digital-to-analog converter 10 and second matching amplifier 11 placed in series. At first stage of operation of device test image with uniform distribution of illumination is projected on to matrix of photodetectors 1 and identical readings of rated reference voltage of analog-to-digital converter 3 are recorded in storage 9. Signals from matrix of photodetectors 1 of test image are read into computer 4 and are recorded from computer in storage 9 in the capacity of readings of compensating reference voltage. Changing voltage which value if propositional to sensitivity of read-out element is element by element fed from output of second matching amplifier 11 to input of reference voltage of analog-to-digital converter 3 for reading of test signal with unspecified distribution of illuminance. Mentioned change of reference voltage of analog-to-digital converter 3 ensures compensation for spread of sensitivity of elements of matrix of photodetectors with minimal usage of hard ware and minimal intricacy of circuit of compensating device. EFFECT: enhanced functional reliability and efficiency. 3 dwg

Description

 The invention relates to optical-electronic instrumentation and can be used in digital multi-channel photometers to compensate for differences in the sensitivity of the elements of the matrix of photodetectors.

 A device for compensating for the heterogeneity of the sensitivity of the elements of the matrix of photodetectors [1], comprising a memory block of samples of sensitivity, a microprocessor, a memory block of samples of inverted sensitivity and a digital multiplier. However, the known device is characterized by high complexity of the circuit and high hardware costs.

 Of the known technical solutions, the closest in technical essence to the claimed object is a device for compensating for differences in the sensitivity of the elements of the photodetector array [2], containing a clock shaper connected to the photodetector matrix, the output of which is connected to the first inputs of the summing amplifier and digital-to-analog converter (DAC) , the second (digital) input of the DAC is connected to the output of the switch, and its output is connected to the second input of the summing amplifier. The output of the summing amplifier is connected to the first input of the comparator, the second input of which is connected to the output of the reference voltage source, and the output is connected to the input of the logic unit. The output of the logical unit is connected to the input of the memory unit and the first input of the switch, the second input of which is connected to the output of the memory unit.

 The specified device is characterized by high complexity and limited functionality, since on the one hand it includes a logical device that generates digital samples, the value of which is inversely proportional to the signal of the standard background. At the same time, the essence of the logical block is not disclosed in the description, which requires inventive creativity when creating it. On the other hand, as a result of sensitivity compensation, an analog signal is generated at the output of the device, which, when using the device in modern digital multi-channel photometers based on photodetector arrays, must be additionally converted to digital form.

 The essence of the invention lies in the fact that eliminating the ambiguity of the circuit and expanding the functionality in a compensation device containing an array of photodetectors, a matching amplifier, a pulse shaper (PTI), a memory unit and a digital-to-analog converter (DAC), an analog-to-digital converter (ADC) is introduced according to the invention ) with the input of the reference voltage, a computing device, the first and second multiplexers, an address counter and a second matching amplifier, while the phase inputs of the photodetector matrix receivers are connected to the outputs of the same name of the clock pulse generator, the input of the horizontal read pulse is combined with the first clock input of the computing device and the first input of the second multiplexer and connected to the output of the horizontal read pulse of the Physicotechnical Institute, and the signal output of the photodetector array is connected to the ADC input by the first matching amplifier, the input the start of conversion of which is connected to the first clock output of the Physicotechnical Institute, and the information outputs and the output of the end of the conversion are connected respectively but to the information inputs and the second clock input of the computing device, the first and second clock outputs of which are connected in the order of listing with the second inputs of the first and second multiplexers, respectively, the control output is connected to the inputs of the same multiplexers of the same name and the recording block input, and the information outputs of the computing device connected to the inputs of the memory block of the same name, the first input of the first multiplexer is connected to the second clock output of the Physicotechnical Institute, and the outputs of the first and second multiplexes sors are connected respectively to the clock input and the reset input of the address counter, the outputs of which are connected to the address inputs of the memory block, the information outputs of the memory block are connected to the same inputs of the DAC, the output of which through the second matching amplifier is connected to the input of the ADC reference voltage, and the output of the computing device is the output compensation devices.

 These signs provide a solution to the problem.

 In electronics, functional elements are known that are introduced into the circuitry of the device for compensating for differences in the sensitivity of the photodetector array, however, the presence of new connections between them led to the appearance of the proposed device with respect to the prototype of a new quality - eliminating the ambiguity of the device circuitry and expanding the functionality. This quality is not the result of summing up the positive effects achieved by introducing new elements or using off-the-shelf technical solutions, and is achieved precisely due to the presence of new connections between the elements. Since among the known technical solutions there are no solutions with similar features (a set of elements and connections between them) that would solve the same problem in the same way (i.e., by applying a voltage that compensates for differences in the sensitivity of the photodetector array directly to the input of the analog voltage reference digital converter quantizing the signal of this matrix), the claimed technical solution meets the criterion of "novelty."

 In FIG. 1 shows a functional diagram of a compensation device; in FIG. 2 - a possible circuit of the pulse shaper; in FIG. 3 is a possible diagram of a computing device.

 The proposed compensation device (Fig. 1) contains a matrix of photodetectors 1, a first matching amplifier 2, an analog-to-digital converter 3, a computing device 4, a pulse shaper 5, the first and second multiplexers 6, 7, an address counter 8, a memory unit 9, digital-to-analog the converter 10 and the second matching amplifier 11. In this case, the phase inputs 12 of the photodetector array 1 are connected to the same outputs of the pulse shaper 5, the input of the horizontal read pulse 13 is combined with the first clock input of the subtractor an expansion device 4, the first input of the second multiplexer 7 and is connected to the output of the horizontal pulse reading the Physicotechnical Institute 5. The output of the photodetector array 1 through the first matching amplifier 2 is connected to the signal input of the ADC 3, the conversion start input of which is connected to the first clock output 14 of the Physicotechnical Institute 5, and information the outputs and the output of the conversion end are connected respectively to the information inputs 16 and the second clock input 17 of the computing device 4. The first and second 20, 21 clock outputs of the computing device 4 are listed in the order of transfer to the second inputs of the first and second multiplexers 6, 7. respectively. The control output 19 is connected to the inputs of the first and second multiplexers 6, 7 and the recording input of the memory unit 9, and the information outputs 18 are connected to the inputs of the same unit. The first input of the first multiplexer 6 is connected to the second clock output 15 of the Physicotechnical Institute 5, and the outputs of the first and second multiplexers 6, 7 are connected respectively to the clock input and reset input of the address counter 8. The outputs of the address counter 8 are connected to the address inputs of the memory unit 9, the information outputs of which connected to the same inputs of the DAC 10. The output of the DAC 10 through the second matching amplifier 11 is connected to the input of the reference voltage of the ADC 3.

 Possible element base of the compensation device: photodetector array 1 - FUK1L2 with the number of elements 1024 [3], ADC 3 - K1108PV2 [4], conversion time 2 μs, number of bits 12, possible range of reference voltage change 2 - 4 V, multiplexers 6, 7 - K555KP11, address counter 8 - K555IE10, memory block 9 - K537RU10 with a capacity of 2K bytes, DAC 10 - K1108PA1 [4], conversion time - 0.4 μs, the number of bits - 12, matching amplifiers 2 and 11 can be based on operating amplifiers type K544UD2. A pulse shaper 5, a possible circuit of which is shown in FIG. 2 may be performed using 555 or 561 series logic circuits.

The photodetector array 1 contains a set of elements whose signal linearly depends on the exposure value, however, the coefficient of this dependence is individual for each element
U _i = S _i • H _i (1)
Where
U _i - the signal value of the i-th element;
S _i - sensitivity of the i-th element;
H _i - exposure of the i-th element.

 In this case, the spread in the sensitivity of elements relative to the average level is 5–10% according to the developers [4].

где
U вх., U оп.1 - величина входного и опорного напряжения АЦП;
N м. 1, N вых. - максимальный и текущий выходной код АЦП;
K1 - коэффициент пропорциональности.The ADC 3 when applied to the start input of the clock pulse generates a code output proportional to the value of the input voltage

Where
U input., U op.1 - the value of the input and reference voltage of the ADC;
N m. 1, N out. - maximum and current ADC output code;
K1 is the coefficient of proportionality.

,
где
U вых., U оп.2 - величина выходного и опорного напряжения ЦАП;
N м.2, N вх. - максимальный и текущий входной код ЦАП;
K2 - коэффициент пропорциональности.DAC 10 generates an output voltage proportional to the input code

,
Where
U o., U op.2 - the value of the output and reference voltage of the DAC;
N m. 2, N input. - maximum and current input DAC code;
K2 is the coefficient of proportionality.

 A possible circuit of the pulse shaper 5 for the array of photodiode elements is shown in FIG. 2 and includes a master oscillator 22, a counter 23 and a clock pulse decoder 24, a line read pulse generator assembled on the basis of the counter 25 and trigger 27, as well as a phase pulse generator - the least significant bit of the counter 26 and the inverter 26.

 A possible implementation diagram of a VU 4 based on a DVK-3 microcomputer is shown in FIG. 3 (typical computer blocks — processor, standard peripheral boards and devices in FIG. 3 are not shown). The structure of WU 4 includes bus transceivers 20, decoders of control signals of output and input 29, 30, a register of control signals 31, triggers for generating a write pulse 32, 34, a multiplexer of control signals 36, address counter 37, buffer RAM 38, and logic elements 33, 35 . The outputs of the bus transceivers 28 are connected to the inputs of the decoders 29, 30 and the register 31 of the control signals and at the same time are the information inputs 18 of the VU 4. The decoder 29 generates a pulse for writing information to the register 31, pulse J1 for resetting the address counter ka and clock pulses at the outputs 20, 21 of the VU 4. The decoder 30 generates a pulse to read the status of the RAM flag from the output of the trigger 34 and a pulse J2 to read data from the RAM 38. The register 31 is used to generate a control signal to enable data writing to the RAM 38 and a control signal to the output of 19 VU 4. Triggers 32, 34 together with the AND-NOT 33 element are used to generate a pulse of information recording in RAM 38 when there is a permission signal from the output of register 31 and when a read-only horizontal pulse arrives at the first clock input 13 of VU 4. Address counter 37 cl It is used to form a fluid address of a recorded or readout signal count and a counter overflow signal. Element base of VU 4: K589AP26 - bus transceivers 28, K537RU10 - RAM 38, all other elements can be made on the basis of functional devices that are part of 555 series chips.

 Thus, the elements included in the compensation device do not require inventive creativity, because all of them are manufactured by industry in the form of ready-made microcircuits or are formed from them using standard circuitry solutions in accordance with the functional purpose of the elements and a description of the operation of the device.

 A device for compensating for differences in the sensitivity of the elements of the matrix of photodetectors works as follows.

где
S макс., S мин. - диапазон изменения чувствительности элементов;
N ном. - величина отсчета сигнала.At the first stage of operation of the compensation device, the formation and recording in the memory unit 9 of the compensating bias voltage samples is performed. To form such samples, a test image with a uniform distribution of illumination is projected onto the photodetector array 1, and a constant reference voltage equal to the nominal reference voltage of the ADC 3 is generated at the output of the second matching amplifier 11. To generate a given reference voltage, the same signal samples are recorded in the memory unit 9. The value of the samples to minimize the deviation of the reference voltage from the nominal value during the subsequent compensation at the first stage is selected based on the ratio between the average and maximum sensitivity level of the elements of the photodetector array

Where
S max., S min. - the range of variation of the sensitivity of the elements;
N nom. - the value of the signal reference.

 In order to minimize the compensation error, the exposure level of the test image is adjusted so that the maximum signal level of the photodetector array is close to the upper level of the input voltage of the ADC 3.

 To record test or compensation readings in the memory unit 9 of the VU 4 using the register 31 (Fig. 3) by generating a low level voltage at the control output 19, the memory unit 9 (Fig. 1) is put into recording mode, and the multiplexers 6, 7 are in control mode from the VU 4. The reference voltage samples are recorded in the memory unit 9 by the information outputs 18 of the VU 4 by applying to the input of the address counter 8 through the first multiplexer 6 pulses from the first output of the clock pulses 20 of the VU 4. The number of clock pulses is equal to the number of matrix elements photo reception emnikov 1. Previously, the address counter 8 is set to the initial state by a pulse from the second clock output 21 of the VU 4 passing through the second multiplexer 7. After the interval of recording voltage samples in the memory unit 9, it is allowed to read the signal from the array of photodetectors 1 and write its samples to RAM 38 WU 4.

 In the initial state, the trigger 32 WU 4 low-level signals from the output of the register 31 is set to zero. To enable recording with a high level of signal from the first output of the register 31, the trigger 32 of the VU 4 is released. The first incoming pulse from the first clock input 13 of the VU 4, the trigger 32 is switched to a single state and this element 2I-NOT 33 is allowed to pass to the trigger reset input 34. Setting the trigger 34 to zero puts the RAM 38 in recording mode, and the multiplexer 36 switches to transmitting signals from the second inputs. At the same time, the pulse from the output of the 2I-NOT 33 element passing through the multiplexer 36, the address counter 37 is set to zero. The pulses arriving after this to the second clock input 17 from the output of the end of the ADC conversion 3 are transmitted to the clock input of the address counter 37 and to the input of the RAM sample 38. The pulse supply to these elements provides a record of the signal samples arriving at the information inputs 16 into sequentially addressed RAM cells 38. After recording the number of samples equal to the number of elements of the photodetector array 1, an impulse is generated at the output of the address counter 37 overflow, setting the trigger 34 to a single state. In this case, the RAM 38 switches to storage mode, and the multiplexer 36 - to transmit signals from the first inputs. The change in the state of the trigger 34 is determined by the computer, which is part of the VU 4, using the software polling the input of the element 2I 35. After detecting a change in the state of the trigger 34, the computer VU 4 reads the signal. Before reading by the pulse J1, the address counter 37 is set to its initial state. Reading samples from RAM 38 is carried out using pulses J2.

где
U вх.о_i, U оп.1_i - уровни входного и опорного напряжений i-го элемента.The test image signal is read in WU 4 and recorded from WU 4 in the memory unit 9 as described above. Thus, at the end of the first stage of operation of the compensation device, in the memory unit 9 there will be signal samples determined in accordance with expression (2) with U op.1 = U opn. These readings will be compensating coefficients at the second stage of the compensation device during registration of images with an arbitrary distribution of illumination. When reading the signals of such images, the input of the ADC reference voltage from the output of the second matching amplifier 11 will be supplied with an element-wise varying voltage, the value of which is determined in accordance with the process of generating compensating samples of the reference voltage described above by substituting the reference value at the ADC output calculated by the formula (2) , into expression (3)

Where
U input about _i , U op.1 _i - input and reference voltage levels of the i-th element.

зависящие, как это следует из выражения (1), только от отношения экспозиций регистрируемого и тестового изображений. Таким образом, влияние различий в чувствительности элементов матрицы фотоприемников оказывается скомпенсированным и не вносит вклада в погрешность оценки уровня их освещенности.When applying to the signal input of the ADC 3 voltages U I. _i from the image with an arbitrary distribution of illumination, codes will be generated at its output

depending, as follows from expression (1), only on the ratio of the exposures of the recorded and test images. Thus, the effect of differences in the sensitivity of the elements of the photodetector array is compensated and does not contribute to the error in estimating the level of their illumination.

Таким образом, из описания работы устройства компенсации различий в чувствительности элементов матрицы фотоприемников следует, что поставленная при разработке этого устройства задача устранения неоднозначности схемы и расширения функциональных возможностей решена в нем за счет введения новых устройств и установления новых связей между ними. Так, в частности, введение аналого-цифрового преобразователя 3 с входом опорного напряжения позволило обеспечить как цифровое представление скомпенсированного сигнала, так и выполнение самой процедуры компенсации за счет изменения опорного напряжения во время считывания сигналов элементов матрицы фотоприемников. Введение вычислительного устройства 4 позволило производить запись постоянных или индивидуальных для каждого элемента отсчетов опорного напряжения в блок памяти 9, а также считывание отсчетов сигнала с выхода матрицы фотоприемников. Первый и второй мультиплексоры 6, 7, а также адресный счетчик 8 введены для обеспечения записи в блок памяти 9 из ВУ 4 отсчетов опорного напряжения и считывания этих отсчетов во время считывания сигнала матрицы фотоприемников. Второй согласующий усилитель 11 введен для согласования диапазонов аналогового сигнала на входе АЦП 3 и скомпенсированного цифрового сигнала на его выходе.The matching of the ranges of the input voltage and the output corrected code is provided by the choice of the value U op.2 and K2. It is advisable to choose the level U op.2 to reduce the influence of internal noise of the DAC 10 sufficiently large, while the coefficient K2, which depends on the transmission coefficient of the matching amplifier 11, can be calculated on the basis of the condition that the output of the ADC 3 is constant when the test image is compensated when U in. _i = U in.o _i . To obtain in this case an output code at the level N nom. Determined from condition (4), the coefficient K2 must have the following value in accordance with expression (6)

Thus, from the description of the operation of the device for compensating for differences in the sensitivity of the elements of the photodetector matrix, it follows that the task of developing this device to eliminate the ambiguity of the circuit and expand the functionality was solved in it by introducing new devices and establishing new connections between them. Thus, in particular, the introduction of an analog-to-digital converter 3 with a reference voltage input made it possible to provide both a digital representation of the compensated signal and the compensation procedure itself by changing the reference voltage during reading signals of the photodetector array elements. The introduction of the computing device 4 made it possible to record constant or individual reference voltage samples for each element in the memory unit 9, as well as read the signal samples from the output of the photodetector array. The first and second multiplexers 6, 7, as well as the address counter 8, are introduced to ensure writing to the memory unit 9 from the VU 4 reference voltage samples and reading these samples during the reading of the signal of the photodetector array. The second matching amplifier 11 is introduced to match the ranges of the analog signal at the input of the ADC 3 and the compensated digital signal at its output.

 New in the proposed device is the relationship between the output of the second matching amplifier and the input of the ADC reference voltage, which made it possible to establish the ambiguity of the device circuit and to simplify it by eliminating the comparator, logic unit, multi-channel switch, and summing amplifier. It should be noted that the ADC and the computing device introduced into the circuit of the compensation device are an integral part of digital multi-channel photometers, which the proposed device is supposed to be used in, and therefore the actual complexity of the compensation device is limited by the introduction of multiplexers, address counter, and voltage divider.

Literature
1. Helfrich RW Programmable compensation technique for staring arrays. // Proc. SPIE vol. 178, 1979, p. 110 - 121.

 2. Copyright certificate N 907868, USSR, cl. H 04 N 5/30, H 04 N 5/20. A device for compensating for differences in the sensitivity of the elements of the matrix of photodetectors. /IN. S. Melikhov, N. Yu. Gerasenov, V.I. Trofimov. Publ. 02/23/82., Bull. N 7.

 3. Photodetector device FUK1L1, FUK1L2. Label of the manufacturer.

 4. Fedorkov B.G., Taurus V.A. DAC and ADC chips: operation, parameters. - M .: Energoatomizdat, 1990.

Claims (1)

 A device for compensating for differences in the sensitivity of elements of a photodetector array, comprising photodetector arrays, a matching amplifier, a clock driver, a memory unit and a digital-to-analog converter, characterized in that an analog-to-digital converter (ADC) with a reference voltage input, a computing unit, the first and a second multiplexer, an address counter, and a second matching amplifier, while the phase inputs of the photodetector array are connected to the outputs of the same name as the clock driver of pulses, the input of the horizontal pulse of reading the matrix of photodetectors is combined with the first clock input of the computing unit and the first input of the second multiplexer and is connected to the output of the horizontal pulse of reading of the shaper of the pulse pulses, and the signal output of the matrix of photodetectors is connected through the first matching amplifier to the signal input of the ADC, the conversion start input of which connected to the first clock output of the pulse shaper, and the information outputs and the output of the conversion end are connected respectively respectively, to the information inputs and the second clock input of the computing unit, the first and second clock outputs of which are connected in the order of listing with the second inputs of the first and second multiplexers respectively, the control output of the computing unit is connected to the control inputs of the same multiplexers and the recording input of the memory unit, and the information outputs the computing unit is connected to the inputs of the memory unit of the same name, the first input of the first multiplexer is connected to the second clock output of the clock driver pulses, and the outputs of the first and second multiplexers are connected respectively to the clock input and reset input of the address counter, the outputs of which are connected to the address inputs of the memory block, the information outputs of the memory block are connected to the same inputs of the DAC, the output of which through the second matching amplifier is connected to the input of the ADC reference voltage and the output of the computing unit is the output of the compensation device.

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