RU2102837C1 - Device for compensation of shadow signal from multiple-element photodiode receivers - Google Patents

Abstract

FIELD: optical-electronic instruments. SUBSTANCE: device has multiple- element photodiode receiver 1, first matching amplifier 2, analog-to- digital converter 3, calculation unit 4, request unit 5, first and second multiplexers 6 and 7, address counter 8, memory unit 9, digital-to- analog converter 10 and second matching amplifier 11. First stage of shadow signal compensation involves storing two bias samples E_bias.1= 0 and E_bias.2= E_bias.max/2 to memory unit 9 and reading two shadow signal arrays UT₁[I] and UT₂[I]. These values and arrays are used by calculation unit 4 for calculation of array of bias voltage samples for each element of receiver 1 providing that shadow signals at input of analog-to-digital converter 3 are greater than lower threshold of input voltage of this analog-to-digital converter by given value U_o. This calculation conforms to equation:

(1). Calculated array of samples is stored in memory unit 9, then corresponding shadow signal samples array UT₃[I] is read. Minimal level shadow signal samples array UT₃[I] and maximal level samples array UT₁[I] are used for calculation of bias voltage array E_bias.0[I] providing that average value of shadow signals of all elements of receiver 1 at output of analog-to-digital converter 3 is equal to zero. Calculation uses equation (1) using substitutions U_o= 0 and UT₂[I] = UT₃[I]. When samples array E_bias.0[I] has been stored to memory unit 9, samples of shadow signal of receiver 1 are equal. Equality of amplitudes of samples of read shadow signal is provided application of signal of alternating bias voltage during reset. Alternating constituent of bias voltage conforms to inverse function of shadow signal of receiver 1 up to scaling factor. Bias voltage level at input of first matching amplifier 2 and calculation of bias voltage using equation (1) leads to equality of constant level of shadow signal and lower threshold of analog-to-digital converter. This results in zero level of digital form of shadow signal at output of analog-to-digital converter up to error in calculation and sampling. EFFECT: increased precision of shadow signal compensation. 5 dwg

Description

 The invention relates to the field of optoelectronic instrumentation and can be used in photometers based on multi-element photodiode receivers to improve the accuracy of dark signal compensation.

 Known devices for compensating for the dark signal of multi-element photodetectors [1, 2] compensating by first storing this signal in the computer memory and then subtracting the stored signal from the total programmatically. Common disadvantages of these devices are the low compensation rate and the limited possibilities of amplifying the signal to the input of the analog-to-digital converter, associated with an increase in the level and heterogeneity of the dark signal.

 The closest in technical essence to the claimed object (prototype) is a device with dark noise compensation [3] containing a linear CCD photodetector, sequentially included matching and subtracting amplifiers, analog-to-digital converter (ADC), dark signal RAM connected to a computer, digital-to-analog a converter, the information inputs of which are connected to the RAM outputs of the same name, and the output is connected to the second input of the subtracting amplifier. Dark noise compensation is carried out in two stages. At the first stage, the dark signal of the photodetector is read and its readings are written into RAM when zero-voltage subtractive amplifier is installed at the second input. At the second stage, the total signal is read, and the voltage of the dark signal from the output of the digital-to-analog converter is supplied to the second input of the subtracting amplifier. For full use of the ADC range, the maximum signal amplitude at the input of the subtracting amplifier should exceed the upper limit of the range of the ADC input signals by the value of the maximum dark signal. Thus, the matching amplifier must have a higher gain than that which would be necessary if there were no inhomogeneity of the dark signal. With a fixed ADC range, such an increase in the gain leads to an increase in the compensation error of the dark signal, which is a disadvantage of this device.

 The essence of the invention lies in the fact that to increase the accuracy of the compensation of the dark signal of multi-element photodiode receivers in a compensation device containing a multi-element photodiode receiver (PDP) with erasure and read registers, matching amplifier, analog-to-digital converter (ADC), RAM compensation signal, address a counter and a digital-to-analog converter (DAC), according to the invention, a computing device, a polling unit, a first and second multiplexer and a second matching amplifier are introduced In this case, the PDP clock inputs are connected to the outputs of the polling unit of the same name, the input of the PDP erase line pulse is combined with the first input of the second multiplexer and connected to the output of the polling unit erase line pulse, the line input of the read pulse is combined with the first clock input of the computing device and connected to the output the horizontal pulse of reading the polling unit, and the signal output of the PDP is connected to the first input of the first matching amplifier, the second input of which is supplied with a bias voltage, the output of the first the matching amplifier is connected to the ADC signal input, the start input of which is connected to the first clock output of the polling unit, and the information outputs and the output of the conversion end are connected respectively to the information inputs and the second clock input of the computing device, the first and second outputs of the clock pulses of which are connected to the second inputs the first and second multiplexers, the control output is connected to the inputs of the same multiplexers of the same name and the RAM write input, and the information outputs are calculated The device is connected to the RAM inputs of the same name, the first input of the first multiplexer is connected to the second clock output of the polling unit, and the outputs of the first and second multiplexers are connected respectively to the clock input and reset input of the address counter, the outputs of which are connected to the address inputs of RAM, the information outputs of RAM are connected to the DAC inputs of the same name, the output of which is connected to the first input of the second matching amplifier, the initial bias voltage is applied to the second input of the second matching amplifier, and its output is connected to the input of the reference voltage bias PDP.

 These signs provide a solution to the problem.

 In electronics, functional elements are known that are introduced into the circuit of a device for compensating the dark signal of a multi-element PDF, however, the presence of new connections between them led to the appearance of the proposed device with respect to the prototype of a new quality of increasing the accuracy of compensation of the dark signal. This quality is not the result of summing up the positive effects achieved by introducing new elements or using off-the-shelf technical solutions, and is achieved precisely due to the presence of new connections between the elements. Since among the known technical solutions there are no solutions with similar features (a set of elements and connections between them) that would solve the same problem in the same way (i.e., by reading two arrays of samples of the dark PDF signal obtained by setting the initial and average from the range changing the bias voltage of all sensitive elements of the receiver, by calculating and setting individual bias values, introducing a dark signal of all elements upon repeated reading to a level close to the lower level of the range and the input signals of the ADC, the final compensation of the dark signal due to the refinement calculation of the optimal bias voltage of each element in two arrays of dark signal, one of which consists of samples of this signal aligned at the previous stage, and the second contains samples obtained when the initial bias voltage is written in RAM ), the claimed technical solution meets the criterion of "novelty."

 In FIG. 1 shows a functional diagram of a compensation device; in FIG. 2 is a functional diagram of a multi-element photodiode receiver; in FIG. 3 schematic diagrams of its sensitive element; in FIG. 4 possible block diagram of the survey; in FIG. 5 is a possible diagram of a computing device.

 The proposed compensation device (Fig. 1) contains a multi-element photodiode receiver (PDP) 1, the first matching amplifier 2, ADC 3, computing device (WU) 4, the polling unit 5, the first 6 and second 7 multiplexers, address counter 8, RAM 9, The DAC 10 and the second matching amplifier 11. In this case, the clock inputs of the PDP 1 are connected to the same outputs 12 of the polling unit 5, the input of the horizontal erase pulse of the PDP 1 is combined with the first input of the second multiplexer 7 and connected to the output 13 of the horizontal pulse erase of the polling unit 5, and the input count pulse of the PDP 1 is combined with the first clock input of the computing device and connected to the output 14 of the polling unit 5. The output of the PDP 1 is connected to the first input of the first matching amplifier 2, to the second input of which bias voltage is applied. The output of the first matching amplifier 2 is connected to the signal input of the ADC 2. The start input of the ADC 3 is connected to the first clock output 15 of the polling unit 5, and the information outputs and the output of the conversion end are connected respectively to the information inputs 18 and the second clock input 17 of the computing device 4. First 19 and the second 20 outputs of the clock pulses of the VU 4 are connected in the order of listing to the second inputs of the first and second multiplexers 6, 7, and the control output 21 of the VU 4 is connected to the inputs of the same multiplexers of the same name and the recording input and RAM 9. The first input of the first multiplexer 6 is connected to the second clock output 16 of the polling unit 5. The outputs of the first and second multiplexers 6, 7 are connected respectively to the clock input and reset input of the address counter 8, the outputs of which are connected to the address inputs of RAM 9. Information inputs DAC 10 is connected to the same outputs of RAM 9, and its output is connected to the first input of the second matching amplifier 11. An initial bias voltage is applied to the second input of the second matching amplifier 11, and its output is connected to the input of the reference voltage zheniya FDP offset 1.

 Possible element base of the compensation device: photodiode receiver FDP DD1 FUNK1L2 with the number of elements 1024 [4] ADC 3 K1108PV2 [5] conversion time 2 μs, number of bits 12, multiplexers 6, 7 K555KP11, address counter 8 K555IE10, RAM 9 K537RU10 with a capacity of 2 kbytes , DAC 10 - K1108PA1 [5] conversion time 0.4 μs, the number of bits 12, the first and second matching amplifiers 2 and 11 can be made on the basis of operational amplifiers of the type 544UD2. Interrogation unit 5, a possible circuit of which is shown in FIG. 4 may be performed using 555 or 561 series logic chips.

In FIG. 2 shows a structural diagram of the PDP 1, and in FIG. 3 is a schematic diagram of its sensitive cell. The PDP 1 contains (Fig. 2) an erase register 23 and a read register 24 of the signal, controlled by clock pulses 12 and horizontal pulses 13 of erase and read 14, as well as a set of photosensitive cells switched by these registers. When the cell is switched by the erase register (Fig. 3), the transistor UT ₁ opens and charges the capacitance of the reverse biased photodiode UD to a voltage of E _cm . After the transistor UT _{1 is} turned off, the voltage on the photodiode decreases in proportion to the illumination and the accumulation time. After the end of the accumulation interval using the read register 24, the cells are connected in series to the output of the PDP 1. In the cell circuit, this connection is made using the transistor UT ₃ when a positive voltage is applied to its input from the output of the read register 24. In the absence of illumination, the output of the PDP 1 is read dark signal which depends on the initial bias voltage of the photodiode and UD is not uniform due to the level variation of the threshold voltages of the transistors ₂ and UT thermally generated B catch photodiodes. The dependence of the dark signal on the bias voltage when the latter changes in the range of 5-8 V is linear [6] however, the parameters of this linear dependence of the slope and the initial voltage are individual for each element of the PDF 1. Thus, for the dark signals of the elements of the PDF 1, the following relation can be written
U _t. [I] K [I] • E _see [I] + U _so [I]
where U _t. [I] the dark signal of the I-th element,
U _so [I] the initial voltage of the dark signal,
E _see [I] the bias voltage of the I-th element,
K [I] the steepness of the transfer characteristic of the I-th element.

A possible implementation diagram of a VU 4 based on a DVK-3 microcomputer is shown in FIG. 5 (typical blocks of a computer processor, standard peripheral boards and devices in FIG. 5 are not shown). The structure of WU 4 includes bus transceivers 32, decoders of control input / output signals 33, 34, a register of control signals 35, triggers for generating write pulses 36, 38, a multiplexer of control signals 40, address counter 41, buffer RAM 42, and logic elements 37, 39 . The outputs of the bus transceivers 32 are connected to the inputs of the decoders 33, 34 and the register 35 of the control signals and at the same time are the information outputs 22 of the VU 4. The decoder 33 generates a pulse for writing information to the register 35, a pulse 31 for resetting the address counter Single and clock pulses at the outputs 19, 20 slave 4. The decoder 34 generates pulse RAM read state flag outputted from the flip-flop 38 and the pulse I ₂ read data from the RAM 42. The register 35 serves to generate a control signal write enable data in the RAM 42 and the control signal at the output of 21 VU 4. Triggers 36, 38 together with the AND-NOT 37 element are used to generate a pulse of information recording in RAM 42 if there is a permission signal from the output of register 35 and when a read-out horizontal pulse arrives at the first clock input of 14 VU 4. Address counter 41 s puddles to form the current address of the recorded or readout countdown signal and the counter overflow signal. Element base VU3: K589AP26 bus transceivers 32, K537RU10 RAM 42, all other elements can be made on the basis of functional devices that are part of 555 series chips.

 Thus, the elements included in the compensation device are produced by industry in the form of ready-made microcircuits or are formed from them using standard circuitry solutions in accordance with the functional purpose of the elements and a description of the operation of the device.

 The compensation device operates as follows.

Before using the compensation device after it is manufactured or equipped with a new photodiode receiver, the gain and initial bias of the first and second matching amplifiers 2, 11 are adjusted. The gain control circuits of matching amplifiers in FIG. 1 are not shown because they play a supporting role. To adjust the parameters in RAM 9 from VU 4 recorded samples corresponding to the average level of the range of variation of these samples. By adjusting the voltage U _n at the second input of the second matching amplifier 11, the bias voltage E _cm. At the output of this amplifier is displayed on the average level of the possible range of its variation, that is, in the region of 6-7 V [4] In the matching amplifier 2, the required gain is set and the level of the initial bias U _see at which the minimum value of the dark signal by a specified value exceeds the lower level of the input signals of the ADC 3. To adjust the gain of the second matching amplifier 11 in RAM 9 from WU 4 recorded samples of the maximum offset at which the readout of the dark signal at the output of the first matching amplifier 2 s Given its inverse inclusion will take the minimum values. The gain of the matching amplifier 11 is adjusted so that the maximum reference level of the dark signal of the PDP 1 does not exceed the lower level of the input signals of the ADC 3. To eliminate the sampling error of the bias voltage E, _{see the} resolution of the DAC 10 so that after the described adjustment the unit voltage the low-order bit of the ADC 3 exceeded the voltage of the unit of the low-order bit of the DAC 10, recalculated to the input of the ADC, by 2-3 times.

 To record bias voltage samples in the RAM 9 of the VU 4 using the register 35 (Fig. 5) by generating a low level voltage at the control output 21, the RAM 9 is put into the recording mode, and the multiplexers 6, 7 are in the control mode from the VU 4. The recording of bias voltage samples in RAM 9 is carried out on the information outputs 22 of the VU 4 by applying to the input of the address counter 8 through the first multiplexer 6 pulses from the first output of the clock pulses of 19 VU 4. The number of clock pulses is equal to the number of elements of the PDP 1. Pre-address counter 8 installed It is initialized by a pulse from the second clock output 20 of VU 4 passing through the second multiplexer 7. After the interval of recording voltage samples in RAM 9, the signal is read from PDP 1 and its balance is written to RAM 42 of VU 4.

 In the initial state, the trigger 36 WU 4 low-level signal from the output of the register 35 is set to zero. To enable recording of dark signal samples with a high level of signal from the first output of the register 35, the trigger 36 of the VU 4 is released. The first incoming pulse from the first clock input 14 of the VU 4, the trigger 36 is switched to a single state and allows this pulse to pass through the 2I-NOT 37 element to the input reset the trigger 38. Setting the trigger 38 to zero puts the RAM 42 in write mode, and the multiplexer 40 switches to transmitting signals from the second inputs. At the same time, the pulse from the output of the 2I-NOT 37 element passing through the multiplexer 40, the address counter 41 is set to zero. The pulses arriving after this to the second clock input 17 from the output of the ADC conversion end are transmitted to the clock input of the address counter 41 and to the input of the RAM selection 42. The supply of pulses to the above elements provides recording of the dark signal samples arriving at the information inputs 18 into sequentially addressed RAM cells 42. After recording the number of samples equal to the number of elements of the PDF 1, an impulse is generated at the output of the address counter 41 overflow, which sets the trigger 38 to a single state. When this RAM 42 is switched to storage mode, and the multiplexer for transmitting signals from the first inputs. The change in the state of the trigger 38 is determined by the computer, which is part of the VU 4, using a software survey of the input element 2I 39.

 To eliminate distortions of the input signal due to the non-synchronization of switching the control signal and the formation of the horizontal pulses of the polling unit, the described input procedure is performed twice after switching the control signal after switching. After the re-detection of a change in the state of the trigger 38, the computer WU 4 reads and processes the samples of the dark signal in accordance with the compensation algorithm. Before reading by the pulse 31, the address counter 41 is set to its initial state. Reading samples from RAM 42 is carried out using pulses 32.

где E_См.2, E_см.[I] тестовое и расчетное напряжения смещения,
UT₁[I] UT₂[I] напряжения тестовых темновых сигналов,
U₀ расчетное напряжение темнового сигнала.When considering the dark signal compensation procedure, it is necessary to take into account that the PDP 1 signal is inverted after passing through the first matching amplifier and the dark signal will decrease with an increase in the bias voltage. Thus, the minimum variable bias voltage at the output of the DAC 10 will correspond to the maximum dark signal and vice versa. At the first stage of dark signal compensation, two test samples of the bias voltage of minimum E _cm.10 and E _cm2 E _cm.max are recorded in RAM 9 _. / 2 and reading two arrays of the dark signal UT ₁ [I] and UT ₂ [I] corresponding to these samples According to the parameters of VU 4, based on the linear nature of the dependence of the dark signal on the bias voltage (1), the array of bias voltage samples of each element is calculated PDP 1, in which their dark signal at the input of the ADC 3 will by a predetermined value U ₀ exceed the lower level of the input voltage of this ADC. The calculation is carried out according to the following formula

where E _{See 2} , E _see [I] test and calculated bias voltage,
UT ₁ [I] UT ₂ [I] voltage of the test dark signals,
U _{0 is the} calculated voltage of the dark signal.

Подстановка оценок коэффициентов (3) в выражение (1) и замена U_т U₀ позволяет рассчитать напряжение смещения E_см.[I] необходимое для достижения требуемого уровня темнового сигнала

При E_см.1 0 выражение (4) переходит в выражение (2). Расчет погрешности экстраполяции по формуле (2) может быть выполнен, исходя из правил расчета погрешности косвенных измерений [8]

где σ_E, σ_И среднеквадратичные значения погрешности измерения амплитуды сигнала и расчета смещения.The calculated array of samples is entered into RAM 9 as described above, after which the corresponding array of pre-aligned samples of the dark signal UT ₃ [I] is read.
The problem of calculating the displacement considered above, based on the conditions for achieving a given signal level, inherently refers to the class of extrapolation problems, when two signal samples measured with a certain error for given values of the arguments determine the signal value for the argument that falls outside the range of the first two . Moreover, in the general case, the coefficients K [I] and U should be estimated _. dependences (1), and then with their help, the necessary bias can be calculated. The indicated coefficients are calculated as follows:

Substituting the estimates of the coefficients (3) in the expression (1) and replacing U _t U ₀ allows you to calculate the bias voltage E _see [I] necessary to achieve the desired level of the dark signal

When E _{see 110,} expression (4) goes over to expression (2). The calculation of the extrapolation error by the formula (2) can be performed based on the rules for calculating the error of indirect measurements [8]

where σ _E , σ _{And the} root mean square values of the error in measuring the signal amplitude and calculating the bias.

При U_o≃ 0 из выражения (6) следует, что погрешность экстраполяции темнового сигнала при поэлементном изменении его уровня UT₂[I] от минимального до максимального будет изменяться от σ_И до 2,3 σ_И Таким образом, для исключения попадания отсчетов массива UT₃[I] в область за границу нижнего уровня входного напряжения АЦП величина U₀ должна превышать максимальную погрешность измерения амплитуды сигнала более чем в два-три раза. С учетом соотношения между максимальным и среднеквадратичным значениями нормально распределенной погрешности можно записать следующее условие выбора U₀:
U_o> (6-9)•σ_И (7)
Наличие массива отсчетов темнового сигнала UT₃[I] с минимальным уровнем и массива UT₁[I] с максимальным уровнем позволяет с минимальной и практически равной для всех элементов ФДП 1 погрешностью рассчитать значения напряжений смещения этих элементов, при которых среднее значение их темновых сигналов будет находиться на уровне нижнего диапазона сигналов АЦП

где E_См.о.[I] напряжение смещения, при котором темновой сигнал элемента находится на уровне нижней границы диапазона АЦП.From expression (5), taking into account the linear relationship between the bias and voltage of the dark signal, an expression can be obtained for calculating the error of amplitude extrapolation

When U _o ≃ 0, it follows from expression (6) that the error of extrapolating the dark signal when the level of its level UT ₂ [I] is element by element changes from minimum to maximum will vary from σ _AND to 2.3 σ _AND Thus, to exclude the occurrence of array readings UT ₃ [I] into the region beyond the boundary of the lower level of the ADC input voltage, the value of U ₀ must exceed the maximum error of measuring the signal amplitude by more than two to three times. Given the relationship between the maximum and mean square values of the normally distributed error, we can write the following selection condition U ₀ :
U _o > (6-9) • σ _И (7)
The presence of an array of samples of the dark signal UT ₃ [I] with a minimum level and an array of UT ₁ [I] with a maximum level makes it possible to calculate the bias voltages of these elements with a minimum and almost equal error for all PDF elements 1, at which the average value of their dark signals will be be at the lower range of the ADC signals

where E _see [I] the bias voltage at which the dark signal of the element is at the lower end of the ADC range.

Moreover, since the level of samples UT ₃ [I] is close to the extrapolated zero level, the error of signal extrapolation in accordance with expression (6) will be equal to the error in measuring the signal amplitude. After recording the array of samples E calculated according to formula (8), _see [I] in RAM 9, the samples of the read dark signal of the PDP 1 will have the same values. The equal amplitudes of the readings of the readout dark signal is ensured by applying an alternating bias voltage during erasing, and the variable bias voltage component changes inversely to the scale of its own dark PDF signal 1. By choosing the bias voltage U _see about the second input of the first matching amplifier 2 and calculating the voltage bias by the formula (8), equality of the constant level of the dark signal and the lower level of the ADC input signals is achieved, as a result of which the level of the dark signal The digital output at the ADC output will be equal to zero to the accuracy of calculation and quantization. In this case, the resulting error compensation of the dark signal will depend on the noise level in the same way as in the case of hardware subtraction of the dark signal implemented in the prototype, i.e., increase by 1.4 times relative to the original error of signal measurement, however, the possibility of lower signal amplification, provided in the proposed device, can equally reduce the amount of noise, and therefore increase the accuracy of the compensation of the dark signal, i.e. provide a solution to the problem.

 Thus, from the description of the operation of the dark signal compensation device of a multi-element photodiode detector, it follows that the task of developing this device to improve the accuracy of compensation was solved in it by introducing new devices and establishing new connections between them. The introduction of computing device 4 allows you to record test bias voltages, calculate and record individual bias voltages, with which the preliminary alignment of the dark signal is performed, as well as calculate and record the final compensating bias voltages. The first and second multiplexers 6, 7 are introduced to ensure recording from WU 4 in RAM 10 samples of bias voltage. The second matching amplifier 11 is introduced to form the reference bias voltage of the PDF 1, consisting of a constant bias voltage and an alternating correction voltage supplied from the output of the DAC 10. The polling unit is introduced to ensure the PDT 1 and synchronize the operation of the elements of the compensation device, in particular the PDP 1 and RAM 9. New in the proposed device is the connection between the output of the second matching amplifier and the input of the reference bias voltage of the photodiode receiver, which made it possible to apply the variable and determine In this way, the calculated correction voltage was not in the path of the read signal, as was the case in the prototype, but in the path of the bias of the photodiodes, which provided a solution to the problem.

Literature
1. Ivanov V.V. Control unit of a linear driver of image signals on devices with charge coupling coupled to a computer. "Electronics-60". PTE, 1986, N 5, p. 63.

 2. Arutyunov V. A. Gorbachev S. F. Demin A.P. Nagulin Yu.S. Optomechanical Industry, 1986, N 1, p. 34.

 3. Demin A.P. Multichannel system for recording optical radiation with dark noise compensation PTE, 1988, N 6, p. 150-154.

 4. Photodetector device FUK1L1, FUK1L2. Label of the manufacturer.

 5. Fedorkov B. G. Telets V.A. DAC and ADC chips: operation, parameters. M. Energoatomizdat, 1990.

 6. Desyatkov V.G. Magdenko S.V. Finogenov L.V. The work of the integrated line of photodetectors as a delay device for analog signals. Autometry, 1987, N 5, p. 38-46.

 7. Dvoryashin B.V. Fundamentals of metrology and radio measurements. M. Radio and Communications, 1993, p. 320.

Claims (1)

 A dark signal compensation device for multi-element photodiode receivers containing a multi-element photodiode receiver (PDP) with erasure and read registers, matching amplifier, analog-to-digital converter (ADC), random access memory (RAM), address counter, and digital-to-analog converter (DAC), characterized the fact that a computing unit, a polling unit, a first and second multiplexer and a second matching amplifier are introduced into it, while the clock inputs of the PDP are connected to the outputs of the same name of the polling eye, the input of the horizontal pulse of erasing the PDP is combined with the first input of the second multiplexer and connected to the output of the horizontal pulse of erasing the polling unit, the input of the horizontal pulse of reading is combined with the first clock input of the computing block and the signal input of the PDP is connected with the first input of the first matching amplifier, to the second input of which a bias voltage is applied, the output of the first matching amplifier is connected to the signal input of the ADC, the trigger input of which the second is connected to the first clock output of the polling unit, and the information outputs and the output of the conversion end are connected respectively to the information inputs and the second clock input of the computing unit, the first and second outputs of the clock pulses of which are connected to the second inputs of the first and second multiplexers, respectively, the control output is connected to the same name the inputs of the same multiplexers and the RAM recording input, and the information outputs of the computing unit are connected to the RAM inputs of the same name, the first input of the first mult the plexor is connected to the second clock output of the polling unit, and the outputs of the first and second multiplexers are connected respectively to the clock input and reset input of the address counter, the outputs of which are connected to the address inputs of RAM, the information outputs of RAM are connected to the same inputs of the DAC, the output of which is connected to the first input of the second matching amplifier, an initial bias voltage is applied to the second input of the second matching amplifier, and its output is connected to the input of the reference bias voltage of the PDP.

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