RU2101772C1 - Mnemonic training bed - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has frequency divider 1, calculation unit 2, registers 3, 5, program memory unit 4, row decoder 6, gate unit 7, line decoder 10 and light-emitting diode matrix 11. Goal of invention is achieved by introduced zero decoder 8 and address counter 9. EFFECT: possibility to learn software and hardware. 2 cl, 4 dwg , 1 tbl

Description

 The invention relates to computer technology and is intended to study hardware and software.

Known simulator mimic diagrams containing an address register, a decoder, information registers associated with the calculator, and an LED matrix consisting of LEDs, mnemonic diagrams, switching elements, AND elements and NOT elements [1]
Such technical means are convenient for practical studies on the study of the hardware of digital technology because of the visual presentation of electronic circuits, but they do not allow teaching software. This reduces the didactic capabilities of the simulator when conducting a workshop on microprocessor technology. In addition, the matrix indicator used has significant hardware redundancy due to the use of two-input AND elements and NOT elements.

Closest to the subject is a mimic simulator containing a calculator, a frequency divider, a valve block, first and second registers, a program memory block, as well as a row decoder and a column decoder, the outputs of which are connected to the corresponding inputs of the LED matrix [2]
The disadvantage of this simulator is the inability to learn software tools.

 The proposed simulator allows you to solve this problem.

 In FIG. 1 shows a block diagram of a simulator; in FIG. 2 LED matrix circuit; in FIG. 3 mimic diagram; in FIG. 4 block diagram of the program.

 The simulator contains a frequency divider 1, calculator 2, implemented in the form of a programmable calculator, pulse-type type, first register 3, program memory block 4, second register 5, column decoder 6, valve block 7, zero decoder 8, address counter 9, decoder 10 lines and LED matrix 11.

 Block 7 is made in the form of two serially connected two-input elements AND-NOT, and the second input of the second of these elements is connected to the output of the frequency divider 1.

 The zero decoder 8 is a four-input AND-NOT element.

 The LED matrix 11 consists (Fig. 2) of n elements 12 NOT and m x n LEDs 13 and has an n-bit bus 14 columns and m-bit bus 15 rows. The LEDs 13 in addition to the indication also serve to decouple the rows and columns of the matrix. LEDs 13 are placed on the front panel of the screen in the form of a matrix m x n with a replaceable mimic (Fig. 3).

 The simulator works as follows.

В двухкоординатной матрицеm, n}10, 10} организуется 100 адресов от 00 до 99. Номер адреса вводится с клавиатуры вычислителя 2 (калькулятора) или формируется программно и регистрируется на цифровом табло.A mimic diagram of an opaque material with holes for LEDs 13 is superimposed on the front panel with LED matrix 11, which depicts the device under study in the form of an application of colored material. This device can be represented on a mnemonic diagram at any necessary hierarchical level, from an element to a network, with a representation of the studied object (process) in a spatial, temporal, or functional field defined by this matrix 11. The number of rows m and columns n is convenient for the calculator to be specified in the positional decimal code, while the address of the LED 13 is advisable to represent a pair i, j} numbers in the form

In the two-coordinate matrix m, n} 10, 10} 100 addresses from 00 to 99 are organized. The address number is entered from the keyboard of the calculator 2 (calculator) or is generated programmatically and registered on a digital display.

The number on the indicator is represented by a mantissa of 8 positions and an order of 8 positions. The mantissa of the number is formed from four addresses A _ij , and the sign of the order of the lowest position is used to indicate the number K1, 4} of the familiarity of the address of the mantissa, from which it is supposed to output the address A _ij to the field of the LED matrix 11. For example, the first pair is output from the values of the order sign 01}, 02} second, 03} third, 04} fourth, 00} - one of the mantissa pairs is displayed.

 The numbers from the calculator (calculator 2) are displayed sequentially in time at one position in the binary decimal code, starting with the order sign and ending with the lowest position of the mantissa. The calculator allows you to select addresses from registers, stacks and program memory. For example, the Electronics-MK 64 microcalculator contains 10 registers, 6 stacks and 66 steps of program memory and allows operating in 64 addresses in the direct addressing mode. When modifying the values of the contents of registers and stacks according to the algorithmic program, the number of displayed coordinates is limited only by the dimension of the matrix 11.

 To indicate the required address on the LED matrix 11, the operator forms on the display panel (in the current register X) of the calculator 2 up to four addresses in the mantissa with an indication of the order of familiarity of this address. An output program and an operating mode code are pre-entered into the calculator in accordance with the instruction (for example, the number 11010003 in register N 9). Use the c / p key to start the microcalculator calculation program (calculator 2). The cyclic output of the coordinates of the addresses to the information output of the calculator 2 is organized by the subroutine of the microcalculator cycle and the clock pulses received at the "Start" input. Each input pulse corresponds to one clock cycle of the calculator 2, and one cycle includes 15 clock cycles. A pack of 14 pulses is generated from the synchronization frequency coming from the generator of the calculator 2 through the elements of block 7. At the control output of the calculator 2, after the next act, a synchronization pulse is generated, which is added up by the counter 9 with a conversion factor of 15 (from 0 to 14). The counter 9 controls the pulses from the output of the decoder 8 zero when forming the service code 1111} at its input} is fixed on the information bus of the calculator 2 after the output of information in the cycle. The counter 9 is reset to zero potential at the time the service code appears, and counts when a unit potential occurs. Counter 9 stops because the start pulses of the calculator 2 are blocked, coming from block 7 at the time of generating the service code that controls the switching of block 7 on the third input.

 Each cycle begins at the moment a pulse appears at the output of the frequency divider 1, which forms it by dividing the synchronization frequency of calculator 2. For the simulator, the period of arrival of clock pulses is selected for 1-10 s and is determined by the subjective characteristics of the perception of the visual change of the student's information.

A clock pulse through block 7 starts the calculator 2, at the information output of which, at the same time, the service code is changed to information. The resolving potential appears at the output of the zero decoder 8 and the counter 9 starts counting the pulses generated at the output of the calculator 2 from the synchronization pulses passing through the block 7 to the “Start” input. The counter 9 changes the addresses of the memory unit 4, which generates recording pulses at the corresponding moments of information output. The first pulse allows writing the number of the lowest position of the order sign in the first register 3 (address register). In this case, the initial code of one of the subroutines of the algorithm for recording information in the second register 5 (information register) is formed on the address buses of the memory unit 4. In accordance with the previously selected example, pulses are generated at the outputs of the memory unit 4: for a sign of order 01} at the moment the positions of the first mantissa pair appear, 02} the second pair, 03} the third pair, 04} the fourth pair, 00} there are no pulses. In register 5, addresses A _ij are sequentially formed in time, given on the mantissa of the number in the indicator of the calculator (calculator 2). The on-off binary decimal code is converted by the decoders 6 and 10 into the on-off unit decimal code and decrypted by the LED matrix 11 into the positional code. On the front panel of the simulator, LEDs 13 are sequentially displayed in time with an address programmatically controlled by the operator by means of calculator 2.

.The LEDs 13 of the matrix 11 transform the two-coordinate code X, Y} received on the bus lines 15 and columns 14, through the use of a logical function of inclusion

.

In this case, LED 13 is displayed with the address A _ij when a combination of α _ij = {0, 1} appears on it. Other LEDs 13 are off because only the remaining three combinations are present at their inputs, locking the diodes of the matrix 11. The necessary function is realized by switching on the elements of the HE 12 element via the bus 14 of the columns and the corresponding connections in the (ij) th cell of the LED 13 (Fig. 2).

 In the above training mode, the mnemonic imitates the functioning of the device under study using the example of a structural, functional or proportional circuit in the basis of combinatorial or matrix logic, with the presentation of a truth or state table, a mathematical model and a time diagram.

 In the control mode, the teacher enters the control addresses into the stacks of the calculator (calculator 2), and the examiner enters the alleged addresses into the registers. According to the program, the addresses are compared. If there are erroneous addresses, the examiner is awarded penalty points, and if the answer is correct, the device’s operation is displayed on the mnemonic diagram, after which the final score is displayed on the calculator’s scoreboard (calculator 2).

 The study of hardware is accompanied by an increase in programming skills, from programs with direct addressing that use register and stack memory to algorithmic programs with subprogram and conditional jumps for implementing modified addressing. The trainee simultaneously obtains values for hardware and software, comprehensively studies the architecture of software-controlled devices, which is necessary for a deep understanding of the essence of microprocessor technology.

 To change the information in the simulator, the calculator (calculator 2) calculates according to the program by pressing the c / p key in accordance with the Stop command according to the staff schedule of calculator 2. At the same time, calculator 2 switches to interactive mode, pulses from the output of valve block 7 are blocked, and accordingly at the input of the counter 9 pulses are not received. The address counter 9 stops, and the current address is fixed at the input of the memory unit 4. The inhibitory potential comes to the inputs of the registers 3 and 5, and the service code appears at the information outputs of the calculator 2. At the output of the zero decoder 8, a inhibitory potential is formed, confirming the stop of the counter 9 and blocking the passage of pulses through the valve block 7.

 After changing the information in the simulator, the operator transfers the calculator (calculator 2) from the dialogue mode to the calculation mode according to the program by pressing the c / p key. At the output of the calculator, the service code is replaced by information, the inhibitory potential at the output of the decoder 8 zero is removed. The pulses from the valve block 7 through the calculator 2 are fed to the input of the counter 9, which, after zeroing, continues the summing, and the cycle of the simulator continues according to the above scheme.

 The simulator software consists of three types of programs: information output from registers, from stacks, and algorithmic. Algorithmic programs allow you to modify the contents in registers and stacks in accordance with the algorithm of functioning of the studied object (process). The simplest programs are the output from the registers, when cyclically, from register to register, addresses are selected from the register memory.

As an example, consider a block diagram of a program for deriving address coordinates from a stack (Fig. 4), which is a fragment in the simulator software. The program is made cyclical and consists of 6 blocks. After the start of operation in the first block of programs, information from the l-th ring stack C _l with the order sign 04 is entered into the operational registers X and Y} In the second block of the program, a two-position address is output from the kth position of the mantissa of register X to the information output of calculator 2. B the first sub-cycle displays the fourth pair in accordance with the fourth order of the mantissa. After the output, the contents in the operational registers are reduced by an order of magnitude, which is necessary for the output of the (k-1) -th pair. The unit in the fourth block is subtracted from the contents of register Y, and the mantissa order is checked in the fifth block. If the order is greater than zero, then X> 0, and the transition to the second block of information is displayed, otherwise, for X <0, the sixth block is executed. The value of the register U is increased by 4 orders of magnitude and through the register X the (l-1) th stack C _l-1 ) is sent, which is necessary to restore the contents selected from the l-th stack. After this, the transition to the first block occurs and the cycle repeats. In each sub-cycle, only the k-th mantissa pair is displayed, and for the cycle 4 pairs, starting from the fourth, with the contents in the stacks moving along the ring without structurally changing.

 On the example of simulating a logical two-input AND-NOT element in a step-by-step time mode, we consider training in a mnemonic diagram in combinatorial and matrix form, in the truth table and time diagrams (Fig. 3). The student superimposes the mimic diagram on the front panel of the matrix 11, while the LEDs project into the openings of the mnemonic diagram 13. The learner needs to enter the program and data into the stacks according to the attached table.

There are two options in this table:
simulation on α combinatorial logic, b truth table and g time diagram,
imitation on a combinatorial logic and d matrix logic.

 The comma located in the fourth position determines the initial fourth order of the mantissa. The line-by-line coordinates reflect the combination of the corresponding terma, b} Information is entered into the calculator stacks line-by-line from left to right and from top to bottom. After loading the seventh stack (an example is given for MK-64, MK-46, BZ-21 microcalculators of the Electronics series) on the digital display of calculator 2, which also corresponds to register X, the first number from the first line of this table is displayed.

 The student starts the program in the calculator 2 by pressing the c / p key. On the mnemonic diagram, the LEDs 13 of the matrix 11 are sequentially displayed in time with the addresses indicated in the table in rows from the fourth to the first pair. In this case, for the first option, pri, b} 0,0} are switched on output C of the element (З2-th address), minterm from the truth table (36), a single logic level at the output C (56) and again the output C of the element (32) . Then, the LEDs at the input "a" of the element 11, the minterm "a" of the table (17), the units at the input "a" (66, etc.) are alternately indicated. After the information is output from the mixture of stacks, the cycle repeats.

 Demonstration of the work of a logical element in various functional representations activates the associative memory of the learner and develops figurative thinking. Based on the results of practical exercises when simulating digital tools on the simulator, the student is taught comprehensive knowledge on hardware and software of software-controlled devices.

Claims (2)

 1. A simulator of mimic diagrams containing a calculator, a frequency divider, a valve block, first and second registers, a program memory block, as well as a row decoder and a column decoder, the outputs of which are connected to the corresponding inputs of the LED matrix, characterized in that a zero decoder and an address counter, the outputs of which are connected to the least significant bits of the address inputs of the program memory block, the control and information outputs of which are connected respectively to the first register write permission input and the address input second register, the clock output of the calculator is directly and through a frequency divider connected to the first and second inputs of the valve block, the information outputs of the calculator are connected to the information inputs of the second register, the first and second groups of outputs of which are connected to the inputs of the row decoder and column decoder, respectively, the outputs of the first register connected to the senior bits of the address inputs of the program memory block, the inputs of the first register and the zero decoder are respectively combined and connected to the elders m bits of information outputs of the calculator, the output of the zero decoder is connected to the input of zeroing the address counter and the third input of the valve block, the output of which is connected to the input of the start of the computer, the control output of which is connected to the counting input of the address counter.  2. The simulator according to claim 1, characterized in that the LED matrix contains LEDs and NOT elements, the inputs of which are the inputs of the matrix columns, and the outputs are connected to the first outputs of the corresponding LEDs, the second output of each LED is connected to the corresponding input of the matrix rows.

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