RU2094815C1 - Simulator of radio sources - Google Patents

Abstract

FIELD: radio engineering, in particular, testing of operations of radio systems using automatic test beds and half-natural models of different radio systems. SUBSTANCE: multiple-channel device has code setter with interface, reference frequency grid generator, adding unit. Each simulation channel has digital frequency synthesizer, unit which controls bandwidth settings, unit which controls power of signal, channel number decoder, master oscillator, frequency converter, first and second modulators and output attenuator. Said units in simulation channel are connected to code setter. Reference frequency grid generator is connected to all simulation channels, code setter and computer. Adder joins signals from outputs of output attenuators of simulation channels. Direct generation of flow signals and their superposition in time proceeds as follows: signal images are stored in memory unit of unit which controls bandwidth settings, to first and second modulators. Rate and intervals for reading signal images from memory unit are provided for timers of unit which controls bandwidth settings, unit which controls signal spectrum and unit which controls power of signal. Initial start of generation of signal flow is done by arrival of synchronization signal simultaneously to all channels or according to program which determines signal superposition. Reference frequency generated by frequency grid generator determine bandwidth of signals depending on data which are read from memory unit of unit which controls bandwidth settings, and are sent to commutator of reference frequencies and commutator of frequency converter of each channel. Spectrum of signals is generated in corresponding digital frequency synthesizers. Their amplitude characteristics depend on second modulators. Device design provides possibility of superposition of source or reflected signals from several different objects which may move in space. EFFECT: possibility to design complex scripts of alternating environment or signal flow at input of equipment to be designed or tested. 9 cl, 11 dwg

Description

 The invention relates to radio engineering tools for monitoring and modeling the functioning of various complex radio systems and their components and can be used in stands of physical and mathematical modeling, simulators and control and measuring complexes for working out functioning algorithms, for measuring parameters and their monitoring of antenna, radio engineering , radar systems, radio countermeasures systems and other devices for simulating several mobile radiation sources, working them in various modes.

 A device is known that implements a method of simulating a radio engineering situation during radio engineering measurements according to ed. St. N 1495878, MKI H 01 Q 17/00, 1989. The device comprises a working volume, an antenna under test, rotating arc guides, a primary and secondary target emitters, and a signal conditioner. In the specified technical solution, the simulation of the radio environment is carried out by an electromechanical system with all its consequent disadvantages in terms of reliability and speed and does not allow simulating several signals simultaneously (with their superposition in time).

 A known radio signal simulator comprising a radio frequency generator, the output of which is connected to the input of the radio frequency unit, the other input of which is connected to the output of the modulation control unit, which is connected by its second output to the control input of the radio frequency generator; the simulator also comprises a computer connected to a keyboard, a disk storage unit, a display, a modem, the computer output is connected to a modulation control unit and to an antenna rotation control unit; the radio frequency unit has an output of radio frequency signals in the range of 0.5 to 18 GHz and five outputs of radio signals, respectively, of five sub-bands, providing a given band of operating frequencies. These five outputs are connected through amplifiers and a switch to antenna emitters (see the technical description of A. R.T.I.S simulator from ELETRONICA S.p.A, Italy, 1989).

 The specified simulator generates radio signals in the range 0.5 to 18 GHz with various types of pulse modulation (single pulse and pulse train, pulse train, sawtooth and triangular pulses), etc., and can be used to simulate the radio environment and train operators of radar systems in conditions approaching the real ones.

 A well-known simulator of electronic signals, containing a control computer with an interface and a simulation channel, a digital frequency synthesizer DSC connected to its output with the first input of the frequency converter. The frequency converter has three steps of frequency conversion for transferring the signal spectrum to the 3 cm microwave range, each of which includes a mixer, filter, amplifier and another fourth block of the same frequency composition of the carrier frequency from the 3 cm microwave range to a lower frequency operating range 10 centimeter, between the first and second stages of conversion, a controlled attenuator is turned on, and the output attenuator is turned on at the output of the fourth stage of conversion. In addition, the simulator contains a reference frequency driver and reference frequency switch, which are circuit-connected, and four switched frequency grids are connected respectively to the inputs of four steps of the frequency converter, i.e. to the heterodyne inputs of the mixers of the conversion steps.

 In addition, the simulation channel contains the first and second modulators, made in the form of storage devices (memory) and structurally combined in one unit. The output spectrum control signal spectrum of the first modulator is connected to the input of the DSC, the first modulator also has a second output, through which the first modulator controls the switching of all reference frequency grids in the reference frequency driver and reference frequency switch, and the input of the first modulator is connected to the computer interface. The output of the signal power control of the second modulator is connected to the second inputs of the controlled and output attenuators, the input of the second modulator is also connected to the computer interface.

 The first and second modulators are essentially databanks specified by a computer in which the parameters of the modulating signals are stored in the form of digital codes, and the direct conversion of digital codes into the form of the spectral components of the signal, its carrier frequency and power is carried out in the digital frequency converter, in the reference driver and switch frequencies, as well as in controlled and output attenuators. (see simulator developed by Hewlett Packard, USA, "Frequency Agile Signal Simulation" type HP 8791, technical description and operating manual, 1990, USA, Hewlett Packard).

 This simulator is taken as a prototype.

 The simulators given as analogues and prototype allow you to get output signals with different types of modulation without superimposing at least two signals in time.

 The invention solves the problem of approximating the actual operating conditions of electronic equipment during their design at the design stages during the development of functioning algorithms, during test control of finished products, as well as the possibility of physico-mathematical modeling of the input signal stream simulating almost any complex radio environment that cannot be created in full-time conditions in real time, as this is associated with unacceptably long periods and material costs.

 Thus, the problem of realizing complex scenarios of the radio environment with a large flow of input signals from a large number of non-synchronous operating in different, alternating modes of electronic means, in which there is a high probability of overlapping several signals in time, is solved.

 The technical result achieved by using the claimed simulator is to expand the functionality due to the formation in real time of radio signals corresponding to a complex radio environment, when the simulated signals are superimposed on each other in time.

 To achieve the specified technical result, a radio signal source simulator containing a control computer with an interface, a low-frequency reference grid driver, an optical frequency reference switch, and a simulation channel, including a digital frequency synthesizer, connected to its output with a frequency converter, including the first mixer, filter, second mixer, power amplifier and controlled attenuator, and the output attenuator is connected to the output of the frequency converter with its first input In addition to the first modulator including a signal spectrum control output connected to the first input of the digital frequency synthesizer and a second modulator with a signal power control output connected to the second inputs of the controlled and output attenuators, a summing unit and N-1 identical simulation channels are introduced, and in each of the N simulation channels, a control unit for setting the sub-band of the BUUP, a master oscillator, a channel number decoder, the first input of which is connected to the "channel number data" interface bus, is inserted the second input of which is connected to the “synchronization” output of the interface, as well as the control unit for the BUSSS signal sector is introduced with its first input connected to the bus “clock data of the interface”, the second input connected to the bus “interface data”, its third input connected to the first output the channel number decoder, its fourth input connected to the second output of the channel number decoder, is connected to the first input of the first modulator with its first output, the second output to the second input of the first modulator, its by the third output to the third input of the first modulator, the fourth output of the BUSS is connected to the fifth input of the first modulator, the fifth output of the BUSS is connected to the sixth input of the first modulator, the fourth input of the first modulator is connected to the bus "signal spectrum data" of the interface, the seventh input of the first modulator is connected to the third output of the channel number decoder, the output of the first modulator is connected to the first input of the DSC; in addition, a power control unit for the BUMS signal of the "interface, with its second input connected to the bus" address is entered data interface, connected to the first output of the channel number decoder with its third input, connected to the second output of the channel number decoder with its fourth input, connected to the first input of the second modulator with its first output, its second output to the second input of the second modulator, and its third output of the BUMS connected to the third input of the second modulator, the fourth output of the BUMS is connected to the fifth input of the second modulator, the fifth output of the BUMS is connected to the sixth input of the second modulator, the fourth input of the second modulator pa is connected to the interface “power setting data” bus, the seventh input of the second modulator is connected to the third output of the channel number decoder, the first output of the second modulator is connected to the fourth input of the frequency converter, the second output of the second modulator is connected to the second input of the channel power attenuator, and to the converter the frequencies of each channel, a splitter for M outputs, a switch for M inputs and M outputs, M filters, an adder for M inputs are introduced, and the splitter input is connected to the output of the controlled attenuato a, the outputs of the splitter are connected to the corresponding inputs of the switch, the outputs of which are connected respectively to the inputs of M filters, the outputs of which are connected to the corresponding inputs of the adder, the output of which directly or through a power amplifier is the output of the frequency converter, M of the fifth inputs of the frequency converter are connected respectively with M outputs of the control unit , the control unit for setting the BUPP subband with its first input is connected to the bus "BUPP clock data" of the interface, with its second input it is connected to it doesn’t have an “data address” of the interface, connected to the first output of the channel number decoder with its third input, connected to the second output of the channel number decoder with its fourth input, connected to the third output of the channel number decoder with its fifth input, subrange setting data connected to the bus ", the output of the master oscillator is connected to the clock inputs of the BUMS, BUSS and the BUUP, the clock outputs of the driver of the reference frequencies FOC from 1 to N are connected respectively to the second inputs of the digital frequency synthesizers of each analog, M outputs of the reference frequencies of the FOC block are connected to the first corresponding inputs of the FOC, the outputs of the frequency of the transfer of the block FOC from 1 to N are connected to the second inputs of the frequency converter of the corresponding channels, outputs of the FOC from 1 to N are connected to the third inputs of the frequency converters of the corresponding channels, second inputs KOCH form N groups of M inputs in each, and the inputs of the first group are connected respectively to the M outputs of the control unit of the first channel, the inputs of the second group are connected respectively to the M outputs of the control unit of the second channel, etc. the inputs of the N group are connected respectively to the M outputs of the BUUP of the N-th channel, the first input of the master oscillator of each channel is connected by the output "enable external clock" of the interface, the second input of the master oscillator of each channel is connected to the output

 In a particular embodiment, the reference frequency switch KOCH contains M splitters, each of which has one input and N outputs, N switches, each of which has a first group of M inputs, a second group of M inputs and one output, as well as N amplifiers, the first outputs each splitter are connected respectively to the inputs from the first to the Mth of the first switch, the second outputs of each splitter are connected to the inputs of the first to the Mth of the second switch, etc. The N-th outputs of each splitter are connected respectively to the inputs from the first to the M-th N-th switch, the outputs of the switches through the corresponding amplifiers form N outputs KOCH, the inputs of the splitters are the first inputs of KOCH, N groups, in each of which M inputs are second inputs KOCH.

 In a particular embodiment, the low-frequency reference driver shaper contains the first and second splitters for N outputs each, the third and fourth splitters for two outputs each and the fifth splitter for M outputs, as well as a crystal oscillator, two logical elements AND, a logical element OR, an inverter, five power amplifiers, three filters and M + 1 reference frequency sensors, the crystal oscillator connected to the first input of the first logical element And, the second input of the first logical element And connected to the output of the inverter, the input of the inverter with is single with the first input of the second logical element AND and is the first input of the “external clock resolution” of the low-frequency element, the second input of the second logical element And is the second input of the “external clock” low-frequency element, the output of the first logical element AND is connected to the first input of the logical element OR, the output of the second logical AND element is connected to the second input of the OR gate, the output of the OR gate through series-connected first power amplifier, third splitter, first filter, second power amplifier, fourth a splitter, a third filter, a third power amplifier connected to the input of the first splitter, the second output of the fourth splitter through the (M + 1) th reference frequency sensor and a fifth power amplifier connected to the input of the second splitter, the second output of the third splitter through the second filter and the fourth power amplifier connected to the input of the fifth splitter, M outputs of which through the corresponding M reference frequency sensors form M outputs of the reference frequencies of the low-frequency reference, outputs 1 to N of the first splitter form the clock outputs of the low-frequency differential, output s from 1 to N of the second splitter form the output frequencies of the transfer channel.

 In a particular embodiment, the control unit for controlling the spectrum of the BUSS signal contains a timer, a processor, an internal address shaper, an address switch, the timer output being connected to the processor clock input, the first timer input is the first BUSS input for connecting to the BUSS clocking interface bus, the second input the timer is a clock input for connecting the ЗГ, the third input “enable data recording” of the timer is the third input of the BUSS for connecting to the third output of the channel number decoder, the second input of the process ORA is the input of the operating mode and the fourth input of the BUSS, the first processor output is clock for generating the address and is connected to the input of the internal address generator, the second output of the processor "RAM selection" is the third output of the BUSS, the third read-write output of the processor is the second output of the BUSS , the fourth output is “enable switching” of the processor is connected to the first input of the address switch, the fifth output of the processor is “write enable in WG” is the fifth output of the BUSS, the sixth output is “control the data switch” is the fourth output of the BUSS, the output "address" of the internal address generator is connected to the third input of the address switch, the output of which is the output of the BUSS, the second input "address from the computer" of the address switch is the second input of the BUSS.

 In a private embodiment, the first modulator contains RAM, a data switch, a register, and current keys, the RAM address being the first input of the first modulator for connecting to the first BUSS output, the read-write RAM input is the second modulator input for connecting to the second the output of the BUSC, the input "selection" of RAM is the third input of the first modulator for connecting to the third output of the BUSC, and the input-output "data" of the RAM is connected to the first input of the data switch, the second input of which is the fifth input of the first modulator, the third input of the “data spectrum of the signal” of the data switch is the fourth input of the first modulator, the output of the “data” of the switch is connected to the first input of the register, the second input of the “write permission” of the register is the fifth input of the first modulator to connect to the fifth output of the BUSS, the third input The "write to register" of the register is the seventh input of the first modulator for connecting to the third output of the channel number decoder, the output of "WG data" is connected to the input of current keys, the output of which is the output of the first about a modulator for connecting to the second input of the digital clock.

 In a particular embodiment, the BUMS signal power control unit comprises a timer, a processor, an internal address shaper, an address switch, the first timer input being the first BUMS input for connecting to the interface’s “BUMS clock data” bus, the second timer input is a clock input for connecting ZG, the third the input "data recording permission" is the third input of the BUMS for connecting to the first output of the channel number decoder, the timer output is connected to the first "clock" input of the processor, the second input is "operation mode" the timer is the fourth input of the BUMS, the first output "clock cycle for forming the address" of the processor is connected to the input of the internal address generator, the second output of the processor "RAM selection" is the third output of the BUMS, the third read-write output of the processor is the second output of the BUMS, fourth output the switching permission of the processor is connected to the first input of the address switch, the fifth output of the processor, the "write resolution in the WG" is the fifth output of the BUMS, the sixth output of the "control data switch" is the fourth output of the BUMS d "address" of the shaper of the internal address is connected to the third input of the address switch, the output of which is the output of the BUMS, the second input "address from the computer" of the address switch is the second input of the BUMS.

 In a private embodiment, the second modulator contains RAM, a data switch, a register and current keys, the RAM address being the first input of the second modulator for connecting to the first output of the BMS, the read-write RAM input is the second input of the second modulator for connecting to the second output of the BUMS, the input "sample" of RAM is the third input of the second modulator for connecting to the third output of the BUMS, and the input-output "data" of the RAM is connected to the first input of the data switch, the second input of which is the fifth control of the second modulator, the third input of the “power setting data” of the data switch is the fourth input of the second modulator, the output of the “data” of the switch is connected to the first input of the register, the second input of the “write permission” of the register is the fifth input of the second modulator for connecting to the fifth output of the BMS, the third input The "write to register" of the register is the seventh input of the second modulator for connecting to the third output of the channel number decoder, the output of "WG data" is connected to the input of current keys, the first output of which is the first you Odom second modulator for connection to a second input of the frequency converter, the second output of the current key is the second output of the second modulator to connect to a third input of the frequency converter.

 In a private embodiment, the control unit for setting the sub-ranges of the control unit comprises a timer, a processor, an internal address shaper, an address switch, RAM, a data switch, a register, a data decoder, current keys, the timer output being connected to the processor clock input, the first timer input is the first input of the control unit to connect the interface to the bus “clock data of the BCCM”, the second timer input is a clock input for connecting the ZG output, the third input of the “data recording enable” timer is the third BECM input for connecting the channel number to the first output of the decoder, the second processor input is the operating mode input and the fourth input of the control unit, the first processor output is clock for generating the address and is connected to the input of the internal control unit of the internal control unit, the second output of the RAM sample processor is connected to the third RAM input , the third read-write output of the processor is connected to the second RAM input, the fourth output of the switching permission processor is connected to the first input of the address switch, the fifth output of the processor is recording permission and into the register "connected to the second input of the register, the sixth output" control of the data switch "is connected to the second input of the data switch, the output of the internal address generator is connected to the third input of the address switch, the second input of which is the second input of the control unit for connecting to the" data address "bus , the output "RAM address" of the address switch is connected to the first RAM input, the "data input-output" of the RAM is connected to the first input of the data switch, the third input of the data switch is the sixth input of the control unit for connecting the data bus ovki subband "interface, the data output of the switch connected to the first register input, the output of which is connected to the input of the data decoder, a third input" Entry RG "register is the fifth input BUUP, the output of decoder of data coupled to the input current of keys which output is the output BUUP.

Comparison of the claimed simulator with the prototype shows that the common features are:
the presence of a control computer with an interface that is a setter of codes,
the presence of a master oscillator in the simulation channel;
the presence in the simulation channel of a digital frequency synthesizer connected by its output to the first input of the frequency converter. The frequency converter includes conversion steps, consisting of a mixer, filter, amplifier, carrying out the transfer of the spectrum of the simulated signal to a given microwave range;
the presence in the simulation channel of the reference frequency driver and reference frequency switches;
the presence in the channel of simulation of controlled and output attenuator;
the presence in the channel simulation of the first and second modulators.

Distinctive features of the claimed simulator are:
the presence of N channels of simulation (in the prototype one channel);
the implementation of the reference frequency shaper (FOC) and the reference frequency switch (KOC) in the form of separate blocks that ensure the operation of all channels simultaneously (in the prototype of the OCh and KOCh, circuitry are combined and are part of the channel);
the presence of a summing block;
the introduction into each of the channels of imitation of new units compared to the prototype, namely, the control unit for setting the sub-band of the BUUP, the control unit for the spectrum of the BUSS signal, the control unit for power of the BUMS signal, the channel number decoder;
new in comparison with the prototype implementation of the first and second modulators;
introduction to the frequency converter unit of each channel simulating a splitter, a switch, filters and an adder (splitter);
new connections between blocks.

 In this case, when creating an N channel simulator in accordance with the principles of constructing a block diagram of a prototype simulator, it would be necessary, in comparison with the proposed simulator, to introduce additional N reference frequency shapers with reference frequency switches (FOC and KOCh), as well as N + 1 control computers.

 To establish a causal relationship between the achieved technical result and the differences of the proposed simulator, we consider how the superimposition of the simulator signals occurs in time.

 In each channel of the simulator, it is possible to form not only one signal, but also several signals independent in time. For example, in the time interval t0 T1, a signal is generated with frequency modulation of the carrier frequency f0, in the time interval t1 t2, a signal is generated with pulse modulation on the carrier frequency f1, etc. In the selected time intervals, it is possible to generate signals with other types of modulation and at different or the same carrier frequencies, depending on the simulated scenario of the electronic environment. The possibility of generating in each channel a large number of signals of various electronic devices operating in different successive modes invariably intentionally or unintentionally leads to the superposition of several signals over each other in time. The direct addition (branching) of the signals at the output of the simulator occurs in a summing block that does not contain nonlinear active elements, which helps to avoid the parasitic effect of one signal on the spectral characteristics of another. Each specific simulation scenario determines the signal flow at the output of the simulator, and the direct formation of the flow signals occurs as follows.

 Programmatically, signal portraits are entered into each simulator channel, namely in the BUUP RAM, the first and second modulators, and data on the rates and intervals for reading portraits from the RAM are entered in the form of codes in the timers BUUP, BUSS, BUMS, reading is carried out according to the commands of the corresponding processors available in each channel. The operation mode of each channel is determined by the computer program controlling each channel through the corresponding channel number decoder. The initial start-up of the formation of a flow, a certain scenario of the electronic environment, is carried out by applying a synchronization signal to either all channels simultaneously or to each separately in accordance with the program, which determines the temporal superposition of signals. In this case, the reference frequencies generated in the FOC, depending on the data read from the RAM of the BUUP of each channel and coming from the outputs of the BUUP to the inputs of the BCF and the inputs of the commutators of the frequency converters of each channel, determine the subband in which a signal spectrum of a certain power is formed at a given carrier frequency , with the given parameters recorded in the RAM of the first and second modulators and read respectively in the DSC and for controlling the attenuators in the frequency converter in each channel.

 In FIG. 1 shows a structural electrical diagram of the proposed simulator of radio signal sources; in FIG. 2 electric circuit of the shaper of the reference frequency grid (FOC); in FIG. 3 electric circuit of the switch of reference frequencies (KOCH); in FIG. 4 electric circuit of the sub-band installation control unit (CUP); in FIG. 5 is an electrical diagram of a first modulator; in FIG. 6 electric circuit of the signal spectrum control unit (BUSS); in FIG. 7 is an electrical diagram of a second modulator; in FIG. 8 is an electrical diagram of a signal power control unit (BMS); in FIG. 9 is an electrical diagram of a frequency converter; in FIG. 10 electrical circuit of the frequency synthesizer (CSC); in FIG. 11 processor circuitry.

 Consider an example of a specific embodiment of the invention.

 The proposed simulator of radio signal sources contains N channels (first channel 1, Nth 2) simulations, a reference frequency shaper (FOC) 3, which has from 1 to Mth outputs of the reference frequencies, N outputs of the clock frequencies and N outputs of the transfer frequency, with their outputs of the reference frequencies, the FOCs are connected to the first inputs of the switch of the reference frequencies (FOC) 4, the second inputs of which form N groups of M inputs in each group. KOCH has N outputs. In addition, the simulator contains a summing block 5, to the inputs of which the outputs 1 through N of the simulation channels are connected respectively, the output of the summing block is the output of the simulator, code generator 6.

 Simulation channels are identical. Each channel contains a master oscillator (ZG) 8, a channel number decoder 9, a subband setting control unit (BPCS) 10, a signal spectrum control unit (BSS) 11, a signal power control block (BMS) 12, a first modulator 13, a second modulator 14, digital frequency synthesizer (DSC) 15, frequency converters 16, output attenuator 17. Each of its clock outputs FOC 1 is connected respectively to the second inputs of the DSC 15 of each simulation channel, outputs 1 to N of the transfer frequency of the FOC block 3 are connected to the second inputs of the frequency converter 16 with of the corresponding channel, outputs 1 to N KOCH 4 are connected to the third outputs of the frequency converters 16 of the respective channels. The first group of second inputs of the block KOCH 4 is connected respectively to the M outputs of the BUUP 10 of the first channel, the second group of second inputs of this block is connected to the M outputs of the BUUP 10 of the second channel, etc. The N-th group of the second inputs of this block is connected respectively to the M outputs of the BUUP 10 of the N-th channel 2.

 ZG 8 with one output is connected to the output 18 “permission of the external clock cycle” of block 6, which is also connected to the input “permission of the external clock of FOC 3, the other input of ZG 8 is connected to the output“ clock "of the VOC 3, the output of ZG 8 is connected to the inputs of the" clock " blocks БУУП 10, БУСС 11 and БУМС 12. The bus "subband setting data" 19 of block 6 is connected to the sixth input of the БУУП 10, the bus "clock data of the БУУП" 20 is connected to the first input of the БУУП 10, the bus "data address" 21 of block 6 is connected to the second inputs of blocks BUUP 10, BUSS 11 and BUMS 12. Bus "channel number data" 22 of block 6 is connected to the first input m of channel number 9 decoder, “synchronization” output 23 of block 6 is connected to the second input of channel number 9 decoder, bus “BUSS timing data” 24 of block 6 is connected to the first input of BUSS 11, bus “busMS timing data” 25 of block 6 is connected to the first input BUMS 12, the bus "data of the formation of the signal spectrum" 26 of block 6 is connected to the fourth input of the first modulator 13, the bus "data of the power setting" 27 of block 6 is connected to the fourth input of the second modulator 14.

 The first output of the channel number decoder 9 is connected to the third inputs of the BUUP 10, BUSS 11 and BUMS 12 blocks, the second output of the channel number decoder 9 is connected to the fourth inputs of the BUUP 10, BUSS 11 and BUMS 12 blocks, the third output of channel number 9 decoder is connected to the fifth input BUPP 10 and to the seventh input of the first 13 and second 14 modulators. The first, second, third, fourth and fifth outputs of the BUSS 11 are connected respectively to the first, second, third, fifth and sixth inputs of the first modulator 13. The first, second, third, fourth and fifth outputs of the BUSS 12 are connected respectively to the first, second, third, the fifth and sixth inputs of the second modulator 14, the outputs with 1 op M BUUP 10 are connected respectively to the fifth outputs of the frequency converter 16. The output of the first modulator 13 is connected to the first input of the DSC 15, the output of which is connected to the first input of the frequency converter 16, the output of the converter 16 s connected to the first input of the output attenuator 17, the second input of which is connected to the second output of the second modulator 14, the first output of the second modulator 14 is connected to the fourth input of the converter 16. The output attenuator 17 with its output, which is the output of the first simulation channel, is connected to the first input of the summing unit 5 whose output is the output of the simulator.

 A specific embodiment of the proposed simulator contains eight identical in composition and execution of the blocks and the relationships between the blocks of channels.

 The buses and outputs of block 6 are connected in parallel to all other channels of the simulator, respectively, to the first channel. The connection of the FOC 3 and FOC 4 blocks to the N-th channel is described above. The outputs of the remaining simulation channels are connected to the corresponding inputs of the summing unit 5.

 FOC 3 contains a crystal oscillator (KG) 28, the output of which is connected to the first input of the first logical element And 29, the second input of the first logical element And 29 is connected to the output of the inverter 30 and the input of the inverter 30 is connected to the first input of the logical element And 31. The second input of the logical AND element 31 is the second input of the “external clock resolution” of VF 3. The output of AND gate 29 is connected to the first input of OR gate 32, the output of gate AND 31 is connected to the second input of OR gate 32. Logical output OR 32 is connected through the first power amplifier 33 to the input of the third splitter 34, which has two outputs. The first through the first filter 35 and the second power amplifier 36 is connected to the fourth splitter 37 having two outputs, the first of which through the third filter 38, the third power amplifier 39 is connected to the input of the first splitter 40 having N outputs (N number of simulator channels). The second output of the third splitter 34 through the second filter 41, the fourth power amplifier 42 is connected to the fifth splitter 43 having M outputs, where M is the number of sub-bands of the operating frequency of the simulator. Each of the M outputs of the fifth splitter 43 is connected to the input of the corresponding reference frequency sensor (DOCH) 44, the number of such sensors M.

 The second output of the fourth splitter 37 through the (M + 1) DOCH 44 and the fifth power amplifier 45 is connected to the input of the splitter 46, which has N outputs. The outputs of the DOCH 44 are the outputs of the reference frequencies of the FOCH 3, the N outputs of the first splitter 40 are the "clock outputs" of the FOCH 3, the N outputs of the second splitter 47 are the outputs of the "transfer frequency" of the FOCH 3, the output of the logic element OR 32 is the output of the "beat" of the FOCH 3.

 The first and second splitters (40 and 47, respectively) are splitters of the microwave signal and are designed according to the scheme of a symmetrical power divider into N channels, splitters 34 and 37 are splitters of the microwave signal into two channels, with filters 35, 36 and at the outputs of the splitters 34 and 37 and 41 have a fairly narrow bandwidth.

 Consider the reference frequency switch KOCH 4, which contains M splitters 48, N switches 49 and N amplifiers 50.

 Each splitter 48 has one output and H outputs, and each switch 49 has one group of M inputs for transfer frequencies and another group of M inputs for control and one output. The splitters 48 and switches 49 are interconnected as follows. The first inputs of each splitter 48 are connected to the inputs from the first to the Mth of the first switch 49, the second inputs of each splitter 48 are connected to the inputs of the first to the Mth of the second switch 49, etc. The N outputs of each splitter 48 are connected to the inputs from the first through the Mth Nth switch 49. The outputs of the switches 49 are connected to the inputs of the respective amplifiers 50, the outputs of which form the N outputs of KOC 4, the inputs of the splitters 48 from 1 to the Mth are inputs of the KOC 4 for M transfer frequencies, the second inputs of KOCH 4 are the second groups of control inputs of the switches 49, and these control inputs form N groups of M inputs in each group.

 The splitters 48 are symmetric microwave power dividers and are made according to known schemes on strip lines.

 The switches 49 are made in the form of microwave power switches on p-i-n diodes controlled by current.

 Consider a frequency converter 16. It contains a first mixer 51, a microwave bandpass filter 52, a second mixer 53, a power amplifier 54, a controlled attenuator 55. Moreover, a controlled attenuator 55 is connected to the output of the mixer 51 through a bandpass filter 52, the output of which is connected to the first the input of the second mixer 53, the output of which is through a power amplifier 54, the output of which is connected to the first input of the splitter 56 having M outputs that are connected to the first M inputs of the switch 57, M outputs of which through the corresponding volts Other bandpass filters 58 are connected to the M inputs of the adder 59, the output of which through the power amplifier 60, which is the output of the frequency converter 16, is connected to the first input of the output attenuator 17, the output of which is the channel output. Moreover, the first input of the first mixer is the first input of the frequency converter 16 for connecting to the output of the DSC 15, the second input of the first mixer is the second input of the frequency converter 16 for connecting to the output of the FOC 3, the second input of the second mixer 53 is the third input of the frequency converter 16 for connecting to the outputs KOCH 4, the second input of the controlled attenuator 55 is the fourth input of the frequency converter 16 for connecting to the second output of the second modulator 14, the second M inputs of the switch 57 are the fifth input frequency converter 16. In its implementation of the blocks 51, 52, 53, 54, 55 may be formed, for example, just as blocks are made similar to the prior art device.

 The splitter 56 and the switch 57 are made similar to the splitter 48 and the switch 49. The adder is a passive microwave power splitter and is made according to known schemes on strip lines.

 The first modulator 13 contains interconnected random access memory (RAM) 61, a data switch 62, a register 63, current keys 64, and the RAM 61 has three inputs and one output "data" (in read mode). This output is connected to the first input of the data switch 62 and in recording mode is the fourth input of RAM 61. The input "address" of RAM 61 is the first input of the first modulator 13 for connecting to the first output of the BUSS 11, the read-write input of RAM 61 is the second input of the first modulator 13 for connecting to the second output of the BUSS 11, the input "selection" of RAM 61 is the third input of the modulator 13 for connecting to the third output of the BUSS 11, the input / output "data" of the RAM 61 is connected to the first input of the data switch 62. The second input is the "control" of the switch data 62 is the fifth input of the first modulator 13, the third input "signal spectrum data" of the data switch 62 is the fourth input of the first modulator 13, the data output of the switch 62 is connected to the first input of the register 63, the second input of which "write permission" is the fifth input of the first modulator 13 for connecting to the fifth output of the BUSS 11, the third input "recording in the WG" of the register 63 is the seventh input of the first modulator 13 for connecting to the third output of the decoder channel number 9, the output of the register data is connected to the input of the current keys 64, the output of which s is the output of the first modulator 13 for connection to a second input TSSCH 15. The number of current determined by the number of keys TSSCH control bits.

 RAM 61 is made in the form of a storage device on static ICs, for example, of type UM 61416A or UM6164B from UMC (USA) or domestic ICs of type K537 RU8.

 The data switch 62 is a conventional multiplexer built on the K531 or K555 series of ICs and performing the operation of switching two inputs to one output.

 Register 63 is a regular register with parallel input data recording and parallel output. It can be performed, for example, on IC type K531IR22 or K531IR23.

 Current keys 64 are key current amplifiers and can be performed according to well-known schemes on transistors or ICs.

 The second modulator 14 contains interconnected random access memory (RAM) 65, a data switch 66, a register 67, current keys 68, and the RAM 65 has three inputs and one output "data" (in read mode). This output is connected to the first input of the data switch 66 and in recording mode is the fourth input of RAM 65. The input "address" of RAM 65 is the input of the second modulator 14 for connecting to the first output of the BOOMS 12, the read-write input of the RAM 65 is the second input of the second a modulator 14 for connecting to the second output of the BUMS 12, the input "selection" of RAM 65 is the third input of the second modulator 14 for connecting to the third output of the BUMS 12, the input / output "data" of the RAM 65 is connected to the first input of the data switch 66. The second input is "control "data switch 66 is the fifth input of the second modulator 14, the third input of the "power setting data" of the data switch 66 is the fourth input of the second modulator 14, the data output of the data switch 66 is connected to the first input of the register 67, the second input of which "write permission" is the fifth input of the second modulator 14, for connecting to the fifth output of the BUMS 12, the third input "recording in the WG" of the register 67 is the seventh input of the second modulator 14 for connecting to the third output of the decoder channel number 9, the output of the "register" data is connected to the input of the current keys 68. Current keys 68 have two outputs. The first output is the first output of the second modulator 14 for connecting to the fourth input of the frequency converter 16, the second output of the current switches 68 is the second output of the second modulator 14 for connecting to the second input of the output attenuator 17.

 The execution of blocks of RAM 65, data switch 66, register 67 is similar to blocks 61, 62, 63 of the first modulator. As for the block of current keys 68, then in execution it is similar to block 64 of the first modulator. The number of current keys providing the first output of block 68 is equal to the number of control inputs M of the switch 57 of the frequency converter 16, and the number of current keys providing the second output of block 68 is equal to the number of control inputs of the output attenuator 17.

 The signal power control unit (BMS) 12 contains a timer 69, the output of which is connected to the first input of the processor 70, the first output of which is a clock for generating an address, which is connected to the input of the internal address generator 71, the output of which is connected to the third input of the address switch 72, the first input which is connected to the fourth output of the processor 70, and the second input "data address" of the address switch 72 is the second input of the BMS 12, the first input of the BMS 12 is the first input of the timer 69 to connect to the bus 25 "clock data BMS", the third input the BUMS 12 house is the third input “data recording permission” of the timer 69 for connecting to the first output of the channel number decoder 9, the second input of the timer 69 is the “BUMS” input for connecting to the ZG 8 output, the fourth input of the BUMS 12 is the second input “operation mode "processor 70, the first output of the BUMS 12 is the output" address "of the address switch 72, the second output of the BUMS 12 is the third read-write output of the processor 70, the third output of the BUMS 12 is the second output" RAM access "of the processor 70, the fourth output of the BUMS 12 is the sixth exit the data switch is "processor 70, the fifth output of the BOOMS 12 is the fifth output" write permission in the WG "of the processor 70.

 The signal spectrum control unit (BUSS) 11 contains a timer 73, a processor 74, an internal address shaper 75, an address switch 76. A timer output 73 is connected to the first input of the processor 74, the first output of which is “address generation clock” which is connected to the input of the internal address shaper 75 the output of which is connected to the third input of the address switch 76, the first input of which is connected to the fourth output of the processor 74, and the second input "data address" of the address switch 76 is the second input of the BUSC 11, the first input of the BUSC 11 measure 73 for connecting to the bus "clock data of the BUSS", the third input of the BUSS 11 is the third input "enable data recording" of the timer 73 for connecting to the first output of the decoder channel number 9, the second input of the timer 73 is the input of the BUSS clock for connecting to ZG 8 output, the fourth input of the BUSS 11 is the second input of the "operating mode" of the processor 74, the first output of the BUSS 11 is the output of the "address" switch address 76, the second output of the BUSS 11 is the third read-write output of the processor 74, the third output of the BUSS 11 is the second exit 'sampling Oh The memory "of the processor 74, the fourth output of the BUSS 11 is the sixth output of" managing data switches "of the processor 74, the fifth output of the BUSS 11 is the fifth output of the" write permission in the WG "of the processor 74.

 The subrange setting control unit (CUP) 10 comprises a timer 77, a processor 78, an internal address shaper 79, an address switch 80, RAM 81, a data switch 82, a register 83, a data decoder 84, current keys 85. The output of the timer 77 is connected to the first input of the processor 78, the first output of “a clock for generating an address” of which is connected to the input of the internal address generator 79, the output of which is connected to the third input of the address 80 switch, the first input of which is connected to the fourth output of the processor 78, and the second input of the “data address” of the switch Dresa 80 is the second input of the BUUP 10, the first input of the BUUP 10 is the first input of the timer 77 for connecting to the bus "clock data BUUP", the third input of the BUUP 10 is the third input "enable data recording" timer 77 for connecting to the first output of the channel number decoder 9, the second input of the timer 77 is the input "BUUP cycle" for connecting to the output of ЗГ 8, the fourth input of the BUUP 10 is the second input "operating mode" of the processor 78 for connecting to the second output of the channel number 9 decoder, the fifth input of the BUUP 10 is the third input record "register 83 for connecting to the third output of the decoder channel numbers 9, the sixth input of the control unit 10 is the third input" data "of the data switch 82 for connecting to the bus 19" data setting subband "interface 7, the second output" selection "of the processor 78 is connected to the third input RAM 81, the third read-write output of the processor 78 is connected to the second input of the RAM 81, the fourth output of the “address switch control” of the processor 78 is connected to the first input of the address switch 80, the fifth write-to-write output of the processor 78 is connected to the second register input 83, she the stable output “data switch control” of the processor 78 is connected to the second input of the data switch 82, the output “address” of the address switch 80 is connected to the first input of the RAM 81, the input / output of the RAM 81 is connected to the first input of the data switch 82, the output of the data switch 82 is connected to the first input of the register 83, the output of the register 83 is connected to the input of the decoder 84, the output of the decoder 84 is connected to the input of the current keys 85, the output of which is the output of the control unit 10 for connection to the second inputs of the COC.

 The number of current switches is determined by the number of digits for the control of the COCH.

 The timer 69, 73 and 77 are made equally in the form of programmable counters with a parallel input for recording data on the IC, for example, type K531IE17.

 The shaper of the internal address 71, 75 and 79 is a counter with serial input and parallel output and can be performed on type K531IE17 ICs.

 The address switch 72, 76 and 80 and the data switches 66 and 82 are made in the same way as the data switch 62, but differ in the number of inputs and outputs in accordance with the capacity of the addresses and data.

 RAM 61, 65 and 81 are made the same.

 The register 63, 67 and 83 are made as well as the register 63, but may differ in the number of inputs and outputs in accordance with the capacity of the data.

 The decoder 84 is a conventional decoder, providing a representation of the binary code supplied to its input, in the form of a positional code at its output, and can be performed on serial ICs, for example, K555ID3 or the like.

 Current keys 85 are key current amplifiers and can be performed according to well-known schemes on transistors or ICs.

The simulator works as follows. When power is applied to the blocks of the simulator, FOC 3 generates output signals at all of its outputs. The quartz oscillator 28 generates a meander signal at its output, which is fed to the first input of the And 29 circuit, to the second input of this circuit, in this case, a signal with a logic level of 1 comes from the output of the inverter 30, which ensures the arrival of the meander signal to the output of the And 29 circuit. Since the input of the inverter 30 in this case receives a logic zero signal from block 6 and a signal with a logic zero level will be present at the first input of the And 31 circuit, which prevents the signal from passing through the circuit 31 coming to the second input of the FOC from outside shnogo generator. Thus, the second input of the OR 32 circuit will receive a signal with a logic zero level from the output of the And 31 circuit, and the square wave signal of the crystal oscillator from the output of the And 29 circuit will come to the first input of this circuit. The signal is output from the output of the OR circuit 32 " the clock cycle of the FOCH 3 and to the power amplifier 33 and branches into two in the splitter 34. From the first output of the splitter 34, the signal enters the clock frequency generating circuit for the DSC 15 and the frequency for the first conversion (frequency up) in the frequency converters 16 of each channel, with the second output of the splitter 34, the signal enters the frequency grid for the second signal conversion (transferring the signal to a predetermined working range) in the frequency converter 16. From the second output of the splitter 34, the signal is fed to a broadband filter 41, which ensures the passage of harmonic components of the crystal oscillator in the band of specified frequencies from f _min to f _max, from the output signal of the filter 41 to an amplifier 42 and then to a splitter 43 which is a symmetrical power divider to m by the number of formed reference frequency in the grid. From each output of the splitter 43, the signal is supplied to the corresponding reference frequency sensor 44, which is a series-connected narrow-band filter tuned to a given frequency, for example, f _min , a valve and a power amplifier. The number of reference frequencies, and, consequently, the DOCH 44 is determined by the working frequency bandwidth of a given range and the tuning bandwidth of the DSC 15 during signal generation and is determined by the formula:
M f _mimic / f _css ,
Where
f _imitates the operating frequency range of the simulator;
f _DSCH operating frequency range DSC.

 Thus, from the output of the DOCH 44, which are the outputs of the FOC 3, the grid of reference frequencies with the number M equally spaced from each other by the width of the working frequencies of the DSC 15 is supplied to the first inputs of the FOC 4.

 The first output of the splitter 34, the signal goes to the input of the low-pass filter 35, then to the amplifier 36 and to the splitter 37. From the first output of the splitter 37, the signal goes to the input of the narrow-band amplifier 38, tuned to the calculated harmonic component of the crystal oscillator, providing the necessary clock frequency 15 after filter 38, the signal at the frequency of the extracted harmonic is fed to amplifier 39, and then to splitter 40, which is a power divider by N, according to the number of channels of the simulator. The number of simulator channels determines the maximum number of signal sources simulated at the same time, provided that these signals coincide in time. The outputs of the splitter 40 are the outputs of the FOC 3 and are connected to the corresponding inputs of the channels of the simulator for clocking DSC 15.

 From the second output of the splitter 37, the signal is supplied to M + 1 DOCH 44 and through the power amplifier 45 to the splitter 46. Moreover, the narrow-band filter in M + 1 DOCH 44 provides the separation of the harmonic component from the signal spectrum of the crystal oscillator 28, which is necessary for the first conversion of the signal into frequency converter 16. The outputs of the splitter 46 are the outputs of the FOC 3 and are connected to the corresponding inputs of the simulator channels to transfer the signal to the high frequency region (second input of the frequency converter 16).

 The signals of the reference frequency network from the outputs of the FOCH 3 are supplied to the first M inputs of KOCH 4 and, respectively, each to the input of its splitter 48, the number of which is KOCH 4 M. From the outputs of the splitters 48, the signals of the reference frequencies are fed to the M inputs of each of the N switches 49. So, the signal of the first reference frequency from the first output of the splitter 48 goes to the first input of the first switch 49, the signal of the second reference frequency from the first output of a second splitter 48 goes to the second input of the first switch 49 etc. finally, the signal of the Mth reference frequency from the first output of the Mth splitter 48 is fed to the Mth input of the first switch 49. Also, the signals of all other reference frequencies from the outputs of the splitters 48 are fed to the corresponding inputs of the other switches 49.

 The switch 49 represents M controlled gates and N adders (splitters). The first inputs of the gates receive reference frequency signals from 1 to Mth, and the second inputs receive control signals from the control unit 10, unlocking only one valve at any given time, determined by the simulator program. The output of each valve with the corresponding input of the splitter and the logic of the switch 49 is that, depending on the number of the valve opened by the control signal, the output of the switch will be a signal of a given reference frequency. From the outputs of the switch, the signals of the reference frequencies are fed to the inputs of N power amplifiers 50, the outputs of which are outputs of KOCH 4, through which they are fed to the third inputs of the frequency converters 16 of each channel of the simulator for signal generation during the second signal conversion on the mixer 53.

 FOCH 3 and KOCH 4 splitters, FOCH 3 filter and KOCH 4 splitters can be made, for example, in the form of passive elements on strip lines taking into account the minimum signal power loss. The controlled valve can be performed on microwave diodes according to traditional schemes, which must take into account the requirements for the speed of switching the reference frequencies in the simulator, minimum losses and maximum isolation between the channels.

The simulator of radio sources can work in several modes:
in the mode of direct data entry into the channel about the parameters of the simulated signal;
in the mode of entering data into RAM BUUP, BUSS and BUMS of each channel;
in the mode of simulating signals according to the data recorded in the RAM of each channel.

 Moreover, the modes can be carried out individually and in various combinations. For example, data from 6 is recorded in one of the channels, while the others at this time work in the simulation mode according to the data read from RAM, or they reproduce the signal according to the data entered earlier in the registers of the control unit, the first and second modulator of any simulator channels.

Consider the simulator in direct mode from the computer data on the parameters of the simulating signal in a particular channel. In this mode, the simulator operates as follows. From block 6 in the form of a code on the bus 21 "channel number data" at the input of channel number decoders 9 of all channels of the simulator, the address of the selected channel and the specified operation mode are received. Each decoder of channel number 9 has an input address analysis circuit that compares the address code arriving at its input with the code that is assigned to this channel in the simulator and is set in this circuit using the built-in switches or by wiring the inputs of the comparison circuit. If the codes match from the second output of the decoder, the channel numbers 9 to the fourth inputs of BUMS 12, BUSS 11 and BUUP 10, which are the second inputs of the processors 70, 74 and 78, respectively, information about the selected operating mode of the channel is received. In this case, the operating mode according to the data directly coming from 6. A signal (0 or 1) is generated at the sixth outputs of the processors 70, 74 and 78, which is fed to the second inputs of the data switches 82, 62, and 66 of the control unit 10, the first and second modulators (13 and 14), respectively, and allowing passage through these switches of data coming from 6:
on the bus 18, "subband setting data" is supplied to the sixth input of the control unit 10, which is the third input of the data switch 82;
on the bus 25 "signal spectrum data" is supplied to the fourth input of the first modulator 13, which is the third input of the data switch 62;
on the bus 26, “power setting data” is supplied to the fourth input of the second modulator 14, which is the third input of the data switch 66.

 Data in the form of a code from the outputs of data switches 82, 62, and 66 are supplied to the first inputs of registers 83, 63, and 67, respectively. On the bus 22 "synchronization from the computer" to the second input of the data decoder in the registers. At the third output of the channel number decoder 9, a logical signal level is formed, which, arriving at the fifth input of the control unit 10 and, respectively, at the third input of the register 83, provides data on the subband in this register, arriving at the seventh inputs of the first and second modulators, and respectively, to the third inputs of registers 63 and 67, it provides data on the spectrum of the signal and its power.

 From the output of register 83, data in the form of a binary code is sent to a decoder 84, from the output of which a signal in the form of a positional code defining a given subrange is supplied to current switches 85, which are current amplifiers and generate a signal sufficient to control switches 49 and 57, for which, from the first output of current keys 85, the signal is supplied to the first group of second inputs KOCH 4 and to the fifth input of the frequency converter 16. In accordance with the position code, a signal with a frequency corresponding to the output of the first switch 49 th subband.

 From the output of the register 63, the binary code is fed to the input of the current keys 64, at the output of which a code signal is generated, the level and power of which is sufficient to control the DSC 15 when applied to its first input. At the output of the DSC 15, a low carrier frequency of the signal with amplitude and phase parameters is formed. This signal is fed to the first input of the mixer 51 of the frequency converter 16. From the output of the register 67, the binary code is fed to the input of the current switches 68, at the output of which a code signal is generated, the voltage and current levels of which are sufficient for control from the first output by a controlled attenuator 55, and with the second output by the output attenuator 17. The difference in the delays in the formation of the signal in the channel after recording its image in the registers in KOCH 4, in the DSC 15 and in the frequency converter 16 can, if necessary, be compensated by introducing Derzhko controlled in the control circuit and the output attenuators 55 and 17, respectively, for example, the register 67 output.

 Upon receipt of the code from the output of register 63 to the second input of the DSC 15 of the clock signal from one of the outputs of the clock frequency FOC 3, the output of the DSC 15 generates a signal at a low carrier frequency with the specified amplitude and phase parameters. This signal is fed to the first input of the frequency converter 16, which is the first signal input of the mixer 51. The signal fed to the second input of the converter 16 from one of the outputs of the transfer frequency of the FOC 3 is a local oscillator signal and goes to the second input of the mixer 51. Thus, at the first the mixer 51 of the frequency Converter 16 the signal is transferred to the microwave region. From the output of the mixer 51, the signal through a band-pass filter 52 is fed to the first input of the controlled attenuator 55, the control code is supplied to the second inputs of this attenuator through the fourth input of the converter from the output of the current keys 68 of the second modulator 14, which sets the signal power at the output of this attenuator at the level corresponding to this code . From the output of the controlled attenuator 55, the signal is supplied to the first signal input of the second mixer 53, and the second heterodyne input of this mixer receives a signal from the third input of the frequency converter 16 from the reference frequency output KOCH 4 corresponding to this channel. At mixer 53, the signal is transferred to a lower frequency.

 This double conversion of the signal frequency provides lower noise and interference of spurious components at the output of the simulator.

 From the output of the second mixer 53, the signal is supplied through a power amplifier 54 to the input of the splitter 56, from each of the M outputs of which the signal divided by M power is supplied to the first corresponding inputs of the switch 57, the position code from the output of the control unit for the control of the output of the switch is received at the second input of this switch on which the signal will be generated. Through the corresponding bandpass filter 58, the signal is fed to the input corresponding to the position code of the adder 59. From the output of the adder 59, which is the output of the frequency converter 16, the signal is fed through a power amplifier 60, compensating for signal loss in the splitter 56, switch 57, the bandpass filter 58 in the adder 59, to the first input of the output attenuator 17. The second input of the attenuator 17 receives a code signal from the second output of the current keys 68 of the second modulator 14, which sets the final power level and mitigated signal source. From the output of the channel, the signal enters the summing unit 5, which is a passive microwave element and on which there is a branching of all signals simulated in other channels with minimal influence on each other.

 Microwave power control with two attenuators provides the required dynamic range of the output signal in multi-channel operation.

 Consider the work of the simulator in the data recording mode in RAM BUUP, BUSS and BUMS. Work in this mode is that the image (portrait) of the signal in digital codes is entered in the OZ of the indicated blocks. Moreover, the addressing and generation of codes is performed in the computer 6 and the transmission of addresses and data to any channel of the simulator, defined by the user, is carried out from block 6. The channel for writing data to RAM and its operation mode is selected by setting “channel number data” on bus 22 interface 7 code of a given channel and operating mode. This code is fed to the first input of the channel number decoder 9.

 At the first and second outputs of the decoder of a given channel, commands are formed that determine the operation of the channel in this mode. These commands come from the first output to the inputs of the timers 69, 73, and 77, and from the second to the second inputs of the processors 70, 74, and 78 of the BUMS 12, the BUSS 11, and the BUUP 10, respectively. A signal (1 or 0) is generated at the sixth outputs of the processors 70, 74, and 78, which is fed to the second inputs of the data switches 82, 62, and 66 of the control unit 10, the first and second modulators (13 and 14), respectively, and allows the data to pass through these switches coming from block 6.

on the bus 19, “subband setting data” is supplied to the sixth input of the control unit 10, which is the third input of the switch 82;
on the bus 26, "signal spectrum data" is supplied to the fourth input of the first modulator 13, which is the third input of the switch 62;
on the bus 27, "power setting data" is supplied to the fourth input of the second modulator 14, which is the third input of the switch 66.

 From the fourth outputs of the processors 70, 74 and 78, the signal is supplied to the second inputs of the address switches 80, 76 and 72 of the BUUP 10, the BUSS 11 and the BUSMS 12, respectively, and allows the addresses passing through the switches from the unit 6 to the “data address” bus 21 to second inputs of these blocks.

 From the outputs of the data switches 82, 62 and 66, the data describing the waveform in this sample is fed to the inputs / outputs of the corresponding RAM 81, 61 and 65.

 From the third outputs of the processors 70, 74 and 78, signals, for example, with a logic zero level, arriving at the second inputs of RAM 61, 65 and 81, respectively, set these RAMs to the data recording mode.

The signal with the level of a logical unit, coming from block 6 at the output 23 "synchronization from the computer" to the second input of the channel number decoder 9, changes the code on its second output and, in accordance with it, the processors 70, 74 and 78 form signals on their second outputs, arriving at the third inputs of the corresponding RAM and at which data arriving from the unit 6 is also written to the RAM at the address given from block 6; A command is generated at the first output of the channel number decoder 9 by which data on clock frequencies is recorded e reading the image (portrait) of the signal in the timers 69, 73 and 77 of BUSMS 12, BUSS 11 and BUUP 10, respectively, on the buses:
25 "BUMS timing data";
24 "BUSS timing data";
20 "BUUP clock data."

 Thus, changing the address and data and recording them sequentially by a signal received via the "synchronization" bus from the RAM unit 6 of a given channel, data on the parameters of the signal that changes in time are entered.

 It can also be written to any other channel of the simulator.

 In the mode of simulating signals according to the data recorded in RAM, the work is performed as follows.

The channel is selected in the same way as in the other two modes of the simulator, on the bus 22 "channel number data". In this case, processors 70, 74, and 78 provide:
from the third outputs, the commands arriving at the second read / write inputs of the RAM 61, 65, and 81 and switching their read mode;
from the fourth outputs of the command switching the address switches 72, 76 and 80 so that through them addresses from the outputs of the shapers of the internal address 71, 75 and 79, respectively, are supplied to the address inputs of the RAM 61, 65 and 81;
from sixth outputs, commands switching data switches 62, 66 and 82 so that through them the first inputs of registers 63, 67 and 83 receive data from the inputs / outputs of RAM 61, 65 and 81, respectively;
from the first outputs of the command, allowing the formation at the outputs of the shapers of the internal address 71, 75 and 79 of the next address;
from the second outputs of the RAM sample command 61, 65, and 81, respectively, set these RAMs to the input / output data output mode;
from the fifth outputs of the command to write data to registers 63, 67 and 83.

 Moreover, the commands generated by the processor on the third, fourth and sixth outputs are set for the entire duration of this mode in the channel.

 The commands generated by the processors for the first, second and fifth outputs are formed sequentially one after another in the above sequence (each subsequent one does not necessarily cancel the previous one) cyclically with the tempo set by each of the timers 69, 73 and 77.

 The beginning of the channel in this mode is provided by the signal supplied to the second input of the channel number decoder 9 from the computer from the output 23 "synchronization" from block 6.

Thus, after the signal from the computer arrives at the second input of the decoder channel number 9 from the outputs of each of the shapers of the internal address 71, 75 and 79, through each switch of the address 72, 76 and 80, the initial address will go to the address inputs of RAM 61, 65 and 81. Then on the inputs "selection" of each RAM will receive commands from the second outputs of each of the processors 70, 74 and 78, providing the appearance at the inputs / outputs of RAM:
subband data from RAM 81 as a binary code;
data on the initial amplitude and phase of the spectral components of the signal at a low frequency from RAM 61;
data on the initial level of output signal power from RAM 65.

 Through the corresponding data switches 62, 66 and 82, information about the initial parameters of the generated signal is fed to the first inputs of the registers 63, 67 and 83. Then, at the fifth outputs of the processors 70, 74 and 78, commands are generated that go to the second inputs of the registers 63, 67 and 83 respectively.

 Further operation of the simulator channel for signal generation does not differ from that described in the first mode of operation.

 Despite the fact that timers 69, 73 and 77 can be programmed to work with different clock frequencies, the use of the same master oscillator in the channel provides synchronous change in signal parameters, since data are written to the registers on the same pulse edge this generator.

 Having enough RAM and using devices such as VDS-3125 from Sqited Electronics (USA) as the DSP, you can program the channel by creating a DSC output that simulates the spectral composition of almost any signal, and quickly switch the reference frequencies generated by the FOC 3, in KOCH 4 and changing the output power of the signal according to any user-defined law in the frequency converter 16 and at the output of the output attenuator 17 allows you to simulate almost any signal source, taking into account the variety of waveforms a, changing operating modes, such as tuning the carrier frequency, changing the parameters of frequency, amplitude, phase, pulse modulation, phase-code manipulation, etc. changes in the parameters of rotation or switching of antenna systems, changes in the parameters of radiation patterns of antenna systems and the laws of movement of the carrier of the signal source in real time.

 Pulse modulation can be carried out by analogy with the prototype, for which a key stage can be connected between the output of the DSC 15 and the input of the mixer 51 of the frequency converter 16 so that its first input is connected to the output of the DSC 15, and the second control input is connected to the input of the pulse modulator, which is a programmable timer that generates at its output a resolving level in time equal to a given pulse duration. The parameters of the pulses can be set from RAM, the data in which are written from the computer through a special bus in the interface. For example, by analogy with BUUP 10.

 In the same way, each of the N channels of the simulator is operated on the outputs of which signals with user-defined parameters of various sources are generated. Moreover, intentionally, or by virtue of probabilistic laws, the number of signals coinciding in time, in the general case, can be equal to the number of channels, i.e. N.

 In this mode of operation of the simulator, commands can be programmatically provided that reset the internal address formers after the corresponding code from block 6 to the initial state and commands that stop the channel without resetting the internal address formers, which allows the so-called start-stop operation.

 For a clearer synchronization of the simulation of the signal situation in complex scenarios of the behavior of signal sources, it is possible to operate all the channels from one master oscillator. In this case, the second input of the master oscillator 8 of each channel from the output 18 "permission of the external clock" from block 6 receives a signal that allows the output of the 3G 8 output clock frequency, which is formed at the output "clock" FOC 3 and goes to the first inputs of 8 all channels of the simulator.

 It is necessary to take into account the ability to simulate sources with a large number of operating modes according to complex algorithms, recording the simulation data sequentially in several channels and organizing their work in such a way that without interruption for writing new data to RAM from block 6 after this data has been completely read from one channel RAM, this channel terminated, and immediately began reading data about the parameters of the same signal source from the RAM of another channel.

The processor in the BUUP 10, the BUSS 11 and the BUMS 12 are generally presented in the block diagram of FIG. 1. It consists of a control circuit 86, the first input of which from the second input of the processor “mode” receives a code about the selected mode of operation from the second output of the channel number decoder 9, the second input, which is the first input of the processor “clock”, receives clock pulses, the first input of the control circuit 86 is connected to the first input of the address counter 87, the second output of the control circuit 86 is connected to the first input of the trigger 88, the third output of this circuit is connected to the second input of the command register 89, the fourth output of this circuit is connected to the first m is the input of the reset circuit 90, the second input of the reset circuit 90 is the processor mode input, the third input of this circuit is connected to the fourth output of the command register 89, the first output of the reset circuit 90 is connected to the reset input of the trigger 88, the second output of the reset circuit is connected to the reset inputs of the address counter 87 and the instruction register 89, the output of the address counter 87 is connected to the second input of the ROM address of the commands 91, the first input of the ROM address of the commands 91 is connected to the processor input “mode”, the third input is the “sample” of ROM of the commands 91 connected to the output trigger 88, the output of the ROM commands 91 connection the first input of the instruction register 89, three outputs of which are:
the first is the first output "address generation cycle" of the processor;
the second second output is "RAM access" of the processor;
third fifth output is "write permission in Pr" processor.

The other three outputs of the processor can be formed from the code coming from the decoder of the channel number 9 to the input "processor" mode:
third read / write RAM output of the processor;
the fourth output is "address switching resolution" of the processor;
sixth output "permission data switching" processor.

 The processor operates as follows. Upon receipt of the “mode” of the enabling code at its input, the control circuit 86 begins to generate pulses sequentially at its outputs. The pulse from the first output, arriving at the first input of the address counter 87, generates a code at its output, which is fed to the second input of the ROM of commands 91. This code and the code received at the first input of the ROM of commands 91 from the processor mode input is the full address ROM of the commands 91. The pulse from the second output of the control circuit 86, arriving at the first input of the trigger 88, provides a signal at its output, which, entering the "sample" ROM of the commands 91, reads from it the corresponding command of the given mode, which is received at the first input register com 89. Pulse input with the third control circuit 86 is supplied to the second input of the instruction register 89 by writing the command into it. From the output of the register of commands 89 commands are sent to the outputs of the processor. From the fourth output of the control circuit 86, the pulse through the first output of the reset 90, is fed to the input "reset" of the trigger 88, ensuring its reset to its original state. After the cycle of generating the necessary commands in the specified mode is completed, the command register is written to the command register 89, which, upon output from the output of this register to the third input of the reset circuit 90, provides a pulse from the fourth output of the control circuit 86 to generate reset pulses at its first and second outputs, which provides resetting to the initial state of the address counter 87, trigger 88 and the instruction register 89. In this simulator, such a processor provides the necessary cycle for reading one discrete signal image from RAM BUUP 10, BUSS 11 and 12 YMC three full stroke operation control circuit 86.

 In the mode of writing data to RAM from block 6, the processor generates the corresponding commands for the third, fourth and sixth outputs, setting the corresponding operating modes of the RAM, address and data switches in BUUP 10, BUSS 11 and BUMS 12 and the command "RAM selection" at its second output with every change of address in the computer.

 In the mode of simulating a signal from data directly set and written from a computer to the registers BUPP 10, BUSS 11 and BUSMS 12, the processor generates only a command at the sixth output "permission data switching". In this mode, cyclic instructions on the first, second and fifth outputs of the processor are not generated.

 The processor according to a similar scheme can be performed on serial ICs of series 530, 533, 564, 1500, etc. depending on the required performance. For example, the control circuit 86 may be performed according to the Johnson counter circuit, the reset circuit may be performed in the form of a combinational circuit on conventional logic elements performing the above reset functions. Other solutions can also be used that perform the same functions when the processor is running.

 DSC 15 can be performed according to the known block diagram shown in FIG. 10. The code of the frequency value and the initial phase is fed to the input of the frequency code register register 92, and the code of the current phase value value during phase modulation is fed to the input of the phase code 93 register. These codes are fed to the digital clock from the second input from the first BUSS 11 modulator. Write to the specified above, the DSC registers are made according to the clock pulse arriving at their respective inputs from the first input of the DSC 15 from the FOC 3. From the output of the code register 92, the code arrives at the first input of the code store 94, the second input of which receives the clock frequency from the first input of the DSC 15 The code accumulator digitally integrates frequency codes over time, also forming a phase incursion code from one clock pulse to another. At the output of the code accumulator 94, a binary code is generated, which goes to the first input of the adder 95, the second input of this adder receives a code of the current phase value (during phase modulation of the synthesized signal) from the output of the code register of the phase 93. From the output of the adder 95, the code goes to the functional converter 96, which is a ROM or RAM, or a combinational circuit with sine wave function values recorded therein. At the output of the functional converter 96, a code for counting the signal value corresponding to the input code is generated. A digital-to-analog frequency converter (DAC) 97 converts the code samples with a clock pulse to its clock input into an analog signal, which, through the output filter 98, which reduces the level of spurious components in the spectrum of the synthesized signal, is fed to the DSC 15.

 According to this scheme, the DSC can be performed on serial microcircuits of the 530, 1533, 1500 series, etc. In addition, at present, DSCs produced in a hybrid design based on AsGa crystals are being mass-produced, providing signal synthesis at a carrier frequency of up to 200 300 MHz with a resolution of up to 1 Hz, for example, ADS-2, ADS-4 from Sgiteg Electronics (USA) .

Claims (9)

 1. A radio signal source simulator comprising a code generator and a simulation channel, including a frequency synthesizer, the output of which is connected to the first input of the frequency converter, the output of which is connected to the first input of the power attenuator, and also including the first modulator, the output of which is connected to the first input of the synthesizer frequency and a second modulator, the first output of which is connected to the control input of the frequency converter, and the second output is connected to the control input of the power attenuator, characterized in that They include a reference frequency generator (FOC), a reference frequency switch (FOC), a summing block, and also N 1 identical simulation channels, and a subband setting control unit (BCU), a master oscillator (ZG), and a decoder are introduced into each of the N simulation channels the channel number, the first input of which is connected to the Data Channel Number Data bus of the code generator, the second input of which is connected to the Synchronization output of the code generator, and a signal spectrum control unit (BUSC) is introduced, the first input of which is connected to the bus "ass code encoder, the second BUSC input is connected to the Data Address bus of the code generator, the third BUSC input is connected to the first output of the channel number decoder, the fourth BUSC input is connected to the second output of the channel number decoder, the first BUSC output is connected to the first input of the first modulator, second output to the second input of the first modulator, the third output to the third input of the first modulator, the fourth output of the BUSS is connected to the fifth input of the first modulator, the fifth output of the BUSS is connected to the sixth input of the first modulator, the fourth input of the first modulate pa is connected to the bus "Data spectrum of the signal" of the code generator, the seventh input of the first modulator is connected to the third output of the channel number decoder, the output of the first modulator is connected to the first input of the frequency synthesizer, the second input of which is connected to the corresponding output of the clock frequency signal power control unit (BMS), the first input of which is connected to the bus "Clock data of the BMS" of the code generator, the second input of the BMS is connected to the bus "Data address" of the code generator, the third input of the BMS with the first output of the channel number decoder, the fourth input of the BUMS connected to the second output of the decoder of the channel number, the first output of the BUMS connected to the first input of the second modulator, the second output of the BUMS to the second input of the second modulator, the third output of the BUMS connected to the third input of the second modulator, the fourth output of the BUMS connected to the fifth input of the second modulator, the fifth output of the BUMS is connected to the sixth input of the second modulator, the fourth input of the second modulator is connected to the bus "Data power settings" code generator, the seventh input is second of the second modulator is connected to the fourth input of the frequency converter, the second output of the second modulator is connected to the second input of the output attenuator of the simulation channel power, M of the fifth inputs of the frequency converter are connected respectively to the M outputs of the control unit, the first input of the control unit connected to the bus "Timing data BUUP" of the code generator, the second input of the BUUP is connected to the bus "Data address" of the code generator, the third input of the BUUP is connected to the first output of the decoder channel numbers, the fourth input of the control unit is connected to the second output of the decoder of the channel number, the fifth input is connected to the third output of the decoder of the channel number, the sixth input is connected to the bus "Data setting subband" code generator, the output of the ZG is connected to the clock inputs BUMS, BUSS and BUUP, the outputs of the FOC and 1 through N are connected respectively to the second inputs of the frequency synthesizers of each channel, the M outputs of the reference frequencies of the FOC are connected to the first corresponding inputs of the FOC, the outputs of the frequency of the transfer of the Foc from 1 to N are connected to the second inputs of frequency generator of the corresponding simulation channels, outputs KOCH from 1 to N are connected to the third inputs of the frequency converters of the corresponding simulation channels, the second inputs of KOCH form N groups of M inputs in each, the inputs of the first group are connected respectively to the M outputs of the first simulation channel, the inputs of the second group connected respectively to the M outputs of the BUUP of the second simulation channel, etc. the inputs of the Nth group are connected respectively to the M outputs of the Nth simulation channel, the first input of the GP of each channel of the simulation is connected to the output "External clock resolution" of the code generator, the second input of the GP of each channel is connected to the output "Clock" of the FOC.  2. The simulator according to claim 1, characterized in that the reference frequency switch KOCH contains M splitters, each of which has one input and N outputs, N switches, each of which has a first group of M inputs, a second group of M inputs and one output, as well as N amplifiers, the first output of the first splitter connected respectively to the first input of the first switch, the first output of the second splitter connected to the second input of the first switch, etc. the first output of the Mth splitter is connected to the Mth input of the first switch, etc. The Mth output of the Mth splitter is connected to the Mth input of the Nth switch, the outputs of the switches are connected respectively to the inputs of N amplifiers, the outputs of which are N outputs of KOCH, the inputs of the splitters are the first inputs of KOCH, N groups of the second M inputs are second inputs KOCH.  3. The simulator according to claim 1, characterized in that the low-frequency reference driver includes the first and second splitters having N outputs each, the third and fourth splitters having two outputs each and the fifth splitter having M outputs, as well as a crystal oscillator, two AND gate, OR gate, inverter, five power amplifiers, three filters and M + 1 reference frequency sensors, the output of the crystal oscillator connected to the first input of the first AND gate, the second input of the first AND gate connected to by running the inverter, the input of the inverter is connected to the first input of the second logic element AND and is the first input "Resolution of the external clock" FOC, the second input of the second logic element And is the second input of the "external generator" FOC, the output of the first logic element And is connected to the first input of the logic element OR, the output of the second logical element AND is connected to the second input of the logical element OR, the output of the logical element OR through series-connected the first power amplifier, the third splitter, the first filter, the second power amplifier, the fourth splitter, the third filter, the third power amplifier is connected to the input of the first splitter, the second output of the fourth splitter through the (M + 1) th reference frequency sensor and the fifth power amplifier is connected to the input of the second splitter, the second output of the third splitter through the second the filter and the fourth power amplifier are connected to the input of the fifth splitter, the M outputs of which are connected respectively to the inputs of the M sensors of the reference frequency, the outputs of which are the outputs of the reference frequencies 1 to N of the first clock outputs of the splitter are FOCH, the outputs 1 to N of the second coupler form the outputs FOCH frequency transfer.  4. The simulator according to claim 1, characterized in that the control unit for setting the BOOP subbands includes a timer, a processor, an address generator, a switch, RAM data switch, an RG register, a data decoder, current keys, the timer output being connected to the processor clock input, the first the timer input is the first input of the control unit for connecting the bus of the code generator, the second input of the timer is the input for connecting the ZG output, the third input of the data recording enable timer is the third input of the control unit for connected to the first output of the decoder of the channel number, the second processor input is the operating mode input and the fourth input of the control unit, the first processor output is clock for generating the address and is connected to the address shaper input, the second output of the RAM Choice processor is connected to the third RAM input, the third output The "read-write" processor is connected to the second RAM input, the fourth output of the "Switching permission" processor is connected to the first input of the address switch, the fifth output of the processor "Writing to register" is connected to to the second input of the register, the sixth output “Data Switch Management” is connected to the second input of the data switch, the output of the address generator is connected to the third input of the address switch, the second input of which is the second input of the control unit, the address “RAM Address” of the address switch is connected to the first input of RAM, the input - RAM data output is connected to the first input of the data switch, the third input of the data switch is the sixth input of the control unit, the output of the data switch is connected to the first input of the register, the output of which is connected to the input of the data decoder x, the third input "Record in the WG" of the register is the fifth input of the control unit; the output of the data decoder is connected to the input of current keys, the output of which is the output of the control unit.  5. The simulator according to claim 1, characterized in that the control unit for the address spectrum of the BUSS signal comprises a timer, a processor, an internal address shaper, an address switch, the timer output being connected to the processor clock input, the first timer input is the first BUSS input, the second timer input is a clock input for connecting a ЗГ, the third input “Data recording permission” of the timer is the third input of the BUSS, the second input of the processor is the fourth input of the BUSS, the first output of the processor is connected to the input of the internal Resa, the second output of the processor “Sample RAM” is the third output of the BUSS, the third output of the “Read-write” processor is the second output of the BUSS, the fourth output of the “Switching permission” of the processor is connected to the first input of the address switch, the fifth output of the processor is “Writing permission to the RG” is the fifth output of the BUSS, the sixth output "Management of the data switch" is the fourth output of the BUSS, the output "Address" of the internal address generator is connected to the third input of the address switch, the output of which is the output of the BUSS, the second input is "Adr The eu from the code generator "address switch is the second input of the BUSS.  6. The simulator according to claim 1, characterized in that the first modulator contains RAM, a data switch, a register and current keys, and the input "Address" of the RAM is the first input of the first modulator, the input "Read-write" RAM is the second input of the modulator, input The RAM “sample” is the third input of the first modulator, the “Data” input-output of the RAM is connected to the first input of the data switch, the second “Control” input of which is the fifth input of the first modulator, the third input of the “signal spectrum data” of the data switch is the fourth input of of the first modulator, the output “Data” of the switch is connected to the first input of the register, the second input “Write permission” of the register is the sixth input of the first modulator, the third input “Register” of the register is the seventh input of the first modulator, the output of “Data WG” is connected to the input of current keys whose output is the output of the first modulator.  7. The simulator according to claim 1, characterized in that the BUMS signal power control unit comprises a timer, a processor, an internal address shaper, an address switch, the first timer input being the first input of the BUMS, the second timer input being the "Clock" and the fifth input of the BUMS, the third input "Permission to write data to the timer" is the fourth input of the BUMS, the timer output is connected to the first "Clock" input of the processor, the third input "Operation mode" is the fourth input of the BUMS, the first output "Clock for forming the address" of the processor is connected to the input ode to the internal address generator, the second output of the processor “Sample” RAM is the third output of the BUMS, the third output “Read-write” of the processor is the second output of the BUMS, the fourth output is “Switching permission” of the processor connected to the first input of the address switch, the fifth output of the processor is “Writing permission” in the RG "is the fifth output of the BUMS, the sixth output" Data switch management "of the processor is the fourth output of the BUMS, the output" Address "of the internal address generator is connected to the third input of the address switch, the output is cerned Bums is first output, a second input of "address from the set point codes" switch address is the second input Bums.  8. The simulator according to claim 1, characterized in that the second modulator contains RAM, a data switch, a register and current keys, and the input "Address" of the RAM is the first input of the second modulator, the input "Read-write" RAM is the second input of the second modulator, RAM sample input is the third input of the second modulator, and RAM data input-output is connected to the first input of the data switch, the second control input of which is the fifth input of the second modulator, the third input of the power setting data of the data switch is the fourth input tue of the modulator, the “Data” output of the switch is connected to the first input of the register, the second input “Write permission” of the register is the sixth input of the second modulator, the third input of “Register” of the register is the seventh input of the second modulator, the output of “Data WG” is connected to the current input keys, the first output of which is the first output of the second modulator, the second output of the current keys is the second output of the second modulator.  9. The simulator according to claim 1, characterized in that the frequency converter of each channel contains first and second mixers, a microwave bandpass filter, a controlled attenuator, first and second power amplifiers, a splitter with M outputs, a switch with M x 2 inputs and M outputs and an adder with M inputs, the output of the first mixer through a microwave bandpass filter connected to the first input of the controlled attenuator, the output of which is connected to the first input of the second mixer, the output of which through the first power amplifier is connected to the input of the splitter, M outputs which through the low-pass bandpass filters is connected respectively to the M inputs of the adder, the output of which is connected to the input of the second power amplifier, the output of which is the output of the frequency converter, the first input of the first mixer is the first input of the frequency converter, the second input of the first mixer is the second input of the frequency converter , the second input of the second mixer is the third input of the frequency converter, the second input of the controlled attenuator is the fourth input of the converter frequency, the second switch M fifth inputs are input inverter.

Images