RU2092894C1 - Device for controlling access of terminal to data bus - Google Patents

Abstract

FIELD: information transmission. SUBSTANCE: device has two units of timers 3, 4, unit of mismatch comparators 5, unit of selector switches 1, unit of registers 2, two AND gates 6, 7. Device provides autonomous operations of terminal using shared- access protocols with carrier detection and prevention of collisions. It implements algorithm of generation of signal for permission of terminal access to data bus. Device provides self-test possibilities and dynamic recovery after fail. EFFECT: increased reliability. 7 dwg

Description

 The invention relates to the field of information transfer in multiplexed data exchange channels and can be used to control access of an autonomous terminal to a data bus based on a shared access protocol with carrier detection and collision avoidance.

 In FIG. 1 shows diagrams of a periodic operating mode of a tire using three terminals as an example; figure 2 diagrams of the aperiodic mode of operation of the tire on the example of three terminals; figure 3 is a structural diagram of a device for controlling access of a terminal to a data bus; figure 4 algorithm of the functional comparator; figure 5 is a functional diagram of a device for controlling access of a terminal to a data bus; figure 6 diagram of a functional comparator; in FIG. 7 an algorithm for restoring the health of a device for controlling terminal access to a data bus.

 The device is intended for use as a separate unit of an autonomous terminal of a multiplex information exchange channel with distributed control of a communication channel (MKIO RU). MKIO RU includes autonomous terminals (hereinafter referred to as terminals) and a data bus (1, 2, 3, 4). In such a channel, each terminal has autonomous access to the data bus with collision avoidance thanks to a special access protocol that is implemented by this device.

 The access protocol is based on three functionally dependent timers: a transmission timer, a synchronization timer, and a terminal timer.

 The terminal transfer timer starts at the moment it starts transmitting its own information to the bus and counts down the interval called the transmission interval of the TP, during which the terminal does not have the right to re-access the bus. The transmission interval is the same for all terminals connected by one data bus.

 The synchronization timer is triggered by the TC interval (pause synchronization), which is the same for all terminals connected by one bus. This timer is always triggered when there is a carrier on the data bus and when the vehicle interval has not yet been worked out.

 The terminal timer fulfills the TT interval (terminal pause) proportional to the number assigned to this terminal. Thus, the TT interval is unique for each terminal. The terminal timer starts only after the synchronization timer has been completed and is reset in all cases if there is a carrier on the data bus. The maximum CT interval must always be less than the TC interval set for this bus.

The terminal is allowed to access the bus only after all the timers have been worked out, i.e., three conditions must be met:
1) the countdown of its own transmission interval TP;
2) the period of time when there is no carrier on the bus should be greater than or equal to the TS interval, i.e. vehicle interval countdown is over;
3) after the end of the TC interval, a time should pass when there is no carrier on the bus equal to its own TT interval.

 Two data bus operating modes are possible: periodic and aperiodic.

 The operation of the bus in batch mode using the example of three terminals is shown in FIG.

 Suppose that when the power is turned on (time moment TO), the transmission timers TP1, TP2, TP3 and synchronization timers TC1, TC2, TC3 of the first, second and third terminals, respectively, have worked out their intervals, i.e. the conditions of claims 1 and 2 are satisfied (see above).

 After that, the timers TT1, TT2, TT3 of the first, second and third terminals are started. TT of the first terminal fulfills its interval first (moment T1), i.e. interval TT1 TT2 TT3. At time T1, the first terminal starts transmission. At the same time, its transfer timer TP1 is started, the synchronization timers TC1 and terminal TT1 are reset, as well as the timers TT2 and TT3 of the other two terminals. At the end of the transmission (time T2), the TT2 and TT3 timers and the synchronization timer TC1 of the first terminal are again allowed (TT1 cannot start, since TC1 did not count the synchronization interval after the end of the transmission by the first terminal). The first at time T3 will work the timer TT2 of the second terminal (because the synchronization pause is longer than the terminal pause of any terminal on this bus), after which the second terminal starts transmitting, etc.

 At time T6, the last (third) terminal completes the transmission. At this point, all synchronization timers and terminal timers are reset and the synchronization interval begins with three timers TC1, TC2, TC3, and then the TT interval (time T7). At the time of T8, the TT1 timer worked, however, the first terminal cannot start transmitting, because TP1 interval countdown is not yet completed. Transmission begins at time T9. At the beginning of the transmission of the first terminal, the spent terminals TT2 and TT3 of the other terminals are reset. After that, the second and third terminals, etc., get access to the bus one by one.

 With an increase in the amount of information transmitted in the bus, the bus is overloaded and, if the total duration of the messages, taking into account technological pauses, becomes longer than the set transmission interval, the bus goes into aperiodic mode of operation (see figure 2). In this case, the interval between transmissions of the same terminal exceeds the transmission interval of TP (the interval between the moments T1 and T8 in figure 2).

 The block diagram of the device for controlling access of the terminal to the data bus (Fig. 3) consists of a block of selector switches 1, a block of registers 2, two identical blocks of timers 3 and 4, a block of mismatch comparators 5, and two elements And 6 and 7.

 The block of selector switches 1 contains three groups of switches that allow you to set three eight-shot codes, each of which corresponds to a certain interval: the transmission interval TP, pause synchronization of the vehicle and the pause of the terminal of the CT. These codes go to the inputs of the timer block 3.

 The register block contains three identical eight-bit registers. These registers contain three codes that are equivalent to the corresponding eight-bit codes set in the selector switch block 1. Codes from the outputs of the registers are fed to the inputs of the timer block 4.

 Each block of timers 3 and 4 operates independently of each other and contains three schemes (timers) of time intervals ТП, ТС, ТТ, the values of which are defined in the groups of selector switches 1 and registers 2. Together, the blocks of timers 3 and 4 provide duplication of counting of each time interval . They have corresponding clock inputs 8 and 9, which receive pulses of the same frequency from two independent generators.

 At the input 10 of the device receives a pause signal indicating the absence of information transfer on the data bus. This signal is generated in the receiving part of the terminal and enters the blocks of timers 3 and 4, resetting the terminal timers and synchronization timers.

 During the pre-installation, eight-bit codes received at the information inputs 11, 12 and 13 from the system read-only memory (ROM) are recorded in the corresponding registers of the register block 2. Recording is performed by applying a signal to the corresponding input of the recording 14, 15 and 16.

 Each timer, after counting its interval, gives a signal to one of the three outputs of the block of timers 3 (4), received at the corresponding information input of the block of comparators 5.

 Block comparators 5 consists of three separate mismatch comparators. Each comparator measures the temporal mismatch between two duplicate signals coming from the block of timers 3 and 4. If the temporary mismatch is less than the set value, the comparator gives a signal to the corresponding output of block 5. Otherwise, there is no signal at the output of block 5, and an error signal is generated at the corresponding block 5 error output. This low-level signal, passing through the I7 element, is fed to the control output of the device.

имеет место условие достоверности интервала, отработанного дублируемыми таймерами, а в случае б)

условие недостоверного интервала.In FIG. 4 schematically shows the operation algorithm of the mismatch comparator. T1 and T2 are the compared intervals, and ΔТ is the specified mismatch time between the compared intervals. In case a)

there is a condition for the reliability of the interval worked out by duplicate timers, and in case b)

false interval condition.

 High-level signals from the outputs of block 5 are fed to the inputs of the And 6 element, at the output of which 18 a signal is issued for allowing the terminal to access the data bus. This signal enters the transmitting part of the terminal.

 A device for controlling access of the terminal to the data bus (Fig. 5) contains three groups of selector switches 19, 20 and 21, switch 22, three registers 23, 24.25, six comparators 26-31, six counters 32-37, three comparators 38 -40 mismatches, four triggers 41-44, nine elements AND 7, 45-52, four elements OR 53-56, six elements NOT 57-62, two clock inputs 8 and 9, pause flag input 10, three information inputs 11, 12,13, three recording inputs 14,15,16, inputs of initial setup 63 and reset of transmission permission 64, output of transmission permission 18 and control output 17.

 The synchronization timer of the block of timers 3 is built on the counter 32, the comparator 26, the elements AND 45, NOT 57, OR 53, trigger 42; transmission timer - on counter 33, comparator 27, AND elements 47, NOT 58, OR 54; the terminal timer on the counter 34, comparator 28, AND 48 and NOT 59 elements. The synchronization timer block of the timers 4 is built on the counter 35, comparator 29, AND 49, NOT 60, OR 55, trigger 44; the transmission timer on the counter 36, the comparator 30, the elements AND 50, NOT 61, OR 56; the timer of the terminal on the counter 37, the comparator 31, the elements And 51 and NOT 62.

 The mismatch comparator (Fig. 6) includes two counters 65 and 66, two triggers 67 and 68, eight AND 69-76 elements, two OR elements 77 and 78, two synchronization inputs 79 and 80, two information inputs 82, 82, output 83 and error output 84.

 The device operates as follows.

 During initial initialization, data from the system ROM of the terminal is supplied to information inputs 11, 12, 13. By applying signals to the corresponding inputs of record 14, 15, and 16, these data are recorded in registers 23, 24, and 25. Then, the signal fed to the input of the initial setup 63, sets the trigger 41, which leads to the installation of triggers 42 and 44 and to the appearance of high-level signals at the outputs 81 and 82 of the mismatch comparators 38 and 39.

 When there are no high level signals at the inputs 81 and 82 of the mismatch comparator, the counters 65 and 66 are in the reset state (see Fig. 6). At their inverse outputs there are high-level signals that support, respectively, the elements And 71, 69 and And 73, 70 in the open state. From the moment high-level signals appear at the inputs 81 and 82 of the mismatch comparator, the corresponding counters 65 and 66 begin counting the pulses arriving at their counting inputs from the corresponding synchronization inputs 79 and 80 of the mismatch comparator. High level signals from the output of the And 71 element and from the output of the And 73 element go to the inputs of the And 74 element. It opens, and the high level signal at its output sets the trigger 67 to a single state. A high level signal is also present at the output of the AND element 75, and thus a high level signal will appear at the output 83 of the mismatch comparator.

 From the moment the high-level signal arrives at the input 81 (82) of the mismatch comparator, the duration of the high-level signal at the output of the AND element 71 (73) is determined by the moment the low-level signal appears on the inverse output of the counter 65 (66), i.e. when the latter counts a certain number of pulses received at its counter input from the moment the signal arrives at input 81 (82). Then the counter 65 (66) is blocked by its own output signal received at the input of the element And 69 (70). Thus, the duration of the high level signal at the output of the element And 71 (73) is determined by the counting coefficient of the counter 65 (66) and the period of the clock pulses received at the synchronization input 79 (80) of the mismatch comparator. The duration of the high-level signal at the output of element 71 (73) corresponds to a predetermined value of the interval T in FIG. 4.

 Thus, after applying a signal to the input of the initial installation 63, high-level signals appear almost simultaneously at the inputs 81 and 82 of the comparators 38 and 39. The comparators are triggered, and high-level signals appearing at the outputs of the I 52 element appear at their outputs 83. These signals are, respectively, signs of reliable testing of the TS and TP intervals (the MOT moment in Figs. 1 and 2). At the input of the pause flag 10, a low level signal is present, signaling the presence of a pause on the data bus. Counters 32-37 begin counting pulses arriving at the corresponding clock inputs 8 and 9 of the device. The timer of the terminal with the lowest number ends the countdown of its interval (interval T0-T1 in Figs. 1 and 2). This occurs at the moment when the codes at the outputs of the counters 34 and 37 correspond to the set code at the outputs of the group of selector switches 21 and register 25. In this case, the comparators 28 and 31 are triggered and the high-level signals from the outputs of these comparators are sent to the elements NOT 59, 62 and to the inputs 81 and 82 of the comparator 40. The low-level signals from the outputs of the elements NOT 59 and 62 block the And 48 and 51 elements, respectively, which will stop the counters 34 and 37. Under satisfactory conditions (see above), the comparator 40. B res In the end, a high level signal appears at its output 83, the element 52 opens and a high level signal at its output resets the triggers 41, 42, 44, counters 33 and 36 through the And 46 element (if the switch 22 is turned off) and sets the trigger 43. At the output of this trigger, a transmit enable signal is generated, which is output to the device 18. The outputs 83 of the comparators 38 and 39 and the outputs of the element And 52 are formed of low level signals. The low level signal enters through the And 46 element to the direct reset inputs of the counters 33 and 36 of the transmission timers, which from this moment begin the countdown of the transmission interval. The high-level signal from the output of the transmission authorization 18 enters the transmitting part of the terminal, initiating the transmission of information by the first terminal to the data bus (moment T1 in Figs. 1 and 2).

 During the period of information transfer, the signal at the input of pause flag 10 at all terminals connected to the bus is at a high level. The counters 32, 34, 35, and 37 of the synchronization and terminal timers are in a reset state.

 After transmitting information from the transmitting part of the terminal, a high-level signal is sent to the reset enable reset input 64, which resets trigger 43. After a pause has occurred on the data bus, the pause flag signal at the input 10 of the device goes into a low level and remains in this state all the time a pause takes place (period T2-T3 in Figs. 1 and 2). From the moment this signal is set to low, the counters 32 and 35 of both synchronization timers begin to work. Counters 34 and 37 of both timers of the terminal cannot work, because the output 83 of the comparator 38 there is a low level signal.

During the interval T2-T3, according to a similar algorithm, it executes a terminal timer for the next terminal number, which then starts transmitting information to the data bus (period T3-T4). This will happen until the last terminal transfers its information. At this point in time (T6), triggers 42 and 44 and counters 32 and 35 of the synchronization timers for all timers are reset. The pause on the data bus is sufficient to trigger the synchronization timers of all terminals, triggers 42 and 44 will be set. High-level signals from the outputs of these triggers go to inputs 81 and 82 of the comparator 38. It is triggered, and a high-level signal from it the output 83 goes to the elements And 48 and 51. If there is no transfer on the data bus, the counters 34 and 37 of the terminal timers start counting the pulses arriving at their counting inputs respectively from the outputs of the elements And 48 and 51 (moment T7 in Fig. 1 and 2) . After the TT1 interval, the comparators 28 and 31 of the first interval are triggered. High-level signals from the outputs of these comparators, respectively:
1) stop the counters 34 and 37;
2) arrive at the inputs 81 and 82 of the comparator 40, at the output of which a high level signal will appear. If by this time the transmission timer has counted its TP1 interval, then a high level signal is also present at the output of the comparator 39. In this case, a high signal level will appear at the output of AND element 52 and the first terminal will be allowed to transmit information (moment T8 in FIG. 2). If the TP1 interval is not counted (moment T8 in Fig. 1), the transmission enable signal at the device output 18 will be absent. It will appear only at the moment T9, when the TP1 interval is counted by the transmission timer and a high level signal appears at the output of the comparator 39. Further, the cycle of transmitting information by the terminals to the data bus is repeated.

, при котором срабатывают компараторы рассогласования. Рассмотрим случай б), когда

. В этом случае имеет место сигнал низкого уровня на выходе ошибки 84 компаратора рассогласования (см. фиг. 6). Это происходит следующим образом. Сигнал высокого уровня, поступающий на любой из входов 81 и 82 компаратора рассогласования, проходя через элемент ИЛИ 77, поступает на вход сброса триггера 68 (см. фиг. 4б). После отсчета интервала Т любым из счетчиков 65 и 66 сигнал низкого уровня с их инверсных выходов, проходя через элемент И 72, поступает на один из входов элемента ИЛИ 78. На другой вход этого элемента поступает сигнал низкого уровня с выхода триггера 68. В результате на выходе элемента ИЛИ 78 появится сигнал низкого уровня, поступающий на выход ошибки 84 компаратора. В случае

этот сигнал будет отсутствовать, т.к. триггер 68 будет установлен в единичное состояние сигналом высокого уровня, поступающим на его вход установки с выхода 83 компаратора. Эта установка произойдет раньше появления сигнала низкого уровня на выходе элемента И 72 (см. фиг. 4а), что не приведет к появлению сигнала низкого уровня на выходе ошибки 84.Previously, the operation of the device was considered, suggesting that duplicate timers work out intervals that satisfy case a) in FIG. 4 when

at which mismatch comparators are triggered. We consider case b) when

. In this case, there is a low signal at the output of the error 84 of the mismatch comparator (see Fig. 6). This happens as follows. A high level signal supplied to any of the inputs 81 and 82 of the mismatch comparator, passing through the OR element 77, is fed to the reset input of the trigger 68 (see Fig. 4b). After the interval T has been counted by any of the counters 65 and 66, the low-level signal from their inverse outputs, passing through the And 72 element, is fed to one of the inputs of the OR element 78. The low-level signal from the output of the trigger 68 comes to the other input of this element. As a result, the output of the OR element 78 will receive a low level signal, which is output to the error output 84 of the comparator. When

this signal will be absent, because trigger 68 will be set to a single state by a high-level signal supplied to its installation input from the output of 83 comparator. This setting will occur before the appearance of a low level signal at the output of the And 72 element (see Fig. 4a), which will not lead to the appearance of a low level signal at the output of the error 84.

 The functional purpose of the device for controlling access of the terminal to the data bus and its scope determine the stringent requirements for its reliability. Given the complexity of the access protocol, a large number of terminals on one bus (up to 120), the use of MKIO RU in on-board systems, the requirement to increase the level of terminal operability is an urgent task. To solve it, it is necessary to use functional blocks in the terminal capable of self-monitoring and dynamic recovery of performance. These requirements are met by the device discussed here for controlling terminal access to the data bus.

 An algorithm for restoring the health of a device as part of a terminal is shown in FIG. 7. The low-level signal from the control output 17 of the device enters the terminal status register in which it sets the control bit of the device. The terminal controller analyzes this bit and, if set, executes the device reinitialization firmware to control the terminal’s access to the data bus.

Claims (1)

 A device for controlling access of the terminal to the data bus, containing six counters, six comparators, three registers, four triggers, three mismatch comparators, eight AND elements, four OR elements, six NOT elements, a switch, three groups of selector switches, and the device’s first clock input connected to the first inputs of the first, second, third AND elements and to the first synchronization inputs of the first, second and third mismatch comparators, the pause indicator input of the device is connected to the reset inputs the first, second, third and fourth counters, the input of the initial installation of the device is connected to the installation input of the first trigger, the reset enable input of the device is connected to the reset input of the second trigger, the output of which is the transfer enable output of the device, the second clock input of the device is connected to the first inputs of the fourth, of the fifth and sixth elements And with the second synchronization inputs of the first, second and third mismatch comparators, the first, second and third information inputs of the device are connected respectively, with the information inputs of the first, second and third registers, the outputs of which are connected respectively to the first inputs of the first, second and third comparators, the information outputs of the first, second and fifth counters are connected with the first inputs of the fourth, fifth and sixth comparators, respectively, the output of the fourth comparator is connected with the first input of the first OR element and the input of the first element NOT, the output of which is connected to the second input of the first AND element, the output of the sixth comparator is connected to the first input the house of the second OR element and with the input of the second element NOT, the output of which is connected to the second input of the second element AND, the output of the fifth comparator is connected to the first information input of the third mismatch comparator and the input of the third element NOT, the output of which is connected to the second input of the third AND element, outputs the first, third and second elements AND are connected respectively to the counting inputs of the first, second and fifth counters, the output of the first comparator is connected to the first input of the third OR element and to the input of the fourth element nta, the output of the second comparator is connected to the first input of the fourth OR element and to the input of the fifth element NOT, the output of which is connected to the second input of the fifth element AND, the output of the third comparator is connected to the second information input of the third mismatch comparator and the input of the sixth element NOT, the output of which connected to the second input of the sixth element And the outputs of the fourth, fifth and sixth elements And are connected respectively to the counting inputs of the third, sixth and fourth counters, the information outputs of which are connected with the second inputs of the first, second, and third comparators, respectively, the direct output of the first trigger is connected to the second inputs of the first, second, third, and fourth OR elements, the outputs of which are connected respectively to the installation input of the third trigger, the first information input of the second mismatch comparator, the input of the fourth installation trigger and the second information input of the second mismatch comparator, the direct outputs of the third and fourth triggers are connected respectively to the first and second information ion inputs of the first mismatch comparator, the information output of which is connected to the first input of the seventh element And, and with the third inputs of the third and sixth elements And, the information outputs of the second and third mismatch comparators are connected to the second and third inputs of the seventh element And, the output of which is connected to the installation input second trigger, reset inputs of the first, third and fourth triggers and with the first input of the eighth element And, the first contact groups of the first, second and third groups of selector switches detectors and the first contact of the switch are connected to the zero potential bus of the device, the second group of contacts of the first, second and third groups of selector switches and the second contact of the switch are connected respectively to the second groups of inputs of the fourth, fifth and sixth comparators and to the second input of the eighth element And, the output of which is connected with reset inputs of the fifth and sixth counters, while the mismatch comparator contains two counters, the first trigger, seven AND elements, the first information input of the comparator coordination is connected to the reset input of the first counter, with the first inputs of the first and second elements And, the second information input of the mismatch comparator is connected to the reset input of the second counter, with the second input of the second element And and with the first input of the third element And, the output of the second element And is connected to the inverse the reset input of the first trigger, and with the first input of the fourth element And, the first synchronization input of the mismatch comparator is connected to the first input of the fifth element And, the output of which is connected to the counting input of the first of the counter, the output of the first counter is connected to the second inputs of the first and fifth elements And, the second synchronization input of the mismatch comparator is connected to the first input of the sixth element And, the output of which is connected to the counting input of the second counter, the output of which is connected to the second inputs of the third and sixth elements And, the outputs of the third and first elements AND are connected to the first and second inputs of the seventh element And, the output of which is connected to the installation input of the first trigger, the output of which is connected to the second input of the fourth element And, the output of which is the output of the mismatch comparator, characterized in that the second trigger, the eighth AND element and two OR elements are introduced into the comparator, the outputs of the first and second counters connected to the first and second inputs of the eighth AND element, the output of which is connected to the first input of the first OR element, the first and second inputs of the second OR element are connected respectively to the first and second information inputs of the mismatch comparator, the installation and reset inputs of the second trigger are connected respectively to the output to mismatch device and the output of the second OR element, the output of the second trigger is connected to the second input of the first OR element, the output of which is the error output of the mismatch comparator, and the device contains the ninth element And, the first, second and third inputs of which are connected respectively to the error inputs of the first, second and the third mismatch comparators, the output of the ninth element And is the output of the control device, the first, second and third inputs of the recording device are connected respectively to the recording inputs of the first, second and third registers.

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