RU204480U1 - Parallel bipolar to binary converter - Google Patents

Abstract

The utility model relates to computer technology and can be used in digital signal processing for converting a bipolar voltage into a digital binary code with an increased dynamic range of conversion. The technical result is the possibility of converting both positive and negative voltages into a binary code, increasing the dynamic range of conversion. The parallel converter includes a block of resistive voltage dividers, 2n-1 comparators, an encoder, a sign comparator, a reference voltage source, an analog inverter, a first analog switch, a second analog switch, an analog adder and a logic inverter. A sign comparator, an analog inverter and two analog switches make it possible to compare in the comparators a positive converted voltage with a positive voltage from the output of resistive dividers, and with a negative converted voltage, the inverted converted voltage is compared with a positive reference voltage. 1 ill.

Description

The utility model relates to computer technology and can be used in digital signal processing to convert a bipolar voltage into a digital binary code with an increased dynamic range of conversion.

Known serial analog-to-digital converter voltage-code, which implements the method of successive approximation (Ziatdinov S.I., Suetina T.A., Povarenkin N.V. Circuitry of telecommunication devices. Textbook. M: Academy, 2016. P.218, Fig. 8.3).

The device is designed to convert a unipolar voltage into a binary code. The converter contains n flip-flops, an n-bit shift register, an n-bit parallel digital-to-analog converter, a clock generator, and a comparator. The control inputs of the flip-flops are connected to the corresponding outputs of the shift register; the outputs of the flip-flops are connected to the corresponding inputs of a parallel digital-to-analog converter, the output of which is connected to one of the inputs of the comparator; the output of the comparator is connected to the control input of the shift register and the output of the clock pulse generator is connected to the input of the shift register shift pulses.

The disadvantages of this device are low speed, the impossibility of converting a multipolar voltage and a small dynamic range of conversion (a small ratio of the range of the converted voltage to the price of a unit of the least significant digit).

Known serial converter of unipolar voltage to binary code with a stepped sawtooth voltage (Gitis E.I., Piskunov E.A.Analog-digital converters. M .: Energoizdat, 1981. S. 218, Fig. 6.4)

The device consists of an n-bit binary summing counter, an n-bit parallel digital-to-analog converter; a comparator, a clock pulse generator, a count start trigger, a two-input conjunctor for supplying counting pulses, the outputs of a binary summing counter are connected to the same inputs of a parallel digital-to-analog converter, the output of which is connected to one of the comparator inputs, a converted voltage is supplied to the other comparator input, the comparator output is connected to the reset input of the count start trigger, the output of the count start trigger is connected to one of the inputs of the counting pulse feed conjunctor, the other input of the counting pulse feed conjunctor is connected to the output of the clock pulse generator, the output of the counting pulses feed is connected to the input of the clock pulses of the binary summing counter.

The disadvantages of this device are low speed, the impossibility of converting a bipolar voltage and a small dynamic range.

The closest in technical essence to the proposed utility model is a parallel converter of unipolar voltage into a binary code (Gitis EI, Piskunov EA Analog-to-digital converters. M .: Energoizdat, 1981. P.242, Fig. 6.10).

The n-bit converter includes a reference voltage source, a block of resistive voltage dividers, 2 ⁿ -1 comparators and an encoder. In the converter, the output of the reference voltage source is connected to the block of resistive voltage dividers, the inverting inputs of 2 ⁿ -1 comparators are connected to the corresponding resistive dividers of the block of resistive voltage dividers, the non-inverting inputs of the 2 ⁿ -1 comparators are the input of the converted voltage, the outputs of the encoder are the digital outputs of the converter.

The disadvantages of the device are the impossibility of converting a bipolar voltage and a small dynamic range of conversion.

The main task to be solved by the utility model is to develop a parallel voltage-to-code converter capable of converting a bipolar voltage and increasing the dynamic range of conversion.

The technical result achieved by the implementation of the claimed utility model is the ability to convert bipolar voltage and increase the dynamic range of conversion.

The specified technical result is achieved by the fact that a parallel converter of a bipolar voltage into a binary code, including a reference voltage source, a block of resistive voltage dividers, 2 ⁿ -1 comparators and an encoder, the output of the reference voltage source is connected to a block of resistive voltage dividers, inverting inputs 2 ⁿ -1 comparators are connected to the corresponding resistive voltage dividers of the block of resistive voltage dividers, the device additionally contains an analog inverter, a first analog switch, a second analog switch, an analog adder, a logical inverter and a sign comparator, the input of which is simultaneously connected to the input of the analog inverter and the signal input of the second analog switch, the output of which is connected to the first input of the analog adder, the output of the analog adder is connected to the non-inverting inputs of 2 ⁿ -1 comparators, the outputs of which are connected respectively to the inputs d ₁ , ..., d _{m of the} encoder, the output of the analog inverter connected to the signal input of the first analog switch, the output of which is connected to the second input of the analog adder, the output of the sign comparator is connected simultaneously to the control input of the first analog switch and the input of the logical inverter, the output of which is connected to the control input of the second analog switch, the input of the sign comparator is the input of the converted voltage , and its output is the sign output d _{zn of the} converter, the outputs Q ₀ , ..., Q _{n-1 of the} encoder are the outputs of the digital data of the converter.

The stated technical result is achieved by introducing additional blocks and connections between them, which allows parallel conversion of both positive and negative voltages into a binary code, and increases the dynamic range of conversion.

The analysis of the prior art carried out by the applicant has established that the analogs do not have a set of features identical to those of the claimed device "Parallel bipolar voltage to binary converter". Therefore, the claimed device meets the "novelty" condition.

The search results for known technical solutions in this and related fields of technology in order to identify features that coincide with the distinctive features of the prototype of the features of the claimed device, showed that they do not follow explicitly from the prior art.

The essence of the utility model is illustrated by the drawing shown in Fig. 1, where 1 is a reference voltage source, a resistive voltage divider unit, including 2m resistors 2.1, ..., 2m (m = 2 ⁿ -1, n is the number of bits of the converter), 2 ⁿ - 1 comparators 3.1,…, 3.m, 4 - encoder, 5 - analog inverter, 6 - first analog key, 7 - second analog key, 8 - analog adder, 9 - logic inverter, 10 - sign comparator.

A parallel converter of a bipolar voltage into a binary code includes a reference voltage source 1, a block of resistive voltage dividers 2, including 2m resistors 2.1, ..., 2m (m = 2 ⁿ -l, n is the number of converter bits), 2 ⁿ -1 comparators 3.1, ... , 3.m, encoder 4, analog inverter 5, first analog switch 6, second analog switch 7, analog adder 8, logic inverter 9, sign comparator 10, the output of the reference voltage source 1 is connected to the block of resistive voltage dividers 2, inverting inputs 2 ⁿ -1 comparators 3.1, ..., 3.m are connected to the corresponding resistive voltage dividers of the block of resistive voltage dividers 2, the output of the analog inverter 5 is connected to the signal input of the first analog switch 6, the output of which is connected to the second input of the analog adder 8, the output of which is connected to the non-inverting inputs 2 ⁿ -1 comparators 3.1, ..., 3.m, the outputs of which are connected respectively to the inputs d ₁ , ..., d _{m of} encoder 4 input zn This comparator 10 is simultaneously connected to the input of the analog inverter 5 and the signal input of the second analog switch 7, the output of which is connected to the first input of the analog adder 8, the output of the sign comparator 10 is simultaneously connected to the control input of the first analog switch 6 and the input of the logical inverter 9, the output of which is connected the control input of the second analog switch 7, entry of the sign comparator 10 is input to the converted voltage, and its output is significant yield d _receptacle converter, outputs Q _0, ..., Q _n-1 are the outputs of the encoder 4, the digital data transmitter.

The AD8564AD microcircuit is used as a comparator, the AD8564AD microcircuit is used as a sign comparator, the K140UD7 microcircuit is used as an analog inverter, the K176KT1 microcircuit is used as logical keys, the K140UD7 microcircuit is used as an analog adder, the K140UD7 microcircuit is used as a logical inverter, and the K155LN is used as a logical inverter. - microcircuit 1K55IV1 [1], [2].

Parallel converter of bipolar voltage to binary code works as follows.

The positive voltage of the reference voltage source 1 enters the block of resistive voltage dividers 2, in which the resistive voltage dividers generate positive reference voltages, which are fed to the corresponding inverting inputs 2 ⁿ -1 of comparators 3.1, ..., 3.m, namely: to the inverting input 2 ⁿ -1 comparator 3.1, the reference voltage comes from the resistive voltage divider 2.1-2.m + 1, the reference voltage from the resistive voltage divider 2.2-2.m + 2 is fed ^{to the inverting input 2 n -1 of the comparator 3.2, and so on.}

With a positive input voltage U _Rin sign comparator 10 is triggered and its output is set low voltage logic-zero level, which is supplied simultaneously to a control input of the first analog switch 6, to a logic input of the inverter 9 and the output transducer d = 0 _receptacle. At the output of the logical inverter 9 is set high voltage level logic units, under the action of which the second analog switch 7 opens and the positive input voltage U _Rin from the output of the second analog switch 7 to a first input of analog adder 8 and further from its output to the noninverting inputs 2 ⁿ -1 comparators 3.1, ..., 3.m. At this time, the first analog switch 6 is closed, since a low voltage acts on its control input. If the reference voltages at the inverting inputs of 2 ⁿ -1 comparators, for example, 3.1, 3.2, 3.2, 3.3, are less than the input voltage U _in , then these comparators will work and high voltages of the logical unit level will be established at their outputs. The rest of the comparators will not work and their outputs will have low voltages at the logic zero level.

As a result, high voltages will be present at the inputs d ₀ , d ₁ , d ₂ , d _{3 of the} encoder 4, and low voltages will be present at the inputs d ₄ - d _m. If the voltages are represented in the form of ones and zeros, then a normal unit code 000 ... 001111 will be formed at the encoder inputs, in which the number of ones indicates the number of triggered comparators. This code is converted by the encoder 4 into a binary code 000 ... 00100 ₂ . The sign bit of the converter with a positive input voltage has the value d _zn = 0.

With a negative input voltage U _in at the output of the sign comparator 10, a high voltage of the logical unit level is set, which is fed to the control input of the first analog switch 6, to the input of the logical inverter 9 and to the output of the converter d _zn = 1. At the same time, a low voltage of the logic zero level is set at the output of the logic inverter 9, under the action of which the second analog switch 7 is closed, the first analog switch 6, under the action of the high voltage at the control input, opens and the inverted input voltage from the output of the analog inverter 5 through the open first analog switch 6 goes to the second input of the logical adder 8 and then from its output to the non-inverting inputs 2 ⁿ -1 of the comparators 3.1, ..., 3.m. If the reference voltages at the inverting inputs of 2 ⁿ -1 comparators, for example, 3.1, 3.2, 3.3, 3.4, are greater than the voltage at the non-inverting inputs, then these comparators will work and high voltages of the logical unit level will be established at their outputs. The rest of the comparators will not work and their outputs will have low voltages at the logic zero level. As a result, high voltages will be present at the inputs d ₀ , d ₁ , d ₂ , d _{3 of the} encoder 4, and low voltages will be present at the inputs d ₄ - d _m. If the voltages are represented in the form of ones and zeros, then a normal unit code 000 ... 001111 will be formed at the encoder inputs, in which the number of ones indicates the number of triggered comparators. This code is converted by the encoder 4 into a binary code 000 ... 00100 ₂ . The sign bit of the converter with a negative input voltage has the value d _zn = 1.

As a result, the proposed converter makes it possible to convert both positive and negative voltages into a binary code and thereby double the dynamic range of conversion compared to the prototype.

The conversion of the bipolar voltage into a binary code is achieved due to the fact that the converter contains an analog inverter, which makes it possible to compare the positive converted voltage in the comparators with positive reference voltages and with a negative converted voltage after its inversion in the analog inverter - also with positive reference voltages. Converting both positive and negative voltages to binary doubles the dynamic range of the conversion.

Comparison of the parameters characterizing the inventive device and the prototype allows us to conclude that the inventive device provides the ability to convert a bipolar voltage into a binary code and double the dynamic range of conversion.

The given information proves that the following conditions are fulfilled in the implementation of the declared model:

- the means embodying the proposed device in its implementation is intended for use in computing, namely in digital signal processing devices;

- for the claimed device in the form as it is described in the independent claim of the utility model, the possibility of its implementation has been confirmed with the help of the means described before the filing date of the application;

- means embodying the claimed device in its implementation, is able to provide the specified technical result.

Therefore, the claimed device meets the condition of "industrial applicability".

Sourse of information:

1. Ziatdinov S.I., Suetina T.A., Povarenkin N.V. Circuitry of telecommunication devices. Textbook. M: Academy, 2016.

2. Shilo V.L. Popular digital microcircuits. M .: Radio and communication, 1988.

Claims (1)

Parallel converter of bipolar voltage into binary code, including a reference voltage source, a block of resistive voltage dividers, 2 ⁿ -1 comparators and an encoder, the output of the reference voltage source is connected to a block of resistive voltage dividers, the inverting inputs of 2 ⁿ -1 comparators are connected to the corresponding resistive voltage dividers block of resistive voltage dividers, characterized in that the device additionally contains an analog inverter, a first analog switch, a second analog switch, an analog adder, a logical inverter and a sign comparator, the input of which is connected simultaneously with the input of the analog inverter and the signal input of the second analog switch, the output of which is connected with the first input of the analog adder, the output of the analog adder is connected to the non-inverting inputs of 2 ⁿ -1 comparators, the outputs of which are connected respectively to the inputs d ₁ , ..., d _{m of the} encoder, the output of the analog inverter is connected to the signal input ne the first analog switch, the output of which is connected to the second input of the analog adder, the output of the sign comparator is connected simultaneously to the control input of the first analog switch and the input of the logical inverter, the output of which is connected to the control input of the second analog switch, the input of the sign comparator is the input of the converted voltage, and its output is the sign output d _{zn of the} converter, the outputs Q ₀ , ..., Q _{n-1 of the} encoder are the outputs of the digital data of the converter.

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