RU2042978C1 - Multichannel device for processing requests - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has decoder 1, flip-flop group 2 having n flip-flops, XOR gate 3, two NOR gates 4, 6, AND gate group 5 having n AND gates. EFFECT: increased speed, simplified design. 2 cl, 3 dwg

Description

 The invention relates to computer technology, in particular to devices for controlling the sequence of services in the face of a multitude of service requests, and can be used in the construction of various automation devices and information-measuring equipment.

A device for processing interrupts is known that contains two triggers, an AND element, as well as a group interrupt register, a mask register, an interrupt vector register, a group of AND elements, an AND element, and a delay element with conditioned connections between circuit elements [1]
The disadvantages of the known device are the complexity and low speed due to the use of delay elements.

It is also known a priority device containing an AND element, a group of OR elements, two registers, a group of OR elements and a delay element with conditional relationships between circuit elements [2]
The disadvantages of this device are the complexity and low speed.

Closest to the technical nature of the present invention is a multi-channel device for processing requests, comprising a decoder, a group of AND elements, a group of triggers and an EXCLUSIVE OR element, as well as a delay element, two AND elements, a group of NOT elements, a second group of AND elements, an OR element, and trigger with conditional relationships between circuit elements [3]
The disadvantages of the prototype include its complexity and low speed due to the use of a delay element and a counter.

 The purpose of the invention is the increase in speed and simplification of the device.

 This goal is achieved by the fact that in the well-known multichannel device for processing requests containing a decoder, a group of AND elements, a group of triggers and an EXCLUSIVE OR element, two OR-NOT elements are introduced, i.e. (i 1, n, where n is the number of channels) element inputs EXCLUSIVE OR, the first OR-NOT element, the decoder and the first input of the i-th element AND groups are connected to the direct output of the i-th trigger, the clock input of which is connected to the i-th input of the device request, the reset input of which is connected to (n + 1) -th input of the decoder, (n + 2) -th input of which connected to the output of the second OR-NOT element, the first input of which is connected to the output of the EXCLUSIVE OR element and the second inputs of the AND elements of the group, the outputs of which are device permission outputs, the information inputs of the trigger group are connected to the output of the first OR-NOT element and the second input of the second OR element -NOT, the reset input of the i-th trigger is connected to the i-th output of the decoder, as well as the fact that the decoder contains the first disjunctive, conjunctive and second disjunctive programmable logic m matrices, the first n inputs of the decoder are inputs of the first disjunctive programmable logic matrix, the (n + 1) -th input is the first input of the second disjunctive programmable logic matrix, the (n + 2) -th input is the first input of the conjunctive programmable logic matrix, and the outputs of the decoder are outputs of the second disjunctive programmable matrix.

 The presence of the above distinguishing features indicates that the invention meets the criterion of "novelty."

 The applicant did not find in the studied patent and scientific literature a multichannel device for processing requests with the indicated set of distinctive features that, when implementing the invention, provide a positive effect, i.e. the proposed technical solution meets the criterion of "significant differences".

 In FIG. 1 is a structural diagram of a multi-channel device for processing requests; in FIG. 2 schematic diagram of a decoder; in FIG. 3 timing diagram of the device.

 The multi-channel device for processing requests (Fig. 1) contains a decoder 1, a group of n triggers 2, an EXCLUSIVE OR 3 element, a first OR-NOT 4 element, a group of n AND 5 elements, a second OR-NOT 6 element, reset input 7, n inputs of request 8 and n outputs of permission 9.

 Decoder 1 (Fig. 1) contains the first 10 and second 11 disjunctive programmable logic arrays, conjunctive 12 programmable logic arrays, each of which contains a group of load resistors 13 and a group of diodes 14 conventionally shown as a dot). In the disjunctive programmable logic matrix, the anodes of the diodes 14 are connected to the inputs of the matrix, and the cathodes to the outputs of the matrix and to one of the terminals of the corresponding load resistor 13, the other terminal of which is connected to the device common bus. In a conjunctive programmable logic matrix, the cathodes of the diodes 14 are connected to the inputs of the matrix, and the anodes to the outputs of the matrix and to one of the terminals of the corresponding load resistor 13, the other terminal of which is connected to the terminal of the power source E of the device. In addition, the decoder contains a group of n inputs 15, (n + 1) -th input 7, (n + 2) -th input 16 and a group of n outputs 17. The matrices under consideration are typical logic elements and can be performed on K556PT1 microcircuits or K712RB1.

 The remaining elements of the device can be implemented on the microcircuits of wide application of the K155 series.

x_j-1, y₁=0 где Х_j сигнал на входе 15 дешифратора 1.The first 10 disjunctive logic matrix must be programmed so that a logical function is performed at its ith output:
y _i =

x _j-1 , y ₁ = 0 where X _{j is the} signal at input 15 of decoder 1.

y_i, v=1 где а сигнал на входе 16 дешифратора 1 (k 2,).The conjunctive 12 logical matrix must be programmed so that a logical function is performed at its Kth output:
V _k = a

y _i , v = 1 where a is the signal at input 16 of the decoder 1 (k 2,).

Z₁=b где b сигнал на входе 7 дешифратора 1.The second 11 disjunctive logic matrix must be programmed so that a logical function is performed at its Kth output:
Z _k = V

Z ₁ = b where b is the signal at input 7 of decoder 1.

 The device operates as follows.

 Channels have relative priority among themselves, corresponding to the channel number, i.e. The first channel has the highest priority for service with respect to the remaining channels.

In the initial state, in the absence of interrogation signals from subscribers for service, the interrogation inputs 8 of the device have logical zero signals (low voltage level). If all triggers 2 of the device are reset to zero, then the output of the first 4 elements OR NOT has a logic signal "1" (high voltage level), and the remaining outputs of the device elements have a logic signal "0". When applying, for example, only to the request input 8 _{n of the} n-th channel of a single pulse (request signal) at time t ₁ (see Fig. 3), the direct output of the trigger 2 _n is also set at the outputs of the EXCLUSIVE OR 3 element and output 9 _n element AND 5 _n , and at the output of the first 4 element OR NOT set a logic zero signal, which is fed to the information inputs of all triggers. Therefore, when, for example, the first channel of a single pulse arrives at the request input 8 ₁ at the time t ₂ (see Fig. 3), the state of the first 2 ₁ trigger does not change and the device only serves the request of the nth channel. At the end of the service, a single pulse is applied to the reset input 7 of the device at time t ₃ and single pulses are generated at all outputs 17 of the second disjunctive programmable logic matrix 11 of the decoder 1, which are fed to the reset inputs of all triggers 2, setting them to zero. In this case, the logic zero signals appear sequentially at the outputs of the trigger 2 _n , the element EXCLUSIVE OR 3 and the output 9 _{n of the} n-th element AND 5 _n , and at the output of the first element OR-NOT 4 the logical signal “1” is set. Further, if at time t ₄ (see Fig. 3) at the request inputs of the first 8 ₁ ; of the second 8 ₂ and n-th 8 _n channels, single pulses appear simultaneously, since triggers 2 are identical, then the first 2 ₁ , second 2 ₂ and n-th 2 _n triggers are simultaneously set to a single state, the signal is held at the output of the EXCLUSIVE OR 3 element logical "0", and at the outputs of the first 4 and second 6 elements OR NOT set respectively zero and unit logic signals.

Logical signal "1" from the output of the second 6 element OR NOT arrives at the (n + 2) -th input 16 of the decoder 1, namely: at the first input of the conjunctive logical matrix 12, therefore, at the outputs of the second 17 ₂ and n-m 17 _n the second 11 of the disjunctive logical matrix, logical 1 signals appear, according to which the triggers of the second 2 ₂ and the n-th 2 _{n are} reset to zero, the logical 1 signal is set at the output of the EXCLUSIVE OR 3 element, and the output of the second 6 element is OR NOT the logical signal “0” is set, which is also set at the outputs 17 of the decoder 1. Thus m, the device serves the request of the highest priority channel, i.e. first, and at its output 9 ₁ the logic signal “1” is held. To change the relative priority of the channels, it is necessary to reprogram the logical matrices 10-12 in accordance with the given priorities.

 Thus, the device serves the request that arrived first in time, and when several requests arrive, the request with the highest priority is simultaneously served.

 The advantages of the proposed device in comparison with the prototype are the simplification of the device, reducing the cost and increasing its speed, since 2 (n + 2) elements are used instead of 4 (n + 2) elements, i.e., the number of used elements is halved excludes the use of a counter and a delay element. In addition, the reliability of the device as a whole is increased, since the number of used elements and the connections between them is reduced without reducing the functionality of the device.

 The proposed device is implemented as a layout and passed the test. It is proposed to use it in the implementation of high-performance computing systems.

 The use of programmable logic matrices also provides the ability to programmatically change the relative priorities of the channels among themselves, without changing the relationships between the elements of the device circuit, by reprogramming the logical matrices, which also significantly expands the functionality of the device, compared to the prototype.

Claims (2)

 1. MULTI-CHANNEL DEVICE FOR PROCESSING REQUESTS, containing a decoder, a group of AND elements, a group of triggers and an EXCLUSIVE OR element, characterized in that, in order to improve performance and simplify the device, two OR OR NOT elements are introduced into it, and i-e (i 1 , n, where n is the number of channels) the inputs of the element EXCLUSIVE OR, the first element OR NOT, the decoder and the first input of the i-th element AND groups are connected to the direct output of the i-th trigger of the group, the clock input of which is connected to the i-th input of the device request, whose reset input is connected to (n + 1) -m input of the decoder, (n + 2) -th input of which is connected to the output of the second element OR - NOT, the first input of which is connected to the output of the element EXCLUSIVE OR and the second inputs of the elements AND groups, the outputs of which are the outputs of the device resolution, information the group trigger inputs are connected to the output of the first element OR NOT and the second input of the second element OR NOT, the reset input of the i-th group trigger is connected to the i-th output of the decoder.  2. The device according to claim 1, characterized in that the decoder contains the first disjunctive, conjunctive and second disjunctive programmable logic arrays connected in series, the first n inputs of the decoder are inputs of the first disjunctive programmable logic matrix, the (n + 1) -th input is the first input the second disjunctive programmable logic matrix, the (n + 2) th input is the first input of the conjunctive programmable logic matrix, and the outputs of the decoder are the outputs of the second disjunctive programmer the logical matrix, the second inputs of the first and second disjunctive matrices are connected to the logical bus "0" of the device, the second input of the conjunctive matrix is connected to the device potential bus.

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