RU2037270C1 - Universal signal-coding device - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has control signal shaper for generating signals affording control of exchange with digital computer, storage register unit for recording, storage, and output of 2^m codes of expected range of objects whose bearing is the same, selector for recording, storage, and output of strobe number and video-signal sampling frequency codes, and strobe shaper for storage addressing and control of recording of video signal codes into two-address main storage residing in address field of digital computer. EFFECT: increased number of sequential codes (signals) converted in fixed-frequency mathematical strobes into parallel codes within single time-base cycle, improved coding accuracy due to provision for signal conversion at minimum strobe-to-strobe space, conversion of high- length signals, arbitrary access to storage for signal code recording, multiple increase in number and maximum length of signals when device is extended, enlarged functional capabilities due to provision for selecting maximum sampling frequency, coding of great number of various-length signals with optimal sampling frequency, and reading of signal codes of preceding time-base during current one. 3 cl, 3 dwg

Description

 The invention relates to computer technology and can find application in radar stations (radar) of simultaneous tracking in range by mathematical gating of a large number of objects of different lengths and in other digital signal processing systems with different purposes.

 Any digital signal processing system comprises a digital computing device, a digital computer (digital computer), a microprocessor, or a specialized computing device. The signal supplied to the input of the computing device must be converted to a form suitable for input and processing of a digital computer.

A device for encoding video signals (AC), GKZ.052, 331.33 automatic radar plotting system (ARPA) [1]
The disadvantage of this device is the inability to convert sequentially incoming video signals reflected from several objects on one bearing. In the case of application through video surveillance processing, this device allows you to accompany five objects on one bearing without loss of accuracy in determining their parameters.

The technical solution closest to the invention and therefore adopted as a prototype is a device for converting a serial code into a parallel one, containing a block of receiving registers, a shift register, three pulse counters, a multiplexer, a decoder, four OR-NOT elements, a trigger and an inverter [2]
The disadvantages of this device are the limited duration of the converted codes and the lack of coding accuracy.

 The aim of the invention is to increase the number of gated serial codes (signals) of various durations, which can be converted with great accuracy into parallel codes for one cycle of time sweep, providing the possibility of conversion at a minimum interval between adjacent tracking gates and random access to memory for recording signal codes, expanding the scope devices due to the ability to select the maximum sampling frequency, signal coding, including long duration, optimum sampling frequency and reading the code signal in the previous time-base process current.

 In FIG. 1 shows a functional block diagram of the proposed device; in FIG. 2 functional block diagram of the gate generator; in FIG. 3 is a functional block diagram of a control signal generator.

 The device comprises a block of registers 1, a driver 2 of the control signals, register 3, a pulse counter 4, a driver 5 gates, a shift register 6, a frequency divider 7, a multiplexer 8, a shift register 9 and a register 10, address inputs 11, exchange inputs 12 and an information input 13 devices, the first 14 third 16 control inputs, clock input 17.

 The gate generator 5 comprises triggers 18-20, address counter 21, register 22, decoder 23, multiplexer 24, elements 2 OR 25-27, elements 2AND-NOT 28-30, n-input gate OR-NOT 31, n-input gate And 32, block of elements 2I 33.

 The driver 2 of the control signals contains a comparison unit 34, a decoder 35, an element 2 OR 36, an element 2 AND 37.

 The components of the block diagram of the proposed device can be implemented depending on the maximum sampling frequency of the signal on microcircuits 1801IR1 and microcircuits of the series 530, 533, 1533.

 The device operates under the control of a computer as follows.

 The exchange of information between the digital computer and the device is synchronized by a signal at input 14, the positive level of which corresponds to the forward course of the time sweep, and the positive difference coincides with its beginning.

 Before the next cycle of time sweep, the device is set to its initial state. The low level of the signal at input 14 and the negative signal at input 16, depending on the code on the address inputs 11 at the inputs of the exchange 12, record the initial information: in register 3 codes of the expected temporary position of information signals located on the same time base; in the register 6 codes of gate numbers and sampling frequencies of information signals; into the counter 4 pulses of the code of the expected temporary position of the closest information signal arriving from the register 3 cell on this scan.

 With the beginning of the time sweep, a positive signal level at the input 14 of the device allows the operation of the frequency divider 7. The counter 4 pulses, the capacity of which depends on the maximum duration of the temporary position of the gated information signal, starts the calculation of time intervals. The information signal received at the input of the installation in the "unit" of the least (senior) bit of the register 9, is sampled with the repetition rate of the pulses arriving at its clock input from the first output of the multiplexer 8, in accordance with the code on its address inputs.

 At the end of the calculation of time intervals, a start signal is received at the third input of the 5-strobe generator and at the moment coinciding with a positive difference in the count pulse, a strobe is installed at the first output of the 5-strobe generator, allowing pulses of the corresponding sampling frequency to pass from the second output of multiplexer 8 to the second input of the shaper 5.

 According to the positive pulse difference at the control input to the register 10 are recorded: the address code of the corresponding cell of register 1, consisting of the senior bits corresponding to the gate number code coming from the corresponding outputs of the register 6, and the lower n bits coming from the corresponding outputs of the generator 5 gates; K bit code of register information 9. After every K clocks of the sampling frequency, the cell address is increased by “one” and, according to the signal at the second output of the generator 5 gates from register 10 to the second port, register 1 at the address stored for the duration of the write cycle in register 10 is rewritten K-bit code of the information signal.

The recording cycle is repeated until K ˙ 2 ⁿ -digit code of the information signal is recorded in register 1.

 Before the end of the strobe, the pulse coming from the fourth output of the gate generator 5 through the driver 2 of the control signals to the second input of the pulse counter 4 carries out a parallel recording of the code for the expected temporary position of the next information signal.

 At the moment of termination of the strobe by the pulse from the third output of the gate generator 5 to the second input of the register 6, the gate number codes and the sampling frequency of the next information signal are selected.

 Upon receipt of the next trigger signal at the third input of the shaper 5 gates, the device operation cycle is repeated.

Thus, during a direct move, 2 ^m codes of information signals of the current time base are recorded in register 1.

· 2^n+q а длительность строба сопровождения информационного сигнала большой длительности
t_дл=

· 2^m+n+q где F тактовая частота;
2m количество стробов сопровождения на одной временной развертке, m 0, 1.Escape strobe duration
t

· 2 ^{n + q} and the duration of the strobe tracking information signal of long duration
t _dl =

· 2 ^{m + n + q} where F is the clock frequency;
2m the number of tracking gates at one time base, m 0, 1.

2 ^{n the} number of memory cells for recording the gated information signal, n 0, 1.

K the number of bits in the memory cell, K 1, 2,
2 ^q coefficient depending on sampling rate, q 0, 1
Reading from the first port of the register 1 codes of the information signal of the previous time scan is carried out by a negative signal at input 15 and the corresponding code at address inputs 11.

Claims (3)

 1. A UNIVERSAL SIGNAL CODING DEVICE, comprising a first block of registers, the first control input of which is the first control input of the device, the first shift register, counter and multiplexer, characterized in that a frequency divider, a second register block, a gate generator, a second shift register are inserted into it , a register and a driver of control signals, the information inputs of which are combined with the corresponding first address inputs of the first and second blocks of registers and are the address bus of the devices a, the second and third control inputs of which are the first and second control inputs of the driver of the control signals, the third control input of which is connected to the first output of the gate driver, and the first, second and third outputs are connected respectively to the input enable download counter, the second control input of the first block of registers and the control input of the second block of registers, the second address inputs of which are connected to the corresponding outputs of the first group of outputs of the gate generator, and information in The odes are combined with the corresponding information inputs of the first shift register and, together with the outputs of the first register block, are the device exchange bus whose clock bus is the clock input of the frequency divider, the preset enable input of which is combined with the first control input of the first register block and combined with the shift input of the first shift register the first control input of which is connected to the fourth output of the driver of the control signals, the second control input with the second output of the driver gates, the first group of outputs with the corresponding inputs of the first information inputs of the register, and the second group of outputs with the corresponding address inputs of the multiplexer and the corresponding inputs of the group of inputs of the gate generator, the first input of which is combined with the control input of the register, the counting input of the counter and connected to the first output of the frequency divider, the second to fifth outputs of which are connected to the corresponding information inputs of the multiplexer, the first output of which is connected to the clock input of the second reg shift, and the second output with the second input of the gate generator, the third input of which is connected to the output of the loan counter, the preset inputs of which are connected to the corresponding outputs of the second block of registers, while the fourth input of the gate generator is combined with the first control input of the first block of registers, the second address and the information inputs of which are connected to the corresponding outputs of the first and second groups of outputs of the register, respectively, the second and third information inputs of the register are connected to the corresponding the outputs of the second shift register and the second group of outputs of the gate generator, the third output of which is connected to the third control input of the first block of registers, and the fourth output with the first gate input of the multiplexer, the second gate input of which is a zero potential bus, the information input of the second shift register being information input device. 2. The device according to claim 1, characterized in that the gate driver is made on three triggers, (K 1) -bit shift register, decoder, multiplexer, three elements OR, three elements AND NOT, element OR NOT, element AND, block of elements And, the address counter, the first to nth outputs of which are the first group of outputs of the driver and connected to the corresponding inputs of the AND element, the output of which is connected to the first input of the first element AND NOT, the second input of which is combined with the D-inputs of the first and second triggers and connected to direct k-th in the output of the shift register, the inverse K-th output of which is connected to the resolution counter input of the address counter, the second control input of which is combined with the R-inputs of the second and third triggers, the R-input of the (K 1) -bit shift register, the S-input of the first trigger, the first inputs of the block of elements AND is the fourth input of the shaper, the first input of which is the C-inputs of the second and third triggers, the inverse output of the first of which is connected to the first input of the first element OR, the second input of which is combined with the first input of the second element nt AND is NOT the first input of the shaper, and the output is the third output of the shaper, the second output of which is the output of the second element AND NOT, the second input of which is connected to the output of the third element AND NOT, the first input of which is connected to the output of the second element AND NOT, and the second the input is combined with the first input of the second OR element and is connected to the output of the first AND element - NOT, while the second input of the second OR element is the third input of the driver and combined with the J-input of the third trigger, the K-input of which is connected to the output ohm of the second OR element, and the inverse output is the fourth output of the former, the first output of which is the output of the third OR element, the first input of which is connected to the output of the multiplexer, and the second input with the output of the OR element, NOT, the first through mth inputs of which are combined with the corresponding the second inputs of the block of elements And and are connected to the (n + 1) -th through the (n + m) -th outputs of the address counter, respectively, the preset inputs of the address counter, except for the (n + 1) -th, are a bus of zero potential, and (n + 1) -th input is a bus of a single potential iala, and the counting input of the address counter is combined with the C-inputs of the (K 1) -bit shift register and the first trigger and is the second input of the shaper, the group of inputs of which are the address inputs of the multiplexer, the information inputs of which are connected to the corresponding outputs of the decoder, address inputs from the first on the nth of which are connected to the corresponding outputs of the address counter, and the gate inputs are connected in series with K · 2 ⁿ 8 by K · 2 ⁿ 1 outputs of the (K 1) -bit shift register, while the direct output of the first trigger with It is connected to the information input of the (K - 1) -bit shift register, and the outputs of the block of AND elements are the second group of outputs of the shaper.  3. The device according to claim 1, characterized in that the driver of the control signals is made on a comparison unit, a decoder, an OR element, an AND element, the output of which is the first output of the driver, the first input is the third control input of the driver, and the second input is connected to the first output of the decoder , the second and third outputs of which are the fourth and third outputs of the shaper, the second output of which is the output of the OR element, the first input of which is the first control input of the shaper, and the second the stroke is combined with the first gate input of the decoder and connected to the output of the comparison unit, the first information inputs of which are combined with the corresponding information inputs of the decoder and are the information inputs of the driver, the second control input of which is the second gate input of the decoder, while the first and second control inputs of the comparison unit are combined with the least significant bits of the second information inputs of the comparison unit are the bus of zero potential, and the highest bits of the second information The input inputs of the comparison unit are combined with its third control input and are the bus of the corresponding potential.