RU2032935C1 - Signal arbitrator - Google Patents

Abstract

FIELD: automatics, computer engineering. SUBSTANCE: signal arbitrator includes logic AND gates 1-3, OR gate 4, univibrator 5, flip-flops 6 and 7, enquiry inputs 8 and 9 and outputs 10 and 11. EFFECT: enhanced operational reliability. 1 dwg

Description

 The invention relates to automation, computer technology and control systems and can be used in various control and computing systems and devices, including in flexible production systems based on micro-computers and microprocessors.

A two-input priority device is known that contains a trigger, a delay element, an AND element, and NOT elements, which allows switching input signals regardless of the time of their appearance [1]
However, in such a device, the removal of signals at one output and the appearance of the signal at the other occurs without taking into account the end time of transients in an external circuit connected to the device, as well as in the case when the request signal arrives at the first input of the device after the appearance of the request signal at the second input of the device with an interval equal to the delay time of the delay element, signals may appear at the device outputs, the duration of which is equal to the transient completion time in the device, which reduces the reliability his work.

A two-input priority device is also known that contains the elements OR-NOT, a delay element, an element NOT, a Schmidt trigger, controlled delay blocks [2]
However, such a device is complex and also does not take into account the end time of transients in an external circuit connected to the device.

 The closest in technical essence to the proposed signal arbiter is a two-input priority device containing the first and second input logic elements in the form of AND elements, an OR element, a one-shot, first and second triggers, in which the first inputs of the first and second input logic elements are connected to the first and the second request inputs of the device, respectively, the outputs of the first and second input logic elements are connected to the first and second inputs of the OR element, the output of the OR element is connected to the input of one a rotor whose direct and inverse outputs are connected to the synchronization inputs of the first and second triggers, respectively, the outputs of the first and second triggers are connected to the second inputs of the second and first input logic elements, respectively, and the direct output of the second trigger is the second output of the device (3).

 A disadvantage of the known device is its complexity, caused by a relatively large number of communication lines, as well as the possibility of unreliable operation with a certain sequence of occurrence of request signals at the inputs of the device.

 The purpose of the invention is the simplification of the signal arbiter by reducing the number of communication lines, increasing the reliability of its operation by blocking the signal at the first output of the arbiter while the first trigger is in a metastable state and expanding the scope by removing restrictions on the type of request signals and separating the moments of the signal end at one output the arbiter and the appearance of the signal at its other output for a time equal to the duration of the signal generated by the one-shot.

 This goal is achieved by the fact that in the signal arbiter containing the first and second elements AND, the OR element, one-shot, the first and second triggers, the first inputs of the first and second elements And are connected to the first and second request inputs of the signal arbiter, respectively, the outputs of the first and second AND elements are connected to the first and second inputs of the OR element, the output of the OR element is connected to the input of a one-shot, the direct and inverse outputs of which are connected to the synchronization inputs of the first and second triggers, respectively, inverse the outputs of the first and second triggers are connected to the second inputs of the second and first elements And, respectively, and the direct output of the second trigger is connected to the second output of the signal arbiter, the third element And, and the direct output of the first trigger is connected to the first input of the third element And, the inverse output of the one-shot with the second input of the third AND element, the output of which is connected to the first output of the signal arbiter, the outputs of the first and second elements AND are connected to the inverse reset inputs of the first and second triggers, respectively Indirectly, and the information inputs of the first and second triggers are connected to the voltage bus log. "1".

 The drawing shows an electrical diagram of the proposed signal arbiter.

 It contains logical elements AND 1-3, element OR 4, one-shot 5, triggers 6 and 7, request inputs 8 and 9 and outputs 10 and 11.

 Arbitrator signals works as follows.

 In the initial state, the outputs of the logs are set at the outputs of the elements And 1 and 2. "0" and triggers 6 and 7 are reset. Triggers 6 and 7 are triggered by a positive signal drop at their sync input. At the information inputs of triggers 6 and 7, a constant signal of log. "1" is set.

 Request signals arrive at random times at the request inputs of the arbiter 8 and 9 in the form of log signals. "1".

 Upon receipt of a request for input 8 at the output of the AND 1 element, a log signal “1” is generated, which is fed to the inverse reset input of the trigger 6 and through the OR 4 element to the start input of the one-shot 5.

 At the direct and inverse outputs of the one-shot 5, simultaneously the log signals “1” and log. “0” are simultaneously generated, the duration of which should exceed the longest time from the following list: total response time of trigger 6 and element “And” 2; the time spent by trigger 6 in a metastable state; the duration of transients in an external circuit connected to the outputs of the arbitrator, caused by the removal of the signal at the output 10 (11) of the arbitrator.

 A trigger 6 is triggered on the leading edge of the Log. "1" signal from the direct output of the one-shot 5, and the log. "0" signal from its inverse output prohibits a request from input 9 to trigger 7 until the first subscriber finishes servicing, withdraws the request from input 8 and return trigger 6 to its original state.

 The pulse signal log. "0" from the inverted output of the single-shot 5 is fed to the element And 3, blocking for a while the output of the signal log. "1" to the output 10 of the arbitrator.

 When a request is received for input 9, the arbiter works in the same way, while the trigger 7 is triggered by the trailing edge of the log signal. "0" at the inverse output of a single vibrator 5.

 With the simultaneous receipt of requests for inputs 8 and 9, the signal log. "1" is generated only at the output of the arbiter 10, since by the time a positive signal difference occurs at the trigger input 7 (corresponding to the trailing edge of the signal log. "0" at the inverted output of the one-shot 5) it is blocked by a log signal. "0" received by its inverse input reset from the inverse output of the trigger 6 through the element And 2.

 At the end of the service, request the first subscriber and remove the signal log. "1" from input 8, trigger 6 is set to zero, the signal is log. "1" from its inverse output allows the request to pass from input 9 to the output of AND element 2. Signal log. "1" from the output of the AND 2 element through the OR element 4 restarts the one-shot 5, on the trailing edge of the signal log. "0" from the inverse output of the one-shot 5 triggers 7. At the output 11, the signal log. "1" is generated.

 Upon receipt of requests for both inputs of the arbiter at time following each other, the moment the log signal ends. “1” at the output of the arbiter 10 (11) (termination of service of the first (second) subscriber) and the appearance of the log signal. "1" at the output 11 (10) of the arbiter (the beginning of the service of the second (first) subscriber) is divided into a time equal to the duration of the signal generated by the single-shot 5.

 In the case when the request signals are received at the inputs of the arbiter in the form of log signals. "0", instead of elements AND 1 and 2, elements are used OR NOT, and their second inputs are connected to the direct outputs of triggers 7 and 6, respectively. The sequence of functioning of the elements of the arbitrator scheme in this case coincides with that described.

Claims (1)

 SIGNAL ARBITRATOR containing the first and second elements AND, the OR element, one-shot, the first and second triggers, the first inputs of the first and second elements And connected to the first and second request inputs of the signal arbiter, respectively, the outputs of the first and second elements And connected to the first and second the inputs of the OR element, the output of the OR element is connected to the input of a single vibrator, the direct and inverse outputs of which are connected to the synchronization inputs of the first and second triggers, respectively, the inverse outputs of the first and second triggers are connected They are connected with the second inputs of the second and first elements And, respectively, and the direct output of the second trigger is connected to the second output of the signal arbiter, characterized in that a third element And is inserted into it, and the direct output of the first trigger is connected to the first input of the third element And, the inverse output is a one-shot connected to the second input of the third element And, the output of which is connected to the first output of the signal arbiter, the outputs of the first and second elements And are connected to the inverse reset inputs of the first and second triggers, respectively, and The input inputs of the first and second triggers are connected to the voltage bus of the logical unit.