RU2020765C1 - Device for search of pseudonoise signal according to delay - Google Patents

Abstract

FIELD: electric communication and radio engineering. SUBSTANCE: device uses multiplier 1, filter 2, detector 3, low-pass filter 4, threshold element 5, delay line 6, control unit 7, maximum selection unit 8, threshold element 9, clock-pulse generator 10, rejection unit 11, switching unit 12, clock-pulse counter 13, pseudonoise signal generator 14. EFFECT: decreased average time of search of pseudonoise signal according to delay. 2 dwg

Description

 The invention relates to telecommunications and radio engineering and can be used in information transmission and ranging systems.

 The purpose of the invention is to reduce the average delay time of the search for a pseudo-noise signal.

 In FIG. 1 is a structural electrical diagram of a delay pseudo noise signal search device; in FIG. Figure 2 shows examples of modules of periodic autocorrelation functions of composite nonlinear sequences (SNP) for a length N = 255.

 The delay pseudo noise signal search device comprises a multiplier 1, a filter 2, a detector 3, a low-pass filter (LPF) 4, a first threshold element 5, a delay line 6, a control circuit 7, a maximum selection unit (BVM) 8, a second threshold element 9, a clock generator 10, a notch circuit 11, a switching unit 12, a clock counter 13, a pseudo noise signal generator (PSH) 14.

 The search device pseudo-noise signal delay works as follows.

The input PShS, which is used as the SPS (see Fig. 2), is fed to the input of the multiplier 1, the second input of which is fed to the reference PShS from the output of the generator 14 PShS. From the output of multiplier 1, the resulting mixture is fed to the input of filter 2, which plays the role of an integrator. Integration is performed over a time of 0 ÷ T _s , where T _s = Nτ _and is the duration of the analysis cycle, and τ _and is the duration of one cycle. Zeroing (resetting) of filter 2 is carried out by a pulse from the counter 13 clock pulses to the second input of filter 2. The voltage from the output of filter 2 is supplied to the detector 3, the output of which is set to a voltage proportional to the modulus of the periodic ACC correlation function (for example, see Fig. 2). This voltage through the low-pass filter 4 is fed to the input of the first threshold element 5 and the first input of the BVM 8. In the case when the voltage from the output of the detector 3 does not exceed the threshold of the first threshold element 5, the switching unit 12 remains in its original position. At the same time, from the third output of the control circuit 7 through the delay line 6, a signal of level "0" is supplied to the second input of the circuit 11 for rejecting one clock pulse in a pulse sequence, not the first input of the rejection circuit 11 from the output of the clock generator 10. The sequence of clock pulses without a single rejected pulse from the first output of the rejection circuit 11 is fed to the first input of the switching unit 12, the output of which goes to the input of the PShS generator 14 and the input of the counter 13 clock pulses. Thus, a shift is made in the delay of the reference PSH relative to the input for a time τ _and .

The counter 13 clock pulses counts the clock pulses received at the input of the PShS generator 14. When the input of the counter 13 clock pulses of the N-th clock pulse appears at its output, the pulse arrives at the fifth input of the control circuit 7 and allows the voltage level to pass from the first threshold element 5 to the control circuit 7, as well as arriving at the second input of the filter 2 and zeroing (dumping) it. Shifts in the delay of the reference PNA relative to the input by one clock pulse continue until the voltage at the input of the first threshold element 5 exceeds its threshold level, which corresponds to the presence of a narrow side peak of the module of the periodic autocorrelation function of the SPS. From this moment on, the delayed PNS search device begins to shift the reference PNS relative to the input at a time Sτ _and . This is done as follows.

The first threshold element 5 provides a signal of level "1", which is fed to the first input of the control circuit 7, as a result of which the pulse of switching the level "1" is received from the fourth output of the control circuit 7 to the third input of the switching unit 12. As a result, the output of the switching unit 12 receives clock pulses from the second input of the switching unit 12. At the same time, a pulse from the first output of the control circuit 7 is received at the second input of the BVM 8, allowing voltage to pass from the output of the low-pass filter 4 to the first input of the BVM 8. At the same time, a level pulse is received from the second output of the control circuit 7 to the third input of the rejection circuit 11 " 0 "for notching S clock pulses. Then the sequence of clock pulses through the switching unit 12 is fed to the input of the generator PShS 14 and the input of the counter 13 clock pulses. The counter 13 clock pulses performs the same role as in the above case. Thus, there is a shift in the delay of the reference PSH relative to the time Sτ _and . Shift delay reference ECP on time Sτ _and continues as long as the counter part of the BVM 8 not count l pulses coming from the first output control circuit 7 (in this case happens to view all points of possible location of the narrow side of the peaks and base the peak of the autocorrelation function of the SNP (see Fig. 2) .After that, from the second output of the BVM 8 the input of the second threshold element 9 receives the stored maximum voltage value from the output of the low-pass filter 4 (the result of the analysis of l points of the possible finding of narrow side peaks and bases peak) .When the threshold level of the second threshold element is exceeded, a decision is made on finding (detecting) the main peak of the periodic autocorrelation function of the SPS. Simultaneously, from the first output of the BVM 8, the number of the point at which the maximum value is detected, for example, n According to the threshold exceeding signal coming from the second threshold element 9 to the third input of the control circuit 7, a level “0” pulse is generated in it to reject n˙S clock pulses from the 10 clock pulse generator . This pulse comes from the second output of the control circuit 7 to the third input of the rejection circuit 11. There is a shift in the reference PSH relative to the time taken n˙S˙τ _and . After that, the search ends.

 If the threshold level of the second threshold element 9 does not exceed, the level “0” appears at its output, which is supplied to the third input of the control circuit 7, and the PNS search device for the delay returns to its original state, i.e. again begins a shift in the delay of the reference PSH by one clock pulse.

Claims (1)

 DEVICE FOR SEARCHING AN ALARM DELAY SIGNAL containing a multiplier, a filter, a detector, a low-pass filter (LPF) and a first threshold block, as well as a clock generator, the output of which is connected to the clock inputs of the control unit and the cutting unit, a clock counter and a generator a pseudo-noise signal (PSH), the output of which is connected to one of the inputs of the multiplier, characterized in that, in order to reduce the average search time by delay, a series-connected block is introduced selecting a maximum and a second threshold block, as well as a switching block and a delay line, wherein the LPF output is connected to the first input of the maximum selection block, the second output of which and the outputs of the first and second threshold blocks are connected to the corresponding inputs of the control unit, the first output of which is connected to the second the input of the maximum selection unit, the second output of the control unit is connected to the first input of the notch unit, the second input of which is connected to the third output of the control unit through the delay line, and the outputs of the notch unit through the commutator The stations are connected to the inputs of the PShS generator and the clock pulse counter, the output of which is connected to another input of the filter and the corresponding input of the control unit, the fourth output of which is connected to the control input of the switching unit.

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