RU2018923C1 - Modulo 2 subtraction and addition device - Google Patents

Abstract

FIELD: computer technology; microelectronics. SUBSTANCE: device has two single-digit binary adders, two half adders, modulo 3 adder, six inputs, outputs of senior and junior digits of the result. Two-digit complete operands X, Y and Z are applied to inputs of the device. Two-digit binary code of the result is formed at outputs of the device of modulo 3 addition and subtraction operations for three numbers X, Y and Z in form of R = (± X ± Y ± Z) mod3. The operation is performed by corresponding commutation of senior and junior digits of operands at outputs of the device. EFFECT: improved reliability. 10 tbl, 1 dwg

Description

 The invention relates to computer technology and microelectronics and can be used to build hardware control equipment and digital devices operating in a system of residual classes.

 Known adder modulo three two full two-bit operands, which contains eight AND elements, two OR elements, two OR-NOT elements and two addition elements modulo two [1].

 The disadvantage of the adder is limited functionality, since it does not implement the addition and subtraction modulo three over three operands.

 The closest technical solution to the proposed one is a device for modulo addition of three two reduced operands, containing six AND elements, two OR elements, two OR-NOT elements and two addition elements modulo two [2].

 A disadvantage of the device is also limited functionality, since it does not perform addition and subtraction operations modulo three over three operands.

 The drawing shows a diagram of a device for adding and subtracting three numbers modulo three.

 The device contains two single-digit binary adders 1 and 2, two half-adders 3 and 4, an adder 5 modulo three, six inputs 6 ... 11, outputs senior 12 and junior 13 bits of the result.

 The inputs of the first one-bit binary adder 1 are connected respectively to the inputs 6, 7 and 8 of the device, the inputs of the second one-bit binary adder 2 are connected respectively to the inputs 9, 10 and 11 of the device. The transfer output of the first one-bit binary adder 1 is connected to the first input of the first half-adder 3, the second input of which is connected to the output of the sum of the second one-bit binary adder 2. The transfer output of the last is connected to the first input of the second half-adder 4, the second input of which is connected to the output of the sum of the first one-bit binary adder 1. The transfer output of the first half-adder 3 is connected to the first input 14 of the senior discharge of the adder 5 modulo three. The transfer output of the second half-adder 4 is connected to the first input 15 of the lower order of the adder 5 modulo three, and the output of the sum is connected to the second input 16 of the highest order of the adder 5 modulo three, the second input 17 of the lower order, which is connected to the output of the sum of the first half-adder 3. Output the highest digit of the adder 5 modulo three is connected to the output 12 of the highest digit of the result of the device, the output 13 of the lowest digit of the result is connected to the output of the least significant digit of the adder modulo three.

 A device for adding and subtracting three numbers modulo three works as follows.

_Two -bit full operands X = 2x ₁ + x ₂ , Y = 2y ₁ + y ₂ and Z = 2z ₁ + z ₂ , where x _i ∈ {0,1}, y _i ∈ { 0,1}, z _i ∈ {0,1}, i = 1,2 and X ∈ {0, 1, 2, 3}, Y ∈ {0, 1, 2, 3}, Z ∈ {0, 1 , 2, 3}. At the outputs 12 and 13, a two-bit binary result code R ₁ = 2r ₁ + r _{2 is formed} for the addition and subtraction of three numbers Z, Y and Z modulo three, r _i ∈ {0,1}, i = 1, 2 and R ∈ {0, 1, 2}. Moreover, at the output 12, the leading bit r ₁ is realized, and at the output 13, the least significant bit r _{2 of the} result R.

The proposed device implements eight operations of addition and subtraction of the form
R = (± X ± Y ± Z) mod 3.

 The operation to be performed is determined by appropriate switching of the high and low bits of the operands at the device inputs, as indicated in Table 1.

In the table. 2-9 show the values of the functions implemented by the device r _i = r _i (x ₁ , x ₂ , y ₁ , y ₂ , z ₁ , z ₂ ), i = 1, 2 for eight types of operations performed.

A device for adding and subtracting three numbers modulo three is constructed using the following relationships:
(2x ₁ + x ₂ ) mod3 = - (2x ₂ + x ₁ ) mod3 =
= (3 - 2x2 - x ₁ ) mod3;
(2y ₁ + y ₂ ) mod3 = - (2y ₂ + y1) mod3 =
= (3 - 2y ₂ - y ₁ ) mod3;
(2z ₁ + z ₂ ) mod3 = - (2z ₂ + z ₁ ) mod3 =
= (3 - 2z ₂ - z ₁ ) mod3.

 As an adder 5, which is part of the device, an adder can be used that performs modulo addition of the three two given operands, for example, the adder from [2]. The operation of such an adder is described in Table 10.

 The advantage of the claimed device is its wide functionality. So, the proposed device performs eight addition-subtraction operations modulo three over three two-bit operands. The known device performs only the addition operation modulo three two numbers.

Claims (1)

 DEVICE FOR ADDING AND SUBTRACTING THREE NUMBERS THROUGH MODULE THREE, containing an adder modulo three, the i-th (i = 1,2) output of which is connected to the output of the device, characterized in that it contains two half-adders and two one-bit binary adders, j-th (j = 1, 2, 3) the input of the i-th of which is connected to the (2i + j - 2) -th input of the device, and the transfer output is connected to the first input of the i-th half-adder, the second input of which is connected to the output of the sum (3 -i) -th single-bit binary adder, the transfer output of the first half-adder is connected to the first input of the senior bit of the adder module three, the second input of the senior bit of which is connected to the sum output of the second half-adder, the transfer output of which is connected to the first input of the least significant bit of the adder modulo three, the second input of the least significant bit of which is connected to the output of the sum of the first half-adder.

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