RU2012110699A - TACT SYNCHRONIZATION DEVICE FOR TRANSFORMING INTERRUPTED INFORMATION INTO CONTINUOUS - Google Patents
TACT SYNCHRONIZATION DEVICE FOR TRANSFORMING INTERRUPTED INFORMATION INTO CONTINUOUS Download PDFInfo
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- RU2012110699A RU2012110699A RU2012110699/08A RU2012110699A RU2012110699A RU 2012110699 A RU2012110699 A RU 2012110699A RU 2012110699/08 A RU2012110699/08 A RU 2012110699/08A RU 2012110699 A RU2012110699 A RU 2012110699A RU 2012110699 A RU2012110699 A RU 2012110699A
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- input
- output
- information
- subtractor
- counter
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Abstract
Устройство тактовой синхронизации для преобразования прерывистой информации в непрерывную, состоящее из последовательно соединенных фильтра нижних частот и генератора, управляемого кодом, отличающееся тем, что в него дополнительно введены счетчик записи, счетчик чтения, два вычитателя, формирователь импульса начальной установки и запоминающее устройство; при этом первый вход счетчика записи является входом тактовых импульсов устройства, а второй вход соединен с выходом формирователя импульса начальной установки и вторым входом счетчика чтения, первый вход которого соединен с выходом генератора, являющимся выходом тактовых импульсов устройства, выходы счетчиков записи и чтения соединены со вторым и третьим входами запоминающего устройства и первым и вторым (инверсным) входами первого вычитателя, при этом выход первого вычитателя соединен с первым входом второго вычитателя, на второй (инверсный) вход которого подана константа 2(n - разрядность счетчиков), а выход соединен с входом фильтра нижних частот; первый вход запоминающего устройства является информационным входом устройства, а выход - информационным выходом устройства.A clock synchronization device for converting discontinuous information into continuous information, consisting of a series-connected low-pass filter and a code controlled oscillator, characterized in that it additionally includes a write counter, a read counter, two subtractors, an initial pulse generator and a memory device; wherein the first input of the recording counter is the input of the device’s clock pulses, and the second input is connected to the output of the initial setting pulse shaper and the second input of the read counter, the first input of which is connected to the generator output, which is the output of the device’s clock pulses, the outputs of the write and read counters are connected to the second and the third inputs of the storage device and the first and second (inverse) inputs of the first subtractor, while the output of the first subtractor is connected to the first input of the second subtractor, to the second (and population-inverted) input of which is fed a constant 2 (n - bit counters), and an output coupled to an input of a lowpass filter; the first input of the storage device is the information input of the device, and the output is the information output of the device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| RU2012110699/08A RU2517269C2 (en) | 2012-03-20 | 2012-03-20 | Clocking device for converting discrete information to analogue information |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| RU2012110699/08A RU2517269C2 (en) | 2012-03-20 | 2012-03-20 | Clocking device for converting discrete information to analogue information |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| RU2012110699A true RU2012110699A (en) | 2013-09-27 |
| RU2517269C2 RU2517269C2 (en) | 2014-05-27 |
Family
ID=49253644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| RU2012110699/08A RU2517269C2 (en) | 2012-03-20 | 2012-03-20 | Clocking device for converting discrete information to analogue information |
Country Status (1)
| Country | Link |
|---|---|
| RU (1) | RU2517269C2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970009688B1 (en) * | 1994-10-19 | 1997-06-17 | 엘지정보통신 주식회사 | Circuit for depreesing jitter |
| JP3555372B2 (en) * | 1997-02-17 | 2004-08-18 | 松下電器産業株式会社 | Synchronous processing circuit |
| US7868949B2 (en) * | 2003-12-15 | 2011-01-11 | Trident Microsystems (Far East) Ltd. | Circuit arrangement and method for locking onto and/or processing data, in particular audio, T[ele]v[ision] and/or video data |
| RU2261528C1 (en) * | 2004-06-07 | 2005-09-27 | Московский государственный университет путей сообщения (МИИТ) | Network-synchronization pulse phase jitter compensator |
| JP5397025B2 (en) * | 2009-06-02 | 2014-01-22 | ソニー株式会社 | Clock reproduction device and electronic device |
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2012
- 2012-03-20 RU RU2012110699/08A patent/RU2517269C2/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| RU2517269C2 (en) | 2014-05-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | The patent is invalid due to non-payment of fees |
Effective date: 20150321 |