RU2001494C1 - Device for control over valve converter - Google Patents

Description

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The invention relates to electrical engineering, in particular to devices for pulse-phase control of valve converters (VP) using digital information processing methods, and can be applied in a controlled DC electric drive.

A device for controlling a valve converter is known, comprising a calculation unit with two interrupt inputs, a synchronization unit with an isolation transformer, clock counters and a block for distributing and amplifying unlocking pulses, the outputs of which are connected to the control electrodes of the converter valves.

The disadvantages of this device are the complexity of the hardware, due to the use of a large number of electronic components - and the limitation of the scope - to control non-reversible (single-bridge) VPs.

The closest in technical essence to the proposed device is a device for controlling a valve converter, comprising a computing unit with two interrupt inputs and a clock output, a synchronization unit with an isolation transformer, the primary winding of which is connected to the mains, clock counters with clock and start inputs , a unit for distributing and amplifying unlocking pulses, the outputs of which are connected to the control electrodes of the converter valves, and a sensor unit s state of the valves converter whose inputs are connected to the supply-controlled converter.

The disadvantages of this device are:

- the complexity of the design of six-channel circuits of the synchronization block and the block of sensors for the state of the valves of the VP;

- insufficient reliability of switching the VP bridges when reversing for a minimum time, due to the lack of accurate fixation of the moment of reliable shutdown of the valves of the working bridge before turning on the valves of the bridge that comes into operation;

-lack of information about the value of the dead time interval (or the angle of conduction of the valves), which impedes the implementation of the adaptation of the current regulator to the intermittent current mode (for example, when using the device in an electric drive) and limits the scope of the device.

- the need for phasing the voltage of the supply network supplied to the inputs of the synchronization unit with the power voltage supplied to the VP, when the device is put into operation.

The aim of the invention is to simplify the design of the device, increase reliability and expand its functionality.

This goal is achieved in that a device for controlling a valve converter comprising a computing unit (WB) with a common bus, two interrupt inputs, an I / O port

5 and the clock output, a synchronization unit with an isolation transformer, the primary winding of which is connected to the mains, connected to a common WB bus. clock counter with inputs

0 timing and start-up and a block of distribution and amplification of unlocking pulses, the outputs of which are connected to the control electrodes of the converter valves, and a block of valve status sensors, inputs

5 of which are connected to the supplying VP network, it is equipped with a programmable timer, a clock divider and two 2I-NOT elements, with a programmable timer and a clock divider connected to a common WB bus, the start input of the clock counter is connected to the output of the I / O port WB, the output of the clock counter is connected to the input of the start of the programmable timer and to the first

5 to the interrupt input V B, the clock inputs of the programmable timer and the clock divider are connected to the output of the clock frequency B. The programmable timer output is connected to the first input of the first element 2I-NOT, the output of the clock divider is connected to the second input of the first 2I element -NOT and with the first input of the second element 2I-NOT, the second input of which is connected to the output of the block of state sensors

5 valves VP. The output of the first 2I-NOT element is connected to the start input of the block of distribution and amplification of the unlocking pulses, and the output of the second 2I-NOT element is connected to the second interrupt input of the WB. At

0 this synchronization unit is single-channel. and the isolation transformer is single-phase, and the secondary winding of the latter through a diode and a resistor connected in series is connected to the inputs of the 5 comparator, the output of which is connected to the second input of the input-output port of the WB. In addition, the device is equipped with a phase rotation sensor, made in the form of three resistors connected to a star, connected respectively to three

phases of the network supplying the VI. and an optome, whose input circuit is connected between the common point of the resistors and one of the output terminals of the VP. moreover, the output of the optocoupler is connected to the first input of the input-output port of the WB.

In FIG. 1 is a functional diagram of a device for controlling a three-phase VI: in FIG. 2 is a circuit diagram of a synchronization block; FIG. 3 is a schematic diagram of a distribution and amplification unit of unlocking pulses; in FIG. 4 is a schematic diagram of a trigger pulse power amplifier; in FIG. 5 is a schematic diagram of a valve condition sensor unit; in FIG. 6 is a circuit diagram of a phase rotation sensor; in FIG. 7 is a flowchart of an airspace control algorithm.

The device (see Fig. 1) contains WB 1, synchronization unit 2, counter 3 clock pulses, block 4 distribution and amplification of optic pulses, block 5 sensors status valves, programmable timer 6, divider 7 clock frequency, two elements 2I-NOT 8, 9 and phase rotation sensor 10. WB 1 has two interrupt inputs - 11 and 12, a common bus 13 (address, data, and control bus), clock output 14, output 15, and I / O ports 16, 17. Programmable timer 6, divider 7 and counter 3 are connected to a common bus 13 of WB1. Clock inputs 18. 19, 20, respectively, of programmable timer 6. Clock divider 7 and counter 3 are connected to output 14 of clock frequency WB 1. Input 21 of counter start 3 is connected to output 15 of input-output port B 1, and output 22 counter 3 by the input 23 of the start of the programmable timer 6 and the first input 11 of the interruption of the power supply 1. Output 24 of the programmable timer 6 is connected to the first input of the first element 8 2I-NOT, output 25 of the divider 7 is connected to the second input of the first element B 2I-NOT and with the first input of the second element 9 2I-NOT. the second input of which is connected to the output of the valve state sensor unit 5. The output of the first element 8 2I-NOT connected to the start input 26 of the block 4 distribution and amplification of the unlocking pulses, and the output of the second element 9 2I-NOT connected to the second input 12 interrupt WB 1: Block 5 sensors of the state of the valves and the sensor 10 phase rotation are connected to three phases A. B, C of the network supplying the VP 27 with a load of 29, and to one of the output terminals (for example, terminal K) of the VP 27. The synchronization unit 2 (see Fig. 2) is single-channel and contains a single-phase isolation transformer 29 , the primary winding of which is connected to one of the phases (any) A. B C and to neutral N

power supply, and the secondary winding through a series-connected diode 30 and resistor 31 are connected to the inputs of the comparator 32. the output of which is the output 5 of the synchronization unit 2. Block 4 distribution and amplification of unlocking pulses (see Fig. 3) consists of a register-latch 33 associated with a common bus 13 WB 1, two buffer elements 34 and 35 with a selection of 2I and

0 six six-channel amplifiers 36 and 37 of the power of the unlocking pulses, the outputs of which are connected respectively to the control electrodes of the valves of the bridge M1 and bridge M2 VP 27. Each amplification channel

5 six-channel power amplifiers 36 and 37 can be performed, for example, according to the scheme (see Fig. 4) of a transistor amplifier stage with galvanic separation of the input and output circuits. AT

The structure includes the resistors 38.39, the transistor 40, the pulse transformer 41 and the diodes 42, 43. The block 5 of the state sensors of the valves (see Fig. 5) consists of three sensors 44, 45, 46 of the state of the valves of the VP 27 ,

5 inverter register 47 and element 48 ZI. Each of the three sensors, for example, sensor 44, contains a single-phase rectifier bridge 49 connected by AC terminals in parallel with two monitored valves, limiting resistor 50. Zener diode 50 and optocoupler 52, the output of which is connected to the input of the corresponding inverter of register 47. Inverter outputs register 47 are connected respectively to

5 to the inputs of the element 48 ZI, the output of which is the output of the block 5 sensors state valves. The phase rotation sensor 10 (see Fig. 6) contains three resistors 53, 54, 55 connected to the star, connected respectively to the phases A, B, C of the network supplying the VP 27, and an optocoupler 56, the input circuit of which is connected between the common point 57 connection of resistors 53, 54. 55 and one of the output terminals (for example K) VP 27, and the output

5, the optocoupler 56 is the output of the phase rotation sensor 10.

For the implementation of the device can be used: as WB 1 - chip K1816BE51 (single-chip micro0 computers); Elements 3, 6. 7 - one chip KR580VI53 (three-channel programmable timer); 8, 9 - K555LAZ (4 elements 2I-NOT), 52, 56 - AOT128 (optocoupler) 33 - K555IR23 (8-bit register-latch);

5 34, 35 - K555LP10 (buffer element with a sampling of 2I); 47 - K555LN1 (6 elements NOT); 48 - K555LIZ (3 elements ZI).

The device for controlling the VI operates as follows.

After turning on the power, WB 1 implements the algorithm of a digital single-channel synchronous system of pulse-phase control (SIFU) by a two-bridge VI. As is known, a three-phase VP for a period of mains voltage has six conduction zones (60 electric degrees each), characterized in that the load current in each conduction zone flows only in series of two specific valves, selected depending on the number of the conduction zone and the range of the valves opening angle working bridge. The single-channel SIFU is constructed in such a way that its algorithm starts at the beginning of each conduction band (at the points of natural switching of the valves). The code of the pair of valves that come into operation is determined from the code table recorded in the read-only memory of WB 1 and is changed six times during the mains voltage period similarly to the known device.

In the proposed device, in contrast to the known one, synchronization of SIFU from the network is carried out by a single-channel synchronization unit 2 (see Fig. 2). The phase voltage from the secondary winding of the isolation transformer 29 through the diode 30, the limiting resistor 31 is supplied to the inputs of the comparator 32. At the output of the comparator 32, a signal is generated in the form of rectangular pulses of a duration equal to the duration of the half-period of the mains voltage, and fed to the second input 17 of the port I / O WB 1. A high logical level of this signal corresponds to a positive value of the voltage at the input of synchronization unit 2, and a low logic level corresponds to a negative value. The output signal of synchronization unit 2 is fed to the second input of the input-output port of WB 1. WB 1 analyzes this signal and, at the moment of signal level change (along the edge), corresponding to the points of natural switching of VP 27 valves, starts the SIFU algorithm to the beginning. Because synchronization unit 2 for each half period of the mains voltage changes the output signal level only once, then. The SIFU algorithm is started at the beginning in only one conduction band, and in the next two zones of conduction, the SIFU algorithm is started at the beginning by software by counting from the first point of natural switching time intervals equal to 1/6 and 1/3 of the network voltage period, respectively (i.e. after 60 and 120 electric degrees).

The time delay for turning on the VP 27 valves relative to the points of natural

switching (unlocking angle of the valves), in contrast to the known device, is provided using only one counter 3. Moreover, the set delay value for turning on the valves in the form of a binary number is transmitted to WB 1 via a common bus 13 and recorded in the counter's internal register 3. Clock pulses WB 1 output

14 are fed to the clock input 20 counts - 0 of the counter 3. The control algorithm is implemented in such a way that at the moments of natural switching of the VP 27 VB 1 valves at the output

15 I / O port generates a signal that starts the counter 3 at input 21. after

5 whereby each clock pulse at input 20 reduces the contents of counter 3 by one until it becomes equal to zero. At this moment, at the output 22 of counter 3, a narrow rectangular pulse is formed, which starts a programmable timer 6 at input 23, which generates a pulse with a duration that ensures reliable unlocking of the valves (the pulse duration is set depending on the nature of the load 28). From the output 24 of the programmable timer 6, a wide rectangular pulse is fed to the first input of the first element 8 2I-NOT, the second input of which from the output 25 of the frequency divider 7 of the clock frequency continuously receives pulses with a frequency of about 50 kHz, obtained by dividing the clock frequency from output 14 WB 1 to the input 19 of the divider 7. Thus, at the output of the first element 8 2I5 NOT after counting the specified time delay from the points of natural switching valves VP 27 form a pulse train with a frequency of 50 kHz of a given duration, which is received is run at the input 26

0 of the control amplification and distribution unit 4 of the control pulses and allow the passage of pulses to the control electrodes of the valves.

Pulse from output 22 of counter 3, except

5, it enters the first input 11 of the interruption of the WB 1, causes the interruption of the main SIFU program, and initiates the execution of the subroutine for selecting the valves and the VP27 bridge. In this case, WB 1-, similarly

0 to a known device, selects from a read-only memory in accordance with the number of the current conduction zone VP 27 and the range of the valves unlocking angle a code corresponding to that pair of valves and

5 of the bridge, which should be operational at the moment, and transmits this code in the form of a single-byte number on a common bus 13 to the latch register 33 of the allocation and amplification blocking unit 4. This code is stored in latch register 33 and

respectively, at the inputs of the buffer elements 34, 35 until the next recording cycle in the next conduction band In the single-byte code, the lower six bits determine the numbers of the gates that should come into operation, with 1 turning on and О turning off the corresponding valve. The most significant two bits are transferred from register 33 to the first inputs of the sample of buffer elements 34, 35, respectively, and determine the choice of the bridge that enters into operation, while O enables and 1 disables the operation of the bridge. At the second inputs of the sample of buffer elements 34, 35, at the instants of the counting of the specified time delay for turning on the valves, a packet of pulses is supplied from the output of the first element 8 2I-NOT. The buffer elements 34 and 35 pass the control code to the power amplifiers 36 or 37 only when low level signals are applied to both inputs of the sample of these elements. Therefore, the control code at the output of the buffer elements 34, 35 and, respectively, at the inputs of the power amplifiers 36 37 appears only at the moment of arrival of the pulse train to the trigger input 26, and this code is modulated in time by the frequency of filling the pulse train (i.e., 50 kHz). In practice, it turns out that the pulse train passes through those buffer channels amplifiers 34, 35, input which was filed logic high level signal. Power amplifiers 36, 37 provide pulse amplification to the level necessary for reliable switching on of the VP 27 valves. In each amplification channel, control pulses are supplied through the current-limiting resistors 38, 39 to the base of the transistor 40, the collector load of which is the primary winding of the pulse transformer 41. The protection of the transistor 40 from the self-induction EMF is provided by the diode 42. From the output winding of the pulse transformer 41, the unlocking pulses are fed through the diode 43 to the control electrodes of the corresponding VP 27 valves.

The formation of the unlocking pulses in the form of a packet of pulses of the required duration provides, firstly, a more stable operation of the VP with inductive load 28 in comparison with the known device; secondly, it reduces the dimensions of the pulse distribution and amplification unit 4 by using small-sized pulse transformers 41.

To implement the switching algorithms (reverse) of the bridges M1 and M2 VP 27 similarly to the known device used

valve state sensor unit 5. However, it consists of only three 44.45 sensors.

46 state valves VP 27, which simplifies the design of the device. The operation of each of the sensors 44, 45, 46 is based on the fact that when the valve is closed, a significant voltage is applied to it, and when it is open, the voltage on it is close to zero. This voltage is rectified by the bridge 49, limited to a certain level by the resistor 50 and the zener diode 51, and fed to the input of the optocoupler 52. If the valve is closed, then the output of the optocoupler 52 receives a low-level logic signal corresponding to the absence of current through the controlled valve, if If the valve is open, the voltage on the NSM is close to zero and a high level logic signal appears at the output of the optocoupler. Logic signals of all sensors 44, 45, 46 invert register

47 and served on the inputs of the element 48 ZI. A high level logic signal appears at the output of the ZI element 48 if there is no current in all the valves of both bridges. If at least one of the valves of the VP 27 is in the open state, then the output of the ZI element 48 will have a low level signal. To eliminate the through short circuit when switching bridges M1 and M2 of the VP 27, it is necessary not only to fix the moment of the end of the current flow in all the valves of the working bridge, but also to make a certain delay in switching on the bridge that comes into operation, necessary for reliable closing of the valves. The magnitude of this delay is determined by the absorption time of the carriers in the semiconductor structure of the valve (about 400 µs). To implement this switching algorithm for the M1 and M2 VP 27 bridges, the signal r of the valve state sensor unit 5 is supplied to the second input of the second element 2 2-NAND, to the second input of which pulses with a frequency of 50 kHz from the 7-clock frequency divider are constantly applied. At the output of element 9, 2I-NOT pulses with a frequency of 50 kHz appear only if there are high-level logic signal gate state sensors at the output of block 5, i.e. at the moments when all valves of both bridges M1 and M2 are in a closed state. From the output of element 2I-NOT, these pulses at the first input of interrupt 11 are supplied to WB 1 to accurately count the time delay between the moment the WB 1 receives a command to switch bridges M1 and M2 (reverse VP 27) and the start of the reverse routine. The switching algorithm of the bridges M1 and M2 is constructed in such a way that upon receipt of a command to reverse to WB 1. the latter writes a negative number in its internal counter, equal in magnitude to the quotient from dividing a given time delay by a frequency period of 50 kHz (for example, to implement a time delay equal to 400 μs, this number is minus 20). WB 1 increases the recorded number by one each time the signal at its input 11 goes from high to low. After the countdown of the set number (the set time delay), the WB 1 counter overflows, which causes the interruption of the main SIFU program and the transition to the reverse maintenance routine. In this subroutine, B B 1 changes the most significant bits in the codes transmitted to the control pulse allocation and amplification unit 4, and thereby switches the bridges M1 and M2BP27.

The use of a clock divider 7 in conjunction with a block 5 of the state sensors of the valves, element 9 2I-NOT and B 1 allows to increase the reliability of switching bridges M1 and M2 when reversing the VP compared to the known device, due to a more accurate count of the specified time delay , and also allows to reverse for the minimum time possible for a given type of VP valves, which is necessary for constructing a VP with high dynamic properties. In addition, the proposed technical solution allows measuring the value of dead time (or conduction angle of valves) in the intermittent current mode, which is necessary for constructing an adaptive current controller when using the device in an electric drive (see, e.g., A.V. Bashirin. V.A. Novikov, G.G., Sokolovsky. Control of electric drives. Leningrad: Energoizdat, 1982.- 392 p., Pp. 306-309). Since the dead time pause corresponds to the closed state of the VP 27 valves and, accordingly, the high level of the signal at the output of the valve state sensor unit 5, the value of the dead time is determined by counting the number of pulses with a frequency of 50 kHz at the output of the 9 2I-NOT element during its existence a high level signal at the output of the valve condition sensor unit 5.

The automatic synchronization introduced into the proposed device (SIFU auto-phasing4 with the voltage of the three-phase power network supplying the VI) is designed to eliminate the emergency mode that occurs when the device is turned on if the device is incorrectly connected to the mains. The fact is that the synchronization circuit ( primary winding of isolation transformer 41 of synchronization unit 2 and power circuit (terminals A,

B, C) VP 27 is connected to the supply network through various switching and protective devices. Therefore, as well as due to the erroneous actions of the electric staff, the probability of disturbing synchronization

0 of these circuits when installing the device or when connecting it to the network is quite large. Automatic phasing of SIFU is carried out immediately after turning on the converter in operation as follows.

5 First, WB 1 determines which of the phases A, B, C of the supply network connected to the VP 27 is connected to the input of the synchronization unit 2 (i.e., the phases of the synchronization circuit and the converter power circuit are identified). Then, the phase sequence order is determined and then the sequence of control pulse codes corresponding to the actual connection of the phases of the supply network to the device is selected from the WB 1 memory. The principle of autophasing is that at times when the logic signal at the output of synchronization unit 2 is at a high level, the control electrode is V1 of the B1 bridge Ml (in the case when the LED of the optocoupler 56 of the phase rotation sensor 10 is connected by the anode to the output terminal K VP 27) constantly supply unlocking pulses and measure the signal level 5 at the output of the phase rotation sensor 10 through an interval of 30, 90, 150 el. degrees relative to the positive edge of the signal at the output of block 2 synchronization. The obtained result in the form of a three-bit binary code is fixed in one of the registers (for example, X1) of the operative memory of VB 1. Then the valve B1 is turned off and at the next moment, when the signal at the output of synchronization unit 2 has a high level, they turn on in a similar way first the gate V3, then the gate B5, and the results of measuring the state of the sensor 10 are recorded in two other registers (for example X2, X3J. Next, analyze the values of the registers X1, X2, XZ. In the event that the switched-on valve was connected by the anode to the same phase as block 2 synchronization, three-bit code in the corresponding register should be equal

5 zero, because during the entire half-voltage period, when this phase was positive, the output signal of the synchronization unit 2 was at a high level, and the phase rotation sensor 10 at the output had a low logic signal, since the current flowed through the optocoupler LED 56 for almost the entire half-period. In this way, the number of the phase connected to the synchronization unit 2 is identified with respect to the phases connected to the rectifier bridges of the VP 27.

In the other two registers X there can be only two codes 110 and 011, because two other phases are shifted relative to the identified +120 e. degrees, and through the optocoupler LED 56, current could flow only with a positive voltage value of the respective phases. Moreover, if the valve turned on immediately after the valve of the identified phase corresponds to code 110. then the sequence of phases connected to the VP 27 is straight forward, if the code is 011, then the reverse.

Therefore, the introduction of the phase rotation sensor 10 and the implementation of the phase identification algorithm described above allows you to automatically physics the SIFU regardless of which phase A, B or C the primary winding of the isolation transformer 41 of synchronization unit 2 is connected to and in what order are connected terminals A. B, C at the input of VP 27 to the phases of the supply network.

The described control algorithm for the VI corresponds to the block diagram of FIG. 7.

Block A1: initial installation and initialization of WB 1.

Blocks A2-A8: SIPU autophasing after power is turned on. Wherein:

block A2 - waiting for a high level of a logical signal from synchronization block 2;

block A3 - supply of unlocking pulses to the valve B1, measuring the signal level at the output of the sensor 10 phase rotation through 30, 90, 150 el. degrees from the moment of occurrence of a positive edge of the signal of synchronization unit 2 and recording of a three-bit status code in the memory register X1 of WB1;

blocks A4, A6 - similar to block A2;

blocks A5. A7 are similar to block A3, only the unlocking pulses are supplied to the valves ВЗ, В5, respectively, and the status code is recorded in the registers X2. HZ;

block A8 - phase identification, determining the order of phase rotation by codes in the registers X1, X2. ХЗ ВБ 1 and selection of the control pulse code table from the constant memory ВБ 1. which corresponds to the actual connection of the device to the phases of the mains.

Block A9: - initial setting of the number N of the conduction band of VP 27: N - 1

Block A10: waiting for a change in signal level (edge) from synchronization block 2

Block A11: - the initial installation of the number M of the point of natural switching VP 27: M 5 1.

Block A12: loading from the output 15 of the input-output port of the WB 1 to the counter 3 by the input 21 of the start of the number defining the specified time delay of the control pulses (unlock angle of the valves) from the natural switching point of the valves of the VP 27 and the start of the counter 3.

Block A13: calculating the time delay of the control pulses for the next conduction zone 5 of the VP 27 and analyzing the need to switch bridges M1 and M2 (VP reverse).

Block A14: permission to interrupt the main SIFU program upon receipt of a reverse command 0 in BB 1 and writing to the WB 1 a number defining the time delay of switching the VP 27 bridges,

Block A15: N N-1 - increment of the conduction band number of VP 27. 5 Block A16: if N 6, then go to the block

A9.

Block A17: M - M - 1 - increment of the natural switching point number VP 27.

B / o A18: if M 2 or 3, then the transition

0 to block A11. same M 3, then the transition to

block A10. When the program is compiled

so that the time taken

WB 1 for processing blocks A11-A18, was

equal to 1/6 of the mains voltage period (60

5 email degrees).

The subroutine for selecting the valves and the VP 27 bridge is implemented by blocks B1-84.

Block B1: start of the subroutine for the selection of valves and the VP 27 bridge.

0 Block B2: selection of the code of impulse control pulses from the read-only memory, depending on the number N of the conduction band and the range of the valves opening angle.

Block VZ: latching in the register-by-click 33 of a single-byte code defining the number of a pair of gates and the number of the bridge that comes into operation.

Block B4: the end of the subroutine for the selection of valves and the bridge VP 27 and the transition to 0 the main program. The reverse maintenance routine is implemented by blocks C1-C4.

Block C1: start of the reverse maintenance routine.

5 Block C2: changing the number of the working bridge in the register-latch 33.

SZ block: prohibition of interruption of the main SIFU program in the absence of a reverse command.

Block C4: end of the reverse maintenance subroutine and transition to the main SIFU program.

Thus, the proposed device in comparison with the known device provides:

-increasing the reliability of switching the VP bridges when reversing in the shortest time, increasing the stability of the VP arrays to inductive load, as well as reducing the size of the distribution block and amplifying unlocking pulses - by introducing a divider, programmable timer, two 2I-NOT elements, their interconnections with the rest elements of the device, as well as corresponding control algorithms;

- simplification of the design, synchronization unit and valve status sensor unit;

-exclusion of emergency conditions and reduction of setup time during

Claims (3)

1. VENTILATION CONTROL DEVICE A CONVERTER containing a computing unit with inputs for determining the moment the valves are turned on, a clock output, outputs of the signal of the moment of natural switching of the valves and setting the delay value for turning on the valves, a synchronization unit with an isolation transformer, the primary winding of which is designed to be connected to the mains, the output of the synchronization unit is connected to the input of the synchronization signal of the computing unit, a clock pulse counter with information, input, clock and trigger inputs, and a distribution and amplification block of unlocking pulses with a trigger input and an information input, the outputs of which are used to connect the converter valves to the control electrodes, the information input - to the output of the bridge number and valve number of the computing unit, and the sensor block of the converter valve status, inputs which are designed to be connected to a network supplying a valve converter, characterized in that it is equipped with a programmable timer, a clock divider with information inputs s, clock and trigger inputs, two 2NI-NOT elements, and the computing unit is equipped with an input for determining the reverse moment, an output for setting the duration of the control pulse and an output for setting the division ratio, 5 1 1 2 putting the device into operation due to the introduction of a phase rotation sensor and an automatic SIFU phasing algorithm with the voltage of a three-phase network supplying the VP into the device; - expanding the functionality of the device when implementing current controllers with adaptation to the intermittent current mode - by obtaining information about the value of dead time (or conduction angle of VP valves) and implementing the corresponding algorithms in the WB. Therefore, the proposed device ensures the achievement of the goal. (56) USSR Copyright Certificate Ms 1146781, cl. H 02 P 11/00, 1984. USSR copyright certificate Ns 1206951. cl. H 02 H 7/12, 1985. the inputs of the programmable timer and the clock divider are connected respectively to the output of the job of the duration of the unlocking pulse and to the output of the job of the division coefficient of the computing unit, and the clock inputs are connected to the output of the clock frequency of the computing unit, the start input of the clock counter is connected to the output of the signal of the moment of natural switching of the valves , the information input of the counter is connected to the output of setting the value of the delay on valves, the output of the clock counter is connected to the start input p the programmable timer and the input for determining the moment the valves of the computing unit are turned on. The output of the programmable timer is connected to the first input of the first 2I-NOT element, the output of the clock divider is connected to the second input of the first 2I-NOT element and with the first input of the second 2I-NOT element, the second input which is connected to the output of the unit of sensors of the state of the valves of the converter, the output of the first element 2I- is NOT connected to the input of the start of the distribution and amplification of unlocking pulses, and the output of the second element 2LI-HE is connected to the input of the unit of the reverse moment of the computing unit. 2. The device according to claim 1, characterized in that it is equipped with a phase rotation sensor, and the computing unit has an input for detecting phase rotation of the supply network, wherein the phase rotation sensor is made in the form of three resistors connected to a star connected to the corresponding phases of the supply network of the valve a converter, and an optocoupler, the input circuit of which is connected between a common point of connection of the resistors and one of the output terminals of the valve converter, and the output circuit of the optocoupler is connected to the input of phase rotation network computing unit. 3. The device according to claims 1 and 2, characterized in that the synchronization unit is made it is single-channel, and the isolation .. transformer is single-phase, with one end of the secondary winding of the latter through a diode and a resistor connected in series to one input of the comparator, the other end to the other input of the comparator directly, the output of the comparator used as the output of the synchronization unit. thirteen U 34 iii; WITH o 8 eat : i i D u u- - s U) L Ј i G, G; CD L Ј X h oi o fll) AND P.I IXII B2 83 1 B4 fil