RU196141U1 - Three-phase digital sine wave generator - Google Patents

Abstract

The utility model relates to digital conversion technology and can be used to synthesize a three-phase digital sinusoid code in digitally controlled DC and AC drives. The technical result is an increase in accuracy and symmetry with the simultaneous formation of three phases of a digital sinusoidal signal with a fixed 120-degree phase shift. For this, a three-phase digital sinusoidal signal generator contains a fixed-frequency rectangular pulse generator 1, a k-bit counter of pulses of a binary code 2, a divider-counter of a six-phase code 3, a shaper 5, invert blocks 4 and 6, logical blocks 7, 8, 9, identical channels of the 1st, 2nd, 3rd, which consist of switches and a two-input binary digital adder. 3 ill.

Description

The utility model relates to digital conversion technology and can be used to synthesize a three-phase digital sinusoid code in digitally controlled DC and AC drives.

A known generator of three-phase sinusoidal signals (USSR Patent No. 1543534, H03B 27/00, publ. 02/15/1990, BIMP No. 6), containing a control unit, a variable frequency generator, a reversible counter, constant memory blocks, digital-to-analog converters, adders, correction block .

The main disadvantage of this device is the presence of analog conversion and read-only memory blocks, which does not allow to obtain an integrated circuit design.

The closest in technical essence to the claimed technical solution is a digital sinusoidal signal generator (RF Patent No. 2670028, Н03В 19/00, publ. 10/17/2018, BIPM No. 29), which uses the digital generation of a symmetric sinusoid with the possibility of increasing the bit depth of the output signal.

However, in this device it is not possible to obtain a sinusoid with the required phase shift.

The technical result obtained by the implementation of the claimed utility model is expressed in increasing accuracy and symmetry with the simultaneous formation of three phases of a digital sinusoidal signal with a fixed 120-degree phase shift.

This is achieved by the fact that the output of the binary counter digit k-1 is connected to the input of the divider-counter of the six-phase code, the outputs of which are connected to the logic blocks, the switches are inserted into the device of the digital sinusoidal signal generator, which contains the master oscillator, the output of which is connected the first inputs of which the outputs of the pulse counter of the binary code, the signals from the inverting units and the shaper, the second inputs of the switches receive signals from the logical blocks, the outputs ommutatorov fed to the two-input binary adder, an output code which determines the digital sine wave signal of a fixed phase offset.

In FIG. 1 shows a structural electrical diagram of the proposed device; in FIG. 2 - structural electrical diagram of the 1st channel; in FIG. 3 is a diagram of the operation of the proposed device.

The three-phase digital sinusoidal signal generator (Fig. 1) contains a fixed-frequency rectangular pulse generator 1, a k-bit binary code 2 pulse counter, a six-phase code divider-counter 3, a B ⁺ signal shaper 5, inverters 4 and 6, logic blocks 7 , 8, 9, identical channels of the 1st, 2nd, 3rd, which consist of switches 10, 11 and a two-input binary digital adder 12 (Fig. 2).

The proposed device operates as follows.

The pulses of a stable frequency ƒ = const from the master oscillator go to the input of the binary counter 2 ^k , where k is the bit capacity. The k-1 bit of counter 2 goes to the input of the divider-counter of the six-phase code 3, the outputs of which m _{1 ...} m ₆ are inputs of logic blocks 7, 8, 9 having six output signals c _{1U ...} c _6U , c _1V ... c _6V , c _{1W ...} with _6W represented by the following dependencies:

с блока инвертирования 4 и сигналы А⁼¹={a ₁=а ₂=…=a _k=1}. Сигнал В⁺ формируется в блоке 5, на вход которого поступают сигналы А⁺={a ₁…a _k} со счетчика 2, в соответствии с заданными математическими соотношениями параметров

и поступает на блок инвертирования 6. Сигналы B⁺=(b₁÷b_k) с формирователя 5, инвертированные сигналы

с блока инвертирования 6 и сигналы B⁼¹={b₁=b₂=…=b_k=1} поступают на первые входы коммутатора 11. На вторые входы коммутаторов 10, 11 поступают сигналы с логических блоков 7, 8 и 9, которые управляют работой коммутаторов 10 и 11 (в каждом канале) таким образом, что на выходе сумматоров образуются двоичные цифровые коды синусоид со 120-градусным фазовым сдвигом. Коммутаторы 10, 11, пропускают на выходы коды А' и В', которые поступают на входы сумматора 12, где реализуется арифметическая операция сложения, выходы которого являются шинами выходного сигнала.The output signals c _{1U ...} c _6U , c _1V ... c _6V , c _{1W ...} c _{6W of} logic blocks 7, 8, 9 are fed to the second inputs of switches 10, 11. The signals A ⁺ = { a ₁ ... a are sent to the first inputs of switch 10 _k } from counter 2, inverted signals

from inverting unit 4 and the signals A ^{= 1} = { a ₁ = a ₂ = ... = a _k = 1}. The B ⁺ signal is generated in block 5, the input of which receives the signals A ⁺ = { a ₁ ... a _k } from the counter 2, in accordance with the specified mathematical relations of the parameters

and enters the invert unit 6. Signals B ⁺ = (b ₁ ÷ b _k ) from the driver 5, inverted signals

from inverter unit 6 and the signals B ^{= 1} = {b ₁ = b ₂ = ... = b _k = 1} are fed to the first inputs of switch 11. The second inputs of switches 10, 11 receive signals from logic blocks 7, 8 and 9, which control the operation of switches 10 and 11 (in each channel) in such a way that binary digital sinusoid codes with a 120-degree phase shift are generated at the output of the adders. The switches 10, 11, pass the outputs of the codes A 'and B', which are fed to the inputs of the adder 12, where the arithmetic operation of addition is implemented, the outputs of which are the output signal buses.

All conversions in the device are performed in a discrete form and full implementation in an integrated version is possible.

Claims (1)

A digital sinusoidal signal generator comprising a master oscillator, the output of which is connected to a binary code pulse counter, the output of the k-1 bit of a binary counter is connected to the input of a divider-counter of a six-phase code, the outputs of which are connected to logic blocks, characterized in that the switches are inserted into it, the first inputs of which the outputs of the counter of pulses of the binary code, the signals from the inverting units and the shaper, the second inputs of the switches receive signals from the logical blocks, the outputs of the commutator s are fed to the two-input binary adder, an output code which determines the digital sine wave signal of a fixed phase offset.

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