RU1828741C - Heart beat rate inspecting unit - Google Patents

Abstract

The invention relates to medicine and can be used to monitor the state of the human cardiovascular system. The aim of the invention is to increase the reliability of control while simplifying the control procedure. The device comprises a shaper unit 1, a ratio determination unit 3, a frequency determination unit 4, a comparison unit 5, and a block 6 control, analog-to-digital Converter 7 cheshz 8 indications, trigger 9. 2 zp, 8 il i)

Description

The invention relates to medicine and can be used to monitor the condition of the patient's cardiovascular system.

The aim of the invention is to increase the reliability of the control of the patient's cardiovascular activity during testing, while simplifying the control procedure.

The object of the invention is achieved in that a control unit comprising a period meter counter, a logic device, an averaging counter, a control device, keys are additionally provided with a driver unit, a memory unit, a ratio determination unit, a frequency determination unit, a comparison unit, analog-to-digital converter, display circuit, trigger, first to fourth outputs of the block

peacekeepers are connected respectively with

the first input of the memory unit, the combined fourth inputs of the memory unit and the control unit, the combined third input of the unit and the first input of the control unit, the start input of the analog-to-digital converter (ADC), the second input of the memory unit is connected to the TI bus, its first and second the outputs are connected respectively to the first inputs of the ratio determination unit and the frequency determination unit, the second and third inputs of the latter are connected respectively to the fourth and fifth outputs of the control unit, and the output is connected to the ADC input and the second input ratio determination unit, the output of which is connected to the third input of the comparison unit, the first and second inputs of which are connected respectively to the third output of the control unit and the first input of the driver unit, the ADC code outputs are connected to the inputs of the display circuit, the initial reset bus is connected to the second input of the unit control and the second trigger trigger input, the Start bus is connected to the third input of the control unit, the fifth input and the first and second outputs of which are connected respectively to the output End of the ADC measurement, fifth a memory input and a first reset input of a trigger, the installation input of which is connected to the output of the comparison unit, and the output is an Alarm signal,

Consider how the device is used to monitor the patient's cardiovascular activity. Percent tolerances are initially set. After the adaptation time, the pulse value, which is then taken as the initial value, is measured and stored. Subsequently, the flow is continuously measured.

0 5

0

5 0 5 0 5 0

5

value of the pulse and the ratio of its value to the stored initial value is determined, if this ratio exceeds the maximum permissible deviations, a specified number of times an alarm is generated.

Since the initial value of the pulse is measured after the start of the tests and can significantly differ from the value of the pulse before they begin, the proposed monitoring sequence allows to increase its reliability.

The behavior of all measurements after the start of testing simplifies control and allows it to be automated, which is carried out in the proposed device.

All elements indicated in the characterizing part of the formula are widely known and are used for their intended purpose. A new is the interconnection of elements, which allows for reliable cardiovascular activity of the patient during the test process while simplifying the control procedure. Schemes similar to those proposed are not known. The foregoing allows us to conclude that the differences in the proposed technical solution are significant.

In FIG. 1 shows a functional diagram of the proposed device; in FIG. 2 is a time diagram of its operation; Figs. 3-8 are specific examples of implementations of a driver unit, a memory unit, a ratio determination unit, a frequency determination unit, a comparison unit, a control unit;

The device comprises (Fig. 1) a driver unit 1, a memory unit 2, an attitude determination unit 3, a frequency determination unit 4, a comparison unit 5, a control unit 6, an ADC 7, an indication circuit 8, a trigger 9.

The first and fourth outputs of the driver unit 1 are connected respectively to the first input of the memory unit 2, combined by the fourth inputs of the memory unit 2 and the control unit 6, combined by the third input of the memory unit 2 and the first input of the control unit 6, the start input of the analog-to-digital converter 7 (ADC), the second input of the memory unit 2 is connected to the TI bus, its first and second outputs are connected respectively to the first inputs of the ratio determination unit 3 and the frequency determination unit 4, the second and third inputs of the latter are connected respectively with the fourth and fifth outputs of the control unit 6, and the output is connected to the input of the ADC 7 and the second input of the ratio determining unit 4, the output of which is c °. with the third

the input of the comparison unit 5, the first and second inputs of which are connected respectively to the third output of the control unit 6 and the first input of the driver unit 1, the ADC code outputs 7 are connected to the inputs of the display circuit 8, the initial reset bus is connected to the second input of the control unit 6 and the second trigger input 9, the Start bus is connected to the third bypass of control unit 6, the fifth input and the first and second outputs of which are connected respectively to the output End of ADC measurement 8, the fifth input of memory unit 2 and the first trigger input of the trigger 9, the installation stroke of which is connected to the output of the comparison unit 5, and the output is an Alarm signal.

In FIG. 2 shows the following voltage plots; a- at the input of 1 block of the formers; b - at the output of the counter 10 of the block 1 shapers; in - at the output of 1 block 1 shapers; g - at the output of 2 block 1 shapers; d - at the output of 3 block 1 shapers; e - at the direct output of the trigger 45 of the control unit 6; g - at the output of 1 control unit 6; h - at the output 4 of the control unit b; and - at the direct output of the trigger 47 of the control unit 6; k - at the output 3 of the control unit 6; l - at the output of the operational amplifier 44 bpoks 5 compared; m - voltage Ep

According to FIG. 3 block 1 shapers contains a counter-divider 10, shapers 11, 12, delay elements 13, 14.

According to FIG. 4, memory unit 2 contains AND element 15, counter 16, registers 17, 18.

According to FIG. 5, the ratio determining unit 3 comprises a digital-to-analog converter (DAC) 19, an operational amplifier 20, a resistor 21.

According to FIG. 6, the frequency determining unit 4 contains keys 22.23, 24.25. DAC 26. operational amplifier 27, resistor 28.

According to FIG. 7, comparison unit 5 contains comparators 29, 30, OR element 31, AND elements 32, 33 AND, element 34, counters 35, 36 with decoders, trigger 37, formers 38 39, switch 40, resistors 41, 42, 43, operational amplifier 44.

According to FIG. 8, the control unit 6 includes a trigger 45, a delay element 46, flip-flops 47, 48, an AND element 49, a driver 50. An AND element 51, back-up elements 52, 53.

The device operates as follows. The signals from the sensor are input to the counter 10 of the period meter (Fig. 2a) of the shaper unit 1, at the output of which a positive or negative pg is generated. -., yll, equal in duration to peomods. i -, lsa. Shaper 11 of the shaper block generates a pulse (Fig. 2c) from any edge of the signal (positive or negative), which blocks the arrival of clock pulses through element 15 AND of memory block 2. In addition, since the blocking action takes place, the information is transferred from the counter 16 to the memory register 17 (Fig. 2d) b ok, 2, after which the counter 16 is reset to zero (Fig. 2e). and after unlocking, it accumulates clock pulses, the number of which corresponds to the current value of the pulse period. The Start signal, after a delay by element 46 of the control unit 6 equal to the estimated adaptation time, sets 1 trigger 45 (Fig. 2e), which allows data from register 17 to register 18 (Fig. 2g) of memory unit 2. From this moment on, register 18 stores the value of the pulse period corresponding to the moment of the census, relative to which the remaining transformations are performed.

The device constantly works in two modes - measuring the heart rate and monitoring the change in the pulse period relative to the beginning of the monitoring

In the pulse rate measurement mode, the DAC 26 of the frequency determination unit 4 operates in a digital-to-analog converter mode for dividing the voltage by the code. The removal of such a converter is given in the book by W. Titze, K. Schenka Popuprok DKchkova circuitry, - M .: Mig, 1983, о -152.

In this mode, the direct output of the tripper 48 of the control unit 6 opens the keys 22 and 24 of the frequency determining unit 4, through which the output of the operational amplifier 27 is connected to the input И0п. DAC 26, and the inverter input of the operational amplifier 27 is connected through a resistor 28 to the source Eop. As a result, the voltage at the output of the operational amplifier 27, which is the input to the ADC 7,

UBX ADC and 8th. OU27:

Rw2 Eon R2 Z2

where Rw2 is the internal resistance of the DAC 26;

2.2 - code at the output of the DAC 26.

Thus, at the input of the ADC 7, a voltage is obtained that is inversely proportional to the period and directly proportional to the pulse.

After that, with the delay determined by the delay element 14 of the block 1 of the shapers, the ADC is started 7. after

the completion of which the pulse is recorded in the display circuit 8, the ADC 7 generates an End of Measurement signal that resets the mode trigger 48 (Fig. 2) of the control unit 6, which corresponds to the transition to the pulse period measurement mode. In this case, the keys 23 and 25 of the frequency determination unit 4, controlled by the inverse output of the trigger 48 of the control unit 6, provide a standard mode for turning on the DAC 26 of the frequency determination unit 4 as a multiplying DAC: to the input И0п. the constant voltage E0n is connected, and the output of the operational amplifier 27 through a resistor 28 is connected to its inverse input. The voltage at the output of the operational amplifier 27 at this time is proportional to the pulse period.

Kvyh OU27 (T):

-on

Z2

Rw2

On the DAC 19 and the op amp 20 of the ratio determining unit 3, an operation is performed for dividing the voltage proportional to the current value of the pulse period by the register code 17 of the memory unit 2 proportional to the period at the start of the reference. At the output of the op-amp 20, the voltage is:

-op

Rwi 1g

R "2 Ri Zi

 f

A. Zi

On the operational amplifier 44, the subtraction of i.v.st and Esm is carried out, by changing the value of Esm we obtain a zero signal at the output of the op-amp 44 after the moment of the start of control.

The output voltage of the op amp 44 (Fig. 2l) is supplied to the inputs of the comparators 29 and 30, the second inputs of which are supplied with threshold voltages En + and En, which are set depending on the allowable relative change in the pulse in the direction of decreasing or increasing it. Checking the operation status of the comparators 29 and 30 is carried out by the strobe of the comparator (Fig. 2k), which you operate with a delay on the delay element 53 after the trigger 48 of the control unit 6 switches to the inverse state corresponding to the period measurement mode.

If the change in the ratio of the periods exceeds an allowable (e.g. 10% or 20%) sequentially specified number of times, an alarm trigger 9 is triggered.

A prototype device has now been developed. The device is made on integrated circuits 140. 561 series. An integrated circuit 572 PA1 was used as the DAC. The ADC is performed according to the well-known time-pulse conversion scheme with indication in decimal form on integrated circuits AL C 314. The device is designed for the possibility of

monitoring the change in heart rate up to 50% of the initial value, the range of which is 40-200 beats per minute.

The advantage of the proposed device for monitoring heart rate compared

0 with the prototype is to increase the reliability of monitoring the cardiovascular activity of the patient during the test and simplifying the control procedure. No initial measurement, heart rate up to

5 of the test start, only its permissible deviation is preliminarily set, all other measurements are performed automatically.

Claims (3)

The claims 0 1. A device for monitoring the heart rate, comprising a sensor connected in series, a driver unit, as well as a control unit, a counter and an indicator, characterized in that, in order to increase 5 reliability of the control, while simplifying the control procedure, it contains a memory unit connected in series, a frequency determination unit, a relationship calculation unit, a comparison unit and the first RS-trigger, an analog-to-digital converter, the first output of which is connected to the indicator, the first - third the outputs of the shaper unit are connected respectively to the first - third inputs 5 of the memory block, the second and fourth inputs of which are connected respectively to the first and second inputs and first outputs of the control unit, the second the output and the third input of which are connected respectively 0 to the second and third inputs of the RS flip-flop, the third output to the second input of the comparison unit, the fourth and fifth outputs, respectively, to the second and third inputs of the frequency detection unit, the fourth input of which is connected to the second output of the memory unit, the third and fourth the outputs of which are connected respectively to the second and third inputs of the ratio calculation unit, the third input of the comparison unit is connected 0 with the input of the driver unit, the fourth output of which is connected to the first input of the analog-to-digital converter, the second input of which is connected to the output of the frequency detection unit, and the second output to 5 to the fourth input of the control unit. 2. The device pop, 1, characterized in that the block of shapers contains connected in series counter, the first and second shapers, the first and second delay elements, the input of the counter is the input of the driver unit, the first and fourth outputs of which are connected respectively to the outputs of the first and second drivers, the first and second delay elements. 3. The device pop. 1, characterized in that the control unit comprises a second RS trigger connected in series, a first And element, a third delay element, a third RS trigger, a second And element and a fourth delay element, connected in series with a fourth RS trigger and a third driver the output of which is connected to the second input of the second AND element, the fifth delay element, the output of which is connected to the first input 0 5 the second RS-trigger, the second and third inputs of which are connected respectively to the first and second inputs of the third RS-trigger, the second input of the first element And is connected to the second input, and the output to the first output of the control unit, the third input of which is connected to the third input of the second RS -trigger, the first and fourth inputs, respectively, with the first and second inputs of the fourth RS-trigger, the second and third outputs, respectively, with the outputs of the fifth and fourth delay elements, the fourth and fifth outputs, respectively, with the second and first outputs the fourth RS-trigger, and the fifth input is with the input of the fifth delay element. Jl 1C P P I AM 1C Fig. E fs / 5.3 fig 6 as  TD P 39 36 s fi.v