RU1823146C - Device for receiving discrete signals - Google Patents

Abstract

The device contains: 1 limiter

Description

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The invention relates to radio engineering,

An object of the invention is to provide reception of signals transmitted using partial manipulation with minimal plumb.

In Fig.1, the image of the structural electrical circuit of the proposed device; figure 2 is a diagram of the fittings of the waveform.

The device comprises a limiter 1, an analog-to-digital converter (ADC) 2, a valve calculation unit 3, a first phase expander 4, a first decision unit

5, the third controlled key 6, the selector 7 edges and slices, register 8, the fourth controlled key 9, the selector 10 edges, the second phase splitter 11, the second decision unit 12, the RS-trigger 13. the first controlled key 14, the T-trigger 15, a second controlled switch 16, an inverter 17, a second pulse shaper 18, a first pulse shaper 19, a frequency divider 20, an AND element 21, an OR element 22, a clock pulse generator 23, a waveform analyzer 24. The analyzer 24 contains a rectifier 25, an electronic key 2G, a threshold unit 27, counters 28, 29.

The device operates as follows.

The received signals are sent simultaneously to the inputs of limiters 1, ADC 2 and dialyzer 24, the output of which, depending on the shape of the input signal, sets a high level of unity or a low level of zero. This level is supplied to the control inputs of all four controlled keys 6, 9. 14, 16. If a discrete signal is input to the input of the device to be installed, then the output level of the analyzer 24 is set to the unit level, which affects four controlled keys

6.9, 14. 16.

If, however, a signal using frequency modulation with a minimum shift arrives at the input of the claimed device, then the output level of the analyzer 24 is set to zero, which acts on the four controlled keys 6, 9, 14, and 16 in such a way that the RS- inputs the trigger 13 connects the outputs of the decider 5, and to the shapers 18 and 19 the outputs of the phase shifter 11 connect the outputs of the decider 12 respectively. 8 as a result of this configuration change, the phase adjustment of the pulses at the output of the divider 20 is carried out as described higher than the mechanism, but under the influence of signals from the outputs of the decisive block 12. At its inputs, another sample of

the input signal from the output of the ADC 2 and delayed by the duration of sending T samples from the signal from the output of the register 8. The value of the amplitude of the signal from the output of the block 3 is received at the corresponding input of the decision block 12. Phase adjustment is performed according to the sign of the sample falling into the doubled frequency oscillations, taking into account the sign of the sample held in register 8. If this sample falls approximately in the middle of the doubled frequency oscillation, then its modulus is much smaller than the amplitude of the frequency-shift signal with minimal shift. This factor is a sign.

5 that the sign of this sample can be used to adjust the phase of the pulses from the output of the T-trigger 15. Moreover, if the previous sample is modulo large and close to the amplitude, then with the same signs

In the next and previous samples, an addition pulse is generated. With different signs of the next and previous samples, an exclusion pulse is generated. In other cases, when both samples are modulo large or both small, add and exclude pulses are not generated. Thus, the phasing of the control pulses of the sampling instants from the input signal to the control inputs of the ADC 2 and the register 8 from the output of the isolator 10 is ensured. The output signal is generated using the decision block 5. In FIG. its input is sampled from the output of ADC 2, and to another input 5, the signal amplitude is from the output of block 3. If the sample is modulo close to the amplitude of the signal, then, depending on its sign, a pulse is generated at one of the two outputs of the decision block 5. With a positive sampling, this pulse from one output of the decision block 5 through the controlled key 6 is fed to the S-input of the RS-trigger 13 and sets it to unity. With a negative sample, the pulse appears

5 other output of the decision block 5 and through a controlled key 9 is fed to the R-input of the RS-trigger 13 and sets it to zero,

If the sample from the signal modulo r0 is much less than the amplitude of the signal, in this Case there are no pulses at the outputs of the decision block 5, therefore, the RS trigger 13 does not change its state.

Amplitude calculator works

5 as follows. It discards small modulo samples and averages the modules to large samples

A waveform analyzer detects the presence of half-waves with a duration of about To / 2 indicate. what's at the entrance

The device operates with a frequency shift signal with a minimum shift.

Claims (1)

The absence or rare occurrence of half-waves of a To / 2 signal at its input indicates the action of a discrete signal at the input of the device. SUMMARY OF THE INVENTION A device for receiving discrete signals, comprising a series-connected clock, an OR element, an AND element, an inverter frequency divider, a front edge selector and a first phase splitter. a limiter, the input of which is the input of the device, and the output is connected to the second input of the first phase splitter and the input of the edge and slitter isolator, the output of which is connected to the first input of the phase splitter, the second input of which is connected to the output of the T-trigger, the input of which is connected to the output of the divider frequency, the first pulse shaper, the output of which is connected to the second input of the OR element, the second pulse shaper, the output of which is connected to the second input of the AND element, and also the RS-trigger, the output of which is the output of the device characterized in that, in order to ensure reception of signals transmitted using frequency shift keying with a minimum shift, a waveform analyzer, an analog-to-digital converter, a register, an amplitude calculation unit, a first, a second decision block, four controlled keys are introduced moreover, the inputs of the analog-to-digital converter and the waveform analyzer are the input of the device, the sync input the waveform analyzer is connected to the output of the edge and slice divider, and the output is connected to the control inputs of the controlled keys, the output of the analog-to-digital converter is connected to the first input of the register, the input of the amplitude calculation unit, the first inputs of the first decision block and the second decision block, the second whose input is connected to the output of the register, and the third input is to the output of the amplitude calculation unit, also connected to the second input of the first decision unit, the first output of the second phase shifter is connected to the first input of the first control key, the second input and output of which are connected respectively with the first output of the second decision block and the input of the first pulse former, the second output of the second phase splitter is connected with the first input of the second controlled key, the second input and output of which are connected respectively with the second output of the second decision block and the input the second pulse former, the output of the front edge coupler is connected to the control inputs of the analog-to-digital converter and register, the first output of the first phase splitter is connected to the first the input of the third controlled key, the second input of which and the output are connected respectively to the first output of the first decision block and the S-input of the RS-flip-flop, the second output of the first phase splitter is connected to the first input of the fourth controlled key, the second input and output of which are connected respectively to the second the output of the first decision block and the R-input of the RS-trigger. Output