RU1823113C - Single-phase converter with polyphase pulse-width modulation - Google Patents

Abstract

The converter contains m main pairs of key elements (3, 8) and an electromagnetic unit, including m located on the magnetic circuits (20-22) of the primary windings (17-19) connected to a star. The converter control unit includes a frequency master and a multiphase pulse width modulator. The converter is equipped with an additional pair of key elements (i. 2) connected in series between the power rails. Magnetic wires (20-22) are made magnetically unconnected and equipped with secondary windings (23-25). 1 s s t 4 s il

Description

The invention relates to electrical engineering, in particular to converter technology, and can be used in power supply systems for various purposes, mainly for converting a constant voltage into a high-frequency, quasi-sinusoidal one.

The aim of the invention is to improve the quality of the output voltage by reducing its distortion, expanding the area of use by eliminating the use of a special source with a midpoint, as well as expanding the functionality by providing the possibility of pulse-width

output voltage control.

To achieve this goal, the proposed single-phase converter with multiphase PWM, as well as known, contains m base pairs in series

interconnected between power rails of key elements shunted by reverse diodes. The electromagnetic assembly of the transducer includes m primary windings located on the magnetic circuits, connected to an m-phase star and connected at their ends to the connection points of said key pairs of key elements. The converter control unit includes a converter output frequency adjuster and a carrier or a multiple frequency adjuster and a multiphase pulse width modulator connected in series with the Vini / пара paraffin outputs to respective inputs of the aforementioned key elements. The mentioned signals are sequentially shifted to each other on the carrier or a multiple of the PWM frequency by an angle of 2 p / t, where t 2. V

Joint venture

WITH

from u to

with

unlike the known one, the proposed converter is provided with an additional pair of key elements connected in series between the power rails, shunted by reverse diodes, the connection point of which is connected to the zero point of the mentioned primary winding star. Magnetic cores made by magnets connected

serially connected secondary windings, the free ends of which are connected to the output terminals of the Converter. The output frequency adjuster is made with paraphase outputs SI, SI connected to the control inputs of the corresponding key elements of the additional pair.

An embodiment of the aforementioned multiphase pulse width modulator comprises m sawtooth generators and comparators, two frequency dividers, two shift registers at an angle of 2 l / t, t formers of pulse-width modulated pulse signals, sequentially shifted by an angle of 2 71 / t on a carrier or a frequency multiple to it, a synchronization node containing m 2I elements and an m element OR, a three-phase shift register of the output frequency signal and m counter-current signal conditioners fy and $, the output terminals of which They are used as the outputs of a multiphase pulse width modulator, the inputs of which are connected to the inputs of frequency dividers, the outputs are connected to the inputs of the two mentioned shift registers by an angle of 2 / t, the corresponding outputs of the first of which are connected to the inputs of m sawtooth generators and m formers modulated by duration of pulse signals. The rest of their inputs are connected to the corresponding outputs of the second shift register by an angle of 2 / m. The shift registers are made in the form of two narrow pulse shapers, outputs connected to the inputs of an OR element 2, an output connected to a clock input RST of a trigger with paraphase outputs FI, FI, one of the installation inputs of each of which is connected to the output of the synchronization node, which is used as an output said element m OR. whose inputs are connected to the outputs of the m elements of 2 AND, their inputs forming the inputs of the synchronization node, respectively connected to the input of one of the mentioned elements 2 OR. Sync node output connect 0

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It also refers to the input of a three-channel shift register of the output frequency signals, the first channel of which is used as the aforementioned converter output frequency adjuster. The outputs of each of the m sawtooth generators are connected to one of the inputs of the comparators with para-phase outputs Si, Si, the other inputs of which are combined and connected to a control signal source. The outputs Si, Si of the comparators are connected to the corresponding inputs m of the shunt signal generators $, C, to the other inputs of which are connected the outputs Qi, Cte, using the three-channel shift register of the output frequency signals and the outputs FI, FI, RST flip-flops. Each of m counter-current signal conditioners, $, is designed to provide internal communications between these elements and the formation of these signals in accordance with a logical expression

VI Q2 FI Si + Q3 FI Si + Qi Si,

where i 1,2 ... m.

The aim of the invention is to improve the quality of the output voltage and expand the scope of use by ensuring matching of the input and output voltage levels, as well as providing pulse-width output voltage control.

In Fig. 1 - a schematic diagram of the power section of the converter (example of implementation with m 3); Fig. 2 is a timing diagram of the signals Qi, $ 1, $ g, ij / b and the ° ° P of the output voltage of the converter for various values of the control angle: a 0 (a) and a 0 (a, b); Fig. 3 is a schematic diagram of a device for controlling a converter; Fig. 4 is a timing diagram explaining the principle of generating control signals of key elements of the converter;

The Converter, a schematic diagram of the power part of which is presented in figure 1. contains m + 1 half-bridge of power transistor switches 1-8 (in Fig. 1 m 3), shunted by reverse current diodes 9-16. To the connection points of m half-bridges of transistor switches 3-8, m primary windings 17-19 m of double-winding transformers 20-22 are connected. The free ends of the primary windings 17-19 of all transformers are combined and connected to the junction point of additional transistor switches 1-2. Secondary windings

20-25 are connected in series, according to and form the output ends of the converter with free ends.

A schematic diagram of a converter control unit is shown in FIG. It contains a frequency adjuster 26. connected to the input of the multiphase modulator 27 of the pulse width. Embodiments of the multiphase modulator 27 of the pulse width may be different, but in all cases it must provide the formation of m pairs of counter-current control signals $ and $, sequentially shifted between each other by an angle of 2 l 1 t (where m 2) at the carrier or a multiple of it modulation.

The variant of the multiphase pulse width modulator 27 shown in Fig. 3, when generating the control signals $ and $ with keys 3-8 of the converter, implements the principle of quasi-bandpass modulation. It consists of two frequency dividers 28.29, the inputs of which are combined and form the input of the multiphase pulse width modulator 27. The outputs of the frequency dividers 28, 29 are connected at the inputs of two shift registers 30.31 by an angle of 2 p 1t (for the case m - 3 this angle is 2/3, while the shift registers 30.31 can be performed in a ring circuit on three JK triggers 32-34). The outputs qi, cJ2, qa and qi, qa of the shift registers 30, 31 are connected to the inputs of m formers 35-37 modulated by the duration of the pulse signals shifted to each other by an angle of 2 / t at the carrier frequency. Each of them is made in the form of a pair of identical formers 38, 39 (40-43) of narrow pulses, outputs connected to the inputs of element 2 OR 44 (45, 46). The output of the latter is connected to the clock input of the RST trigger 47 (48, 49). Formers 38-43 narrow pulses can be performed, for example, in the form of series-connected elements NOT 50 and 2 AND 51. The output of the element NOT 50 through the capacitor 52 is also connected to the common point of the converter, and the second input of the element 2 AND 51 is connected to the input of the element NOT fifty.

To ensure that the operation of individual nodes of the multiphase modulator 27 of the pulse width is in phase, it is equipped with a synchronization unit 53. It includes elements 2 AND 54-56, inputs connected to the inputs of elements 2 OR 44-46, and outputs to the inputs of the element OR 57. The same installation R and S inputs of RST triggers 47-49 are combined and connected

to the common point of the converter and to the output of the synchronization node 53, formed by the output of the element m OR 57. The output of the synchronization node 53 is also connected to the input

three-channel register 58 of the shift of the signals of the output frequency, performed on three JK flip-flops 59-61, switched on according to the crossover circuit, similarly to the shift registers 30, 31. The outputs of one of the latter (usually lower frequency - in Fig.3 this is a register shear 31) is also connected to the inputs of m chains of serially connected sawtooth voltage generator 62-64 and comparator 65-67, the second inputs of which are combined and connected to the control signal source U and Comparators 65-67 are made with paraffin outputs Si,

Si, which, together with the paraphase outputs Fi, FI of the shapers of 35-37 modulated signals shifted between each other by an angle In 1t at the carrier frequency and the outputs Qi, Q2, Qa of the three-channel register 58 for shifting the output frequency signals, are connected to the corresponding inputs m of the waveforms 68 -70 counter-feedback signals $, $ The connections between the inputs of the mentioned shapers 68-70 and their outputs provide

generating signals $, $ in accordance with a logical expression

V, CteFiSi + QaRSi 4- QiSi,

where 1,2, ... t.

Two elements 3 AND 71, 72 (73-76) can be used to implement this logical expression. one element 2 AND 77 (78, 79) and one element 3 OR 80 (81, 82). and to receive the signal $, the element is NOT 83 (84, 85). Outputs, rfc. V elements 3 OR 80-82, $ 1. # 2 V elements NOT 83-85, as well as outputs Qi, Qi of flip-flop 59 are outputs of the converter control unit, which are connected (through the amplification and galvanic isolation unit of control signals, not shown in Figs. 1, 3) with the corresponding control entrances

power transistor switches 1-8.

The principle of operation of the converter is further illustrated by the timing diagrams shown in Fig. 2. The half-bridge transistors 1.2 of the converter are switched according to the simplest 180-degree algorithm at the output frequency (see USQ (Qi) in Fig. 2). The remaining transistors 3-8 are switched in counter-clock, with a duty cycle modulated by

output frequency according to a certain law (sinusoidal, trapezoidal, etc.). In this case, the pulse control signals Vi V Vm must be formed by coinciding in phase at the output frequency and shifted by an angle of 2jr / m at the modulation carrier frequency (see Usa-Ues - $ 3), 2a). As a result, the voltages on the primary windings 17-19 of the transformers 20-22 will be in the form of a signal with unipolar PWM according to the selected law. The main harmonics of these voltages coincide in phase, and some of the higher harmonics are in antiphase and cancel each other out when the secondary windings 23-25 are serially connected. To provide pulse-width control (WID) of the output voltage, the $ -V signals are additionally modulated linearly, and the introduction of control pauses and pulses is carried out at the modulation carrier frequency with an angle shift of 2 / t at the carrier or a multiple of it ( see the shaded zones in the Uea-Ues signals (- Vu in Fig. 2a). Depending on the modulation depth (relative amount of the control pause a), the shape of the output voltage changes. So at ok / sh, the output voltage has m steps ( see fig 2a) with l / t, and 2 / pl- {t-1) tupen (see. 2b) it.d. For (m --l) jc / m, the output voltage takes on a single-stage shape with zero pause.

On the example of the device for controlling the converter shown in fig.Z. I will take a look at using the principle of quasi-single-band modulation to generate control signals $ and $ with PWM according to the trapezoidal law and multiphase (or multi-band) WID. The high-frequency pulse signal from the output of the frequency adjuster 26 is fed to the inputs of two frequency dividers 28, 29, the division coefficients N28, N29 of which are chosen so that their ratio is represented by the ratio of two adjacent members of the natural series of numbers N28 / N29 - а / а ± 1 , where a is any integer (for example, in Fig. 4, a 3). Shift registers 30.31. to the clock inputs of which different frequency sequences of pulses IJ28, U29 are received, they are separated by no m channels, and each sequence of received pulses qi, f. q and qi, 0.2, qa are shifted relative to others by an angle of 2 p / t (see

5

Usi - {qi,, q} in Fig. 4) at its frequency. After the selection of pulses from U43 synchronous, for example, with a leading edge of the mentioned sequences

Uzo, U31 they are folded in pairs using 2 OR 44-46 elements and fed to the clock inputs of the RST flip-flops 47-49, which change their state with the arrival of each next pulse (see LM (Fi) U49 (Pz) in FIG. .4). To give certainty to the state of the triggers 47-49, which are used, for example, as RST triggers, one of the setup inputs (in FIG. 3 S-input) is connected to the output of the synchronization node 53. The latter performs pairwise comparison of sequences of narrow-frequency narrow pulses U38-U43 and the selection of the sequence Us arising from the coincidence of pulses in only one of the m formers 35-37. The pulse train frequency Us is six times the inverter output frequency. As a result, each of the aforementioned RST flip-flops 47-49 will be set to a certain state six times during the period, which further increases the reliability of the device. The same

0 pulse train Us, fed to the input of a three-channel register. provides back-contact switching of three J-K flip-flops 59-61 with an output conversion frequency. Phase shift

5 between leraphase pulses Qi, Qi

Oz, Oz is 60 electric degrees (see Usg (Cb) -ib1 / (Oz) in Fig. 4). As already mentioned, additional keys 1-2 are switched in antiphase, with a frequency equal to the output

0 frequency converter. To this end, signals Qi, 61 are supplied to the control inputs of the keys 1,2 (after appropriate amplification and necessary galvanic isolation). The Uzo signals (or U31, depending on what frequency the WID of the output voltage is implemented at) are also fed to the inputs of the sawtooth voltage generators 62-64, which provide

sequences of sawtooth signals having the same amplitude and shifted to each other by an angle of 2 g / t at the carrier frequency of the modulation. These signals

g are supplied to one of the inputs of the corresponding comparator 65-67, the second inputs of which supply a control signal (Ja, which provides a change in the relative duration of Si-ЗЗ signals and Si-ЗЗ signals inverse from 0 to 1.

Signal conditioning Vi V 2 V. V key management 3-8 is performed using shapers 68-70. Options for their execution can be different, however, the connections between their inputs and outputs must be such as to obtain sequences of control signals defined by expressions

  QeFiSi + Q3FiSi + QiSi; at the output of element 3 OR 80:

i Q2FiSi + QaFiSi + QiSi (see UBO on

figure 4)

at the output of the element NOT 83: signal $ i; at the output of element 3 OR 81:

V & Q2F2S2 4-Q3F2S2 + QlS2

at the output of the element NOT 84: signal tyz; at the output of element 3 OR 82:

V $ 02Рз5з + 6зРз5з + С11§з

at the output of the element NOT 85: signal t /

Some of the intermediate sequences of pulses obtained during the formation of the ipi (Ueo) signal are shown in Fig. 4 (see, U72, Uv).

The developed converter with a control circuit allows the implementation of the so-called multiphase pulse width modulation and multiphase pulse width control of the output voltage. A specially made version of the control unit and the power part of the converter (serial connection of the secondary windings 23-25 of transformers 20-22) provide mutual compensation (elimination) of certain arrays of higher harmonics

Thus, the converter provides a constant voltage conversion water-phase quasi-sinusoidal voltage having an improved spectral composition,

With an increased value of the frequency of the output voltage, the converter becomes especially efficient due to a significant decrease in the mass-size indicators, due to a decrease in the corresponding indicators of its output filter.

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Claims (1)

The claims 1 A single-phase converter with a multiphase PWM, containing m main pairs connected in series between the power lines of the key elements connected by reverse diodes, and an electromagnetic unit, including m primary windings located on the magnetic cores connected to a t-phase star and connected at their ends to the connection points the aforementioned main pairs of key elements, a control unit including an output frequency adjuster of the converter and sequentially connected to each other by a carrier cracking unit e frequency and a multiphase pulse width modulator, connected by a pair of aphase outputs p, to the corresponding inputs of the aforementioned key element, and the signals $ - are sequentially shifted between each other on a chip or a multiple of the PWM frequency by an angle of 2 i / m, where t 2, different gay men, with the goal of improving the quality of the holmap. April of the converter in terms of-, h, its distortions and the expansion of f, -1 and ionic capabilities due to it iHiiH coi / .taking the input and b voltage levels, it is equipped with an additional pair sequentially in ohm the power supply buses are R ... icMe - iot.s 3c1Sh of the reverse mounted d1 g volume, the connection point of which is nj; u lk.a. and to the forest point of the aforementioned gate: torn windings, the aforementioned Mig pipelines made magnetically independent 4i and equipped with secondary windings, which are interconnected in series with i free ends under Chance lyu- to output terminals of the converter output frequency .g.dztchik uprsp / saw cut block configured paraphase The yields Ar, n1 -. G1 associated with the management of the I / O see the corresponding key electronic pair / Fri browser according to claim 1 is distinguished /. so that in order to expand the functional potential due to the pulse-width regulation of the output voltage, the multiphase impulse width modulator is made containing m generating pi / 1 & ohms output voltage and paratsoy dza frequency divider, two (g shift by .head 2tg / t t formed aaiejias-- - edulronnyh in duration .snyl signals, sequentially s.dinute to each other at an angle of 2l / t on a carrier or a multiple of it, a synchronization unit containing m elements 2 I and element m IL AND, a three-phase register for shifting the signal of the output frequency and m shapers of counter-current signals $, $ whose output outputs are used as the outputs of a multiphase pulse width modulator, to the input of which the inputs of frequency dividers are connected, the outputs are connected to the inputs of the two mentioned shift registers by an angle of 2 / t, the corresponding outputs of the first of which are connected to the inputs of m sawmill generators voltage and m formers of pulse-width modulated pulse signals, sequentially shifted to each other by an angle of 2 l / m at a carrier or a multiple of it, the remaining inputs connected to the corresponding outputs of the second shift register by an angle of 2 l / t, and made in the form of two narrow pulse shapers, outputs connected to the inputs of element 2 OR, the output of which is connected to the clock input of the RST flip-flops with peer-phase outputs FI, FI, one of the installation inputs of each of which is connected to connection, for which I use the output of the above element m OR, the inputs of which are connected to the outputs of m elements 2 AND, with their inputs forming the inputs of the synchronization node, connected respectively to the input of one of the m mentioned elements 2 OR, the output of the synchronization node is also connected to the input of a three-channel shift register of the output frequency signals, the first channel of which is used as the mentioned output frequency driver of the converter, the outputs of each of the mentioned m sawtooth generators are connected to one of the inputs of m comparators with paraphase outputs Si, Si, the other inputs of which are combined and connected to the source of the control signal, and the outputs Si, Si, 82. 82 are connected to the corresponding inputs of m shapers of counter-current signals Щ, $, to the other inputs of which Q the outputs Qi, U2, Oz of the three-channel shift register of the output frequency signals and the outputs FI, FI of the RST flip-flops are connected, each of m counter-current signal conditioners tjt, ij; made providing internal connections between the specified element / and the formation of these signals and in accordance with the logical expression 0 5 5 thirty  / 1 -CfczFiSi + CtoFiSi + QiSi, where I 1,2 .... ft ABOUT P / 32F / 3 Figure 1 ig FIG 3 U3, Un I;  U33 U Uu Ux U 41 40 HZ 44 C U Us uM Unfi USB® Ueo & U & No. Ussfa) Ujt U72 u ,, them Щ (Yu