RU1807496C - Data exchange device - Google Patents

Abstract

The invention relates to computer technology and is intended for use in highly reliable multiprocessor systems. The purpose of the invention is to increase the reliability of control by controlling information features generated in subscriber processors. The device for exchanging data comprises first to sixth bus switches, an information register, a feature register, first to sixth triggers, first to fifth elements, an adder modulo 2, a comparison circuit, first to eighth AND elements, an OR element 29, a first NOT element. the second element is NOT, the seventh bus switch 32. 3 ill.

Description

The invention relates to computer technology and is intended for use in highly reliable multiprocessor computing systems. AX,

The aim of the invention is to expand the functionality of the device and increase the reliability of the control of information and features.

In FIG. 1a, 16 is a functional diagram of an apparatus for exchanging data; in FIG. 2 shows an example of building a multiprocessor system using the proposed device in it; in FIG. 3 is a timing diagram of the operation of the device. .

The device for exchanging data (Fig. 1) contains the first to seventh multiplexers 1, 4, 5, 32, 2, 3, 6 made on the IC 1533KP12 (see 6K0.347.364-04TU), the first register 7, the second register 8, the first Sixth triggers 11, 12, 9, 10. 13. 14, first fifth

adders 15-19 are modulo two, comparison unit 20, first to eighth elements 21, 23, 26, 25, 22, 24, 27, 28 AND, element 29 OR, first element 31 NOT. the second element 30 is NOT, and the first synchronization input 40 of the device is connected to the first inputs from the first to fourth elements 21, 23, 25, 26 And, the outputs of which are connected respectively to the synchronization inputs from the first to fourth triggers 11, 12, 10.9, the first the input 41 of the sign of control of the device is connected to the second inputs of the first and second elements 21, 23 And, the input 43 of the sign of activity of the device formed by the subscriber processor is connected to the first inputs of the fifth and sixth elements 22 and 24, the output 44 of the sign of the master / slave device is connected to a second input of the fifth and sixth elements 22 and 24 and to the input and the first member 31 is not. the output of which is connected to the first inputs of the seventh and eighth elements 27 and 2V AND, the outputs

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which are connected respectively to the synchronization inputs of the fifth 13th and sixth 14 triggers, the outputs of which are connected respectively to the first and second outputs 57 and 50 of the device failure indicator, the first device mode input 45 used to connect the subscriber processor is connected to the third inputs of the fifth and sixth elements 22 and 24 I, the second and third inputs 62 and 63. of the device modes used to connect the control processor are connected respectively to the fourth inputs of the fifth and sixth elements 22 and 24 I, information the inputs 64 of the first group of a-ro devices used to connect the (o-1) -th device, where a 1, .... and, n is the number of subscriber processors, are connected respectively to the inputs of the first adder 15 modulo two, to the information inputs of the first groups of the first, second, third, fourth multiplexers 1, 4, 5, 32, the information inputs 33 of the second group of the a-th device, used to connect (a-1) the device, are connected to the inputs of the second adder 16 modulo two, to the information inputs of the second groups of the first, second, third and fourth mule of multiplexers 1, 4, 5, 32, the information inputs 34 of the third group of the a-th device, used to connect the (a) -th device, are connected to the inputs of the third adder 17 modulo two, to the information inputs of the first group of the fifth multiplexer 2, to the information inputs of the third corpus of the third multiplexer 5, to the information inputs of the third group of the fourth multiplexer 32 and to the information inputs of the first group of the sixth multiplexer 3, information inputs 35 of the fourth group of the a-th device used for connection (a-AND ) th the devices are connected to the information inputs of the second groups of the fifth and sixth multiplexers 2 and 3, to the information inputs of the fourth groups of the third and fourth multiplexers 5 and 32 and to the inputs of the fourth adder 18 modulo two, information inputs 52 and J50 of the fifth and sixth device groups, used to connect the subscriber processor are connected respectively to the information inputs of the first and second registers 7 and 8. the outputs of which are connected respectively to the information inputs of the first and second groups of the seventh multipl litter 6, the outputs of which are connected to the inputs of the fifth adder 19 modulo two, the output of which is connected to the information inputs of three groups of the first, second, fifth and sixth multiplexers 1, 4, 2, 3 and to the inputs of the first group of the comparison unit 20, output which is connected to the information inputs of the fifth and sixth triggers 13 and 14, the device control enable input 61, used to connect the control processor, is connected to the second inputs of the seventh and eighth elements 27 and 28, and the device control indicator input 46 is connected to the second inputs am of the third and fourth elements 26 and 25 And, the second input 47 of the synchronization device is connected to the third input of the seventh and eighth element 27 and 28 And, inputs 59, 65, 5.1, 49 of the fourth to seventh mode. devices used to connect the control processor, respectively connected to the first control input of the third multiplexer 5, to the first control input of the fourth multiplexer 32, to the write / read input of the first register 7 and to the write / read input of the second register 8, the eighth device mode input 48, are used for connecting the control processor, it is connected to the control input of the seventh multiplexer 6. to the fourth input of the seventh AND element 27 and to the input of the second element 30 NOT. the output of which is connected to the third input of the eighth element 28 AND, the input 42 of the reset device is connected to the inputs of the zero setting of the second and third triggers 12 and 9 and to the inverse inputs of the zero setting of the first, fourth, fifth and sixth triggers 11,

10. 13, 14. the inverse output of the first trigger 11 is connected to the third input of the first element 21 AND and to the first control input of the first multiplexer 1, the output of which is connected to the first information output 36 of the device, the output of the first adder .15 modulo two is connected to the information the input of the first trigger

11. whose direct output is connected to the first output 54 of the device failure indicator and to the first input of the OR element 29, the output of which is connected to the second control inputs of the third and fourth multiplexers 5 and 32, the output of the fourth multiplexer 32 is connected to the second information output 56 of the device, the output of the second adder 16 modulo two is connected to the information input of the second trigger 12, the direct output of which is connected to the second output 53 of the sign of Device failure, the inverse output of the second trigger is connected to the third input the second element 23 And to the first control input of the second multiplexer 4. the output of which is connected to the third information output 38 of the device,

the direct output of the third trigger 9 is connected to the third output 55 of the device failure indicator and to the second input of the OR element 29, the inverse output of the third trigger 9 is connected to the third input of the third AND element 26 and to the first control input of the fifth multiplexer 2, the output of which connected to the fourth information output 37 of the device, the output of the third adder 17 modulo two is connected to the information input of the third trigger 9, the output of the fourth adder 18 modulo two is connected to the information input of the fourth trigger 10, direct the output of which is connected to the fourth output 60 of the device failure indicator, the inverse output of the fourth trigger 10 is connected to the third input of the fourth element 25 And to the first control input of the sixth multiplexer 3, the output of which is connected to the fifth information output 39 of the device , the output of the fifth element 22 AND is connected to the second control inputs of the first and second multiplexers 1 and 4, the output of the sixth element And is connected to the second control inputs of the fifth and sixth multiplexers 2 IZ.

The multiprocessor system includes k-66 data exchange devices (UOD), as well as non-k-processor element (PE) 67 devices and a control processor 68 (UP). Also marked: ША - address bus; SHI - information bus; SHU - control bus,

The device operates in the following modes;

; -the output of information to the right with the ability to receive information on the left or right;

- Issuing information to the left with the possibility of receiving information from the left or right;

 - issuing information left and right with the ability to receive information left or right ;.

-transmission of information to the left or (and) to the right with the ability to receive information from the left or right;

- issuing ALU signs to the left. Consider the operation of the device in the mode of issuing information to the right with the reception of information on the left.

UP software configures the processor elements (PE). Each PE and its corresponding UOD are programmatically given the following state:

- active (executes all commands) or inactive (input 43 of the device activity indicator);

- the master executes all the commands and provides information or signs through the RCD (input 44 of the characteristic Master / slave device;

- the slave executes all the commands, but does not give out information or signs through the DRM, but only compares it in the comparison circuit 20 with the received information from the master.

The remaining control signals of the UOD are obtained from the control device of the control processor. Thus, inactive, slave, or inactive for the issuance of UOD (low signal levels at the corresponding inputs of the fifth element 22 AND) will be in the mode of transmitting information to the left or (and) to the right. On the other hand, at the third input of the seventh element 27 And and at the second input of the eighth element 28 And, a high level of signal is present, allowing the information to be monitored by the slave UOD.

Consider the operation of a device that is associated with a host PE. The information input of the fifth group of the device receives information that is recorded on the leading edge of the clock pulses (fed to the third input 51 of the device mode) in the first register 7. At the eighth input 48 of the device mode, there is a high signal level connecting the contents of the first register to the output of the seventh multiplexer 6 7. Then, the oddity padding bit is formed into this information (inframation is minimized on module 5, adder 19, modulo two. A high level is applied to the second input 62 of the device mode, which the fifth through the fifth element 22 And connects the information from the output of the seventh multiplexer 6 and the odd-out bit to the output of the second multiplexer 4 and the output of the first multiplexer 1. In this mode, the signal level is also fed to the third input 63 of the device mode, which is transmitted through the sixth element 24 And also connects this information to the output of the fifth and sixth multiplexers 2 and 3. The information enters the left ECD, which is a slave and in which it will be compared with its information. Thus, the information is issued to the right for further distribution along the ring and for reception in one or more right PEs, tuned to the reception and to the left to compare it with the information in the slave DRM. The information, which is similarly issued from the left master ECD, is fed to the information inputs of the first groups of the third and fourth multiplexers 5 and

32 and the first adder 15 modulo two. In addition, similar information is fed through the backup channel to the information inputs of the second groups of the third and fourth multiplexers 5 and 32. Information is received at the second information output 56 of the device, which is received further by the receiver tuned to reception.

The fourth input 59 of the device mode receives a high signal level, which connects the right group of the main information inputs 64 of the first group of the device to the input of the comparison unit 20. However, in. the leading UOD fixation of the comparison result about the fifth trigger 13 does not fail, since the third input of the seventh element 27 And is low.

At the output of the first or second adder 15 or 16 modulo two, the result is the convolution of all information bits, as well as the complement bit to odd, That is, if the result is even, that the left channel (main or backup) is working (in Fig. 3 shows this case). If the result is odd, the first flip-flop 11 is cocked, which switches with the direct shoulder through the element 29 OR the third and fourth multiplexers 5 and 32 to receive information received at the information inputs 33 of the second group of devices. With an inverse shoulder, the first trigger 11 blocks subsequent control,

Consider the operation of a slave DRM, which is on the left. For the issuance of information, the slave UOD is closed, since the second input of the fifth element 22 is a low signal level. This UOD is in the mode of broadcasting information to the right through the first and second multiplexers 1 and 4 to the leading UOD. In addition, the slave UOF similarly monitors the received information at the first and second triggers 11 and 12 and writes to the fifth trigger 13 the result of comparing its information with the data coming to the right of the leading UO (at the fourth input of control 59 of the device mode, as well as the leading UO, a high level ) Configured to receive slave PE receives information from the output of the fourth multiplexer 32.

Consider the mode of issuing signs of ALU PE operation with control. When information is not exchanged through the DRM, its resources are used to monitor the signs of ALU operation (result sign, result zero, bit overflow, transfers). In this mode, the master DRM has output to the seventh multiplexer 6 and then to the output of the fifth and sixth multiplexers 2 and 3 connect the contents of the second register 8.

The slave UOD receives these features from the information inputs 34 of the third device group through the third multiplexer 5 to the comparison node. The result of the comparison is recorded in the sixth trigger 14 ..

The left and right translation modes are shown in FIG. 3 with appropriate control at the inputs of the device.

SUMMARY OF THE INVENTION A device for exchanging data, comprising first to seventh multiplexers, first and second registers, first and

5 second triggers, from the first to the eighth AND elements, the first adder modulo two, the comparison node and the OR element, characterized in that, in order to increase the reliability of the control due to the control of information signs generated in the subscriber processors, it contains third through sixth triggers, second through fifth adders modulo two, the first and second elements are NOT, and the first input

5, the synchronization device is connected to the first inputs from the first to fourth elements, And, the outputs of which are connected respectively to the synchronization inputs from the first to fourth triggers, the first

0 the input of the sign of control of the device is connected to the second inputs of the first and second elements AND, the input of the sign of activity of the device formed by the subscriber processor is connected to the first inputs

5 of the fifth and sixth AND elements, the output of the master / slave attribute is connected to the second input of the fifth and sixth AND elements and the input of the first element NOT, the output of which is connected to the first inputs

0 of the seventh and eighth AND elements, the outputs of which are connected respectively to the synchronization inputs of the fifth and sixth triggers, the outputs of which are connected respectively to the first and second outputs of the device failure indicator. The first device mode input used to connect the subscriber processor is connected to the third the inputs of the first and sixth elements And, the second and third inputs

0 device modes used to connect the control processor are connected respectively to the fourth inputs of the fifth and sixth elements AND, information inputs of the first group of the a-th

5 devices used to connect the (a-1) -th device, where a 1, ..., n, n is the number of subscriber processors, respectively connected to the inputs of the first adder modulo two, to the information inputs of the first groups of the first, second, third

the fourth multiplexer, the information inputs of the second group of the a-th device used to connect the (a-1) -th device are connected to the inputs of the second adder modulo two, to the information inputs of the second groups of the first, second, third and fourth multiplexers, information inputs of the third groups of the a-th device used to connect the (a + 1) -th device are connected to the inputs of the third adder modulo two, to the information inputs of the first group of the fifth multiplexer, the information inputs of the third group of the third multiplexer, information inputs of the third group of the fourth multiplexer and information inputs of the first group of the sixth multiplexer, information in the odes of the fourth group of the ith device, used to connect the (a + 1) th device, are connected to the information inputs of the second groups of the fifth and sixth multiplexers, the information inputs of the fourth groups of the third and fourth multiplexers and the inputs of the fourth adder modulo two, the information inputs of the fifth and sixth groups of the device used to connect a Bonent processor, respectively connected to the information inputs of the first and second registers, the outputs of which are connected respectively to the information inputs of the first and second groups of the seventh multiplexer, the outputs of which are connected to the inputs of the fifth adder modulo two, the output of which is connected to the information inputs of three groups of the first, second , the fifth and sixth multiplexers, and the inputs of the first group of the comparison node, the output of which is connected to the information inputs of the fifth and sixth triggers, the control enable input the device used to connect the. control processor is connected to the second inputs of the seventh and eighth elements And, the input of the sign of the control device is connected to the second inputs of the third and fourth elements And, the second synchronization input of the device is connected to the third input of the seventh element And, the inputs the fourth to seventh modes used to connect the control processor are connected respectively to the first control input of the third multiplexer, the first control input of the fourth mul ipleksora to the read-write input of the first register and the read-write input of the second register, the eighth input device mode used for the connection

the control processor, connected to the control input of the seventh multiplexer, the fourth input of the seventh AND element and the input of the second element NOT, the output of which 5 is connected to the third input of the eighth AND element, the reset input of the device is connected to the installation inputs to O of the second and third triggers and inverse inputs installation in About the first, fourth, fifth and sixth

0 triggers, inverse, the output of the first trigger is connected to the third input of the first AND element and the first control input of the first multiplexer, the output of which is connected to the first information

5 to the device output, the output of the first adder modulo two is connected to the information input of the first trigger, the direct output of which is connected to the first output of the device failure indicator and the first

0 to the input of the OR element, the output of which is connected to the second control inputs of the third and fourth multiplexers, the output of the fourth multiplexer is connected to the second information output of the device. the output of the second adder modulo two is connected to the information input of the second trigger, the direct output of which is connected to the second output of the device failure indicator, the inverse output of the second trigger is connected to the third input of the second element And and the first control input of the second multiplexer, the output of which. connected to the third information output of the device, direct output

5 of the third trigger is connected to the fth output of the device failure indicator and the second input of the OR element, the inverse output of the third trigger is connected to the third input of the third AND element and the first control input of the fifth multiplexer, the output of which is connected to the fourth information output of the device, the output of the third adder modulo two is connected to the information input of the third

5 triggers, the output of the fourth adder modulo two is connected to the information input of the fourth trigger, the direct output of which is connected to the fourth output of the device failure indicator, the inverse output of the fourth trigger is connected to the third input of the fourth element And and the first control input of the sixth multiplexer, the output of which connected to the fifth information output of the device, the output of the fifth AND element is connected to the second control inputs of the first and second multiplexers, the output of the sixth AND element is connected to the second m the control inputs of said fifth and sixth multiplexers.

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