RU1803972C - Insulated-gate field-effect inverter - Google Patents

Abstract

Usage: the invention relates to pulse technology and may find application in digital integrated circuits. SUMMARY OF THE INVENTION An MOS inverter comprising four MOS transistors with an induced channel 1,2,3 and 4, a diode 5 and a capacitor 6. 1 ill.

Description

4 s

 tn

00

oo oo

N

Yu

The invention relates to pulse technology and may find application in digital integrated circuits.

The aim of the invention is to increase the noise immunity of the MOS inverter by increasing the threshold for opening it.

The drawing shows a schematic diagram of an MOS inverter, consisting of four MOS transistors with an induced p-channel 1, 2, 3 and 4, diode 5, capacitor 6, additional diode 7 and resistor 8. The sources of the MOS transistors 1 and 3 are connected to the common bus. The drains and gates of the MOS transistors 2 and 4 are connected to the power supply terminal. The input terminal is connected to the first output of the resistor 8 and the gate of the MOS transistor 1, the drain of which is connected to the source of the MOS transistor 2, the gate of the MOS transistor 3, the cathode of the diode 5, and the output terminal. The second output of the resistor 8 is connected to the anode of the diode 7, the cathode of which is connected to the anode of the diode 5 and the first lining of the capacitor b, the second lining of which is connected to the drain of the MOS transistor 3 and the source of the MOS transistor 4. Substrates of the MOS transistors 1, 2, 3 and 4, depending on the specific technical requirements and manufacturing technology used, can be connected to their sources or connected to a common bus. MOS transistors 1 and 3 are controlled and fulfill their usual functions as active elements, and MIS transistors 2 and 4 are load-carrying and act as resistors. Diodes 5 and 7 provide the connection of the necessary circuits for recharging the capacitor 6. The resistor 8 determines the discharge time of the capacitor 6 and the input resistance of the device.

The inventive device operates as follows.

When a logic unit UBX signal is received at the input terminal, the MOS transistor 1 opens, and the MIS transistor 3 closes. At the output terminal of the device there is a logic signal of zero ° 0. In this case, the capacitor 6 will be charged from the power source (via MOS transistors 1 and 4 and diode 5) to a voltage close to En DM (where Uo4 is the MIS threshold voltage transistor 4).

Then, upon entering the UBX ° input terminal, the MOS transistor 1 closes and the MIS transistor 3 opens. On the output terminal there is a signal of a logical unit Uvykh1 “ErrUcG (where Uo2 is the threshold voltage of the MOS transistor 2). Wherein

the voltage across the capacitor 6 appears to be an applied minus sign to the gate of the MIS transistor 1 (via diode 7 and resistor 8). ensuring its reliable locking.

So, due to the influence of the negative voltage of the charged capacitor 6 on the gate of the MOS transistor 1, the opening threshold of the MOS transistor 1 increases to approximately the level of Uoi-KEn-Uo4) (where Uoi is the threshold voltage of the MOS transistor 1), which ensures increased noise immunity of the MIS inverter.

The experimental check of the MIS inverter was carried out on discrete

MOS transistors KP305, KP350, KP902 and laboratory samples. Unlike analogs and prototypes of the claimed device, it was possible to increase the threshold for opening it. So, at B the threshold for opening the prototype is Uoi -1.5 V, and in the claimed device it reached about 9 V.

The economic effect in the inventive device is not created due to the use of additional elements. With the practical use of the MIS inverter, the economic effect can be achieved by increasing the noise immunity. It can be evaluated after the manufacture of a prototype integrated sample and use in specific equipment.

Claims (1)

SUMMARY OF THE INVENTION A MOS inverter containing four MOS transistors with an induced channel, a diode and a capacitor, the first lining of which is connected to the anode of the diode, and the second to the drain of the third MOS transistor and the source of the fourth MOS transistor, the drain of which is connected to the power supply terminal and the drain of the second MOS transistor, the gate of which is connected to the gate of the fourth MIS transistor, and the source is connected to the output terminal and the drain of the first MOS transistor, the source of which is connected to the common bus and the source of the third MOS transistor, and the shutter The first MOS transistor is connected to an input terminal, characterized in that, in order to increase the noise immunity, additional diode and resistor, the first output of which is connected to the input terminal, and the second output to the anode of the additional diode, the cathode of which is connected to the anode of the main diode, the cathode of which is connected to the output terminal and the gate of the third MOS transistor, and the gates of the second and fourth MOS transistors are connected to the terminal of the power source.