RU1802395C - Pulse repeating frequency multiplier - Google Patents

Abstract

The pulse repetition rate multiplier comprises a reset integrator, a sampling and storing unit, a controlled generator, an output bus, a voltage reference, a pulse shaper, a delay element, a key, a trigger, and an input bus. 2 ill.

Description

I The invention relates to pulsed engineering and can be used in automation and measurement technology.

 The purpose of the invention is to expand the range of input frequencies.

| On Fig, 1 shows a structural electrical circuit diagram of the device; in FIG. 2 - time diagrams explaining the operation of the device.

j The device comprises an integrator 1 with Reset, a sampling and storage unit 2, a controlled generator 3, an output bus 4, a reference voltage source 5, a pulse shaper 6, a delay element 7, a key 8, a trigger 9, and an input bus 10.

 The reference voltage source 5, the switch 8J, the reset integrator 1, the data access module 2 and the controlled generator 3. are connected in series. The output of the controlled generator 3 is connected to the output Zina 4.

j The counting input of the trigger 9 is connected to the input bus 10, and its output is connected to the control inputs of the key 8 and the pulse shaper 6, the output of which is connected to the input of the delay element 7. and

the control input of the sample-storage unit 2, the output of the delay element 7 is connected to the control input of the integrator 1 with a reset:

The device operates as follows.,

Input pulses with a trace period, neither T.1 arrive at the counting input of trigger 9 (Fig. 2, a). The trigger 9 is flipped with each input pulse, and at its output a sequence of im- is formed; pulses with a repetition period of 2Ti and a duty cycle of 2 (Fig. 2.6). During the action of pulses at the output of the trigger 9, the key 8, controlled by the signal from the output of the trigger 9, is open, and the constant voltage is supplied to the input of the integrator 1, its output voltage increases linearly (Fig. 3, e) with a speed determined by the time constant of the synthesizer equal to.;

In the pauses between pulses at the output of the trigger 9, the key 8 opens, the constant voltage Uon ceases to be supplied to the input of the integrator 1, and the signal at its output ceases to increase (Fig. 3e). On the trailing edge of each output pulse

ate

with

with about

K5 S

Yu

fcn

trigger 9, shaper 6 generates short sampling pulses, which are directly transmitted to the control input of block 2 (Fig. 3, c) and through element 7 with a small delay in time, to the control input of integrator 1 (Fig. 3, d) . During the action of the sampling pulses, block 2 stores the signal from the integrator 1. At the end of the sampling pulse, block 2 stores the stored signal for a period of 2Ti until the next sampling pulse arrives (Fig. 3e).

With the appearance of the next pulse at the output of trigger 1, the process repeats.

The voltage stored by block 2 is proportional to the period Ti of the pulse repetition of the input pulses

U Uon.

0)

Under the action of voltage U from the output of block 2, the generator 3 generates pulses, the follow-up period Tz of which is directly proportional to this voltage

T2 KU, (2) where K is the coefficient of proportionality.

Solving equations (1) and (2) together, we obtain

Ti g

T2 K Uon

(3)

0

5

0

5

0

or

f2 g

fl k uon

where fi and fa are the pulse frequencies at input 10 and output 4 of the frequency multiplier, respectively.

Claims (1)

Formula of the invention A pulse repetition rate multiplier comprising a series-connected integrator with a reset sample-storage unit and a controlled generator, a reference voltage source, series-connected pulse shaper and a delay element, the input and output of which are connected respectively to the control inputs of the sample-storage unit and integrator with reset, the output of the controlled generator is connected to the output bus, characterized in that, in order to expand the range of input frequencies, h and trigger a counting input coupled to an input bus and an output - to the input of the pulse shaper and the control input of a key, a first terminal coupled to an output source of the reference voltage and the second output - to the input of an integrator with reset.