RU1800658C - Control and delta modulation interaction signals adaptive digital group detector - Google Patents

Abstract

Usage: in adaptive group receivers of control signals and interaction with delta modulation. The inventive device includes a matching unit 1, the first and second blocks 2.3 of random access memory, address switcher 4, block 5 generators, the first, second, third registers 6,7,8 shifts, block 9 read-only memory delta stream , read-only memory block 10, multiplier 11 by sine, multiplier 12 by cosine, register 13 of the sine component, register 14 by the cone component, counter 15 by the sine component, counter 16 by the sine component, calculation unit 17, the decision block 18, adaptive code register 19, feedback register 20, comparator 21 threshold codes, output register 22, logic block 23, OR element 24. 1-2-3-6-9-11-13-15-17-18-19-21-22-22-24, 1-4-3, 1-5-18, 7-8-9-12-14-16-17-18- 20-23, 1 ill.-

Description

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The invention relates to telecommunication technology and is intended, in particular, for receiving control and interaction signals transmitted as part of a group 8-channel digital stream 256 kbit / s with adaptive delta modulation. These signals are used to control the switching equipment of adaptive delta modulation digital electronic exchanges.

The aim of the invention is to increase the noise immunity of an adaptive digital group receiver of control signals and interaction with delta modulation, expanding the dynamic range of reception levels and simplifying the circuit.

The drawing shows a functional diagram of the proposed receiver,

. The adaptive digital group receiver contains a matching block 1, the first block 2 - random access memory, the second block 3 random access memory, switch A addresses, block 5 generators, the first 6, second 7 and third 8 shift registers, block 9 read-only memory delta -current, read-only memory block 10, multiplier 11 by sine, multiplier 12 by cosine, register 13 of sine component, register 14 by sine component, counter 15 by sine component, counter 16 by sine component, calculation unit 17, calculation unit, decision block 18, register 19 adaptive code, register 2 0 feedback, comparator 21. threshold code, output register 22. Logic block 23 m element OR 24.

An adaptive digital group receiver of control and interaction signals with delta modulation operates as follows.

A group digital stream of 256 kBit / s is supplied to the data inputs of matching block 1 by four-bit code combinations in parallel binary

4 . code for a time t of 15.6 μs,

g

Each code combination displays four consecutive delta samples on the next channel, from the 1st to the 8th.

In addition to Di-D4 information, the remaining nine by the input of matching block 1 receive a frequency grid (meanders) 2048; 1,024; 512; 256; 128; 64; 32; 16 and 8 kHz for clock and loop synchronization of the receiver along the trailing edges of the pulses.

The matching unit 1 includes, in particular, four buffer elements with a third output state, for servicing the Di-D / j data bus, providing

parallel operation of the first 2 and second 3 blocks of random access memory when recording and reading information on the same input and output data buses. 5 From the first four outputs of matching block 1, Di-D information is sequentially written (read) to the first 2 and second 3 blocks of RAM. From the remaining outputs of the matching unit 1, a network of 10 ka frequencies of 2048-8 kHz is supplied to block 5 of the generators, in which meanders with frequencies of 4 are formed by sequentially dividing the frequency RC 8 kHz; 2; 1; 0.5; 0.25; 0.125; 0.0625 and 0.013125 kHz. The lower frequency - 15 Hz RC 31.25 Hz determines the complete processing cycle (write / read) of the signal

Nala T o --TLE- 16 ms in the first 2 and second Ј g n

Rum 3 blocks of random access memory (RAM).

20 Grids of input and generated frequencies through a 4-address switch go to the address inputs of the first 2 and second 3 blocks of RAM. The 4 address switch provides the desired sequence of changing the addresses of both RAM in the write and read modes.

In the real-time recording and reading mode, information about the next four delta samples (D1-D4 via the next channel is entered) into the corresponding addresses, for example, of the first block 2 of the operative memory

j, - - 125 μs, recording cycle according to G

The 35th channel is repeated at the subsequent addresses of the first 2 blocks of RAM. In total, during the processing of the length of the ms signal, 128 quadruples of information are recorded on each channel, or 512

40 delta readings. In general, binary information units are entered into the RAM block 2 through 8 channels.

At the same time, reading from the second block 3 of RAM takes place earlier

45 recorded there the signal segment T0 16 ms. Reading is performed accelerated, with a clock frequency of fT 64 Rts 512 kHz in order to carry out sequential processing of the signal at 8 frequencies, each of 8

50 channels.

The sequence of address changes when reading information from the second RAM block 3 differs from that described above when writing to the first RAM block 2. When reading, the addresses of all previously recorded 128 quadruples of information on the first channel are changed first, which takes a length of time

  μs, during this time

1st

processing of the first of 8 possible frequency components of the signal of the 1st channel proceeds. Then, during the time L T, 128 quadruples of delta samples on the 1st channel are read again and a decision is made on the presence (absence) of the second frequency component of the signal. In general, on the 1st channel, 8 times in a row, the same information is read from the second 3 blocks of RAM, which takes the time period AT about 8 A T 2ms, by the end of which a decision is made about the existence of that or a different frequency component of the signal (or two) out of eight possible.

Then, the 2nd, 3rd, etc. are similarly processed. channels up to the 8th, which takes the total analysis time T0 of 16 ms. During this time, the recording of the new 16 ms information interval in the first block 2 of the RAM ends and the write / read cycle is completed. After that, the blocks 2 and 3 of the RAM are interchanged, i.e. from block 2, reading of the leading information begins, and into block 3, writing of the next segment T0 1 bms of current information.

The switch 4 addresses on its control input provides alternating non-overlapping in time sampling of blocks 2 and 3 of random access memory, from the combined outputs of which the information is read out sequentially into the first 6, 7, and 8 third shift registers promoted with a frequency of fT 512 kHz . With their help, a signal segment with a duration of 12 delta samples 7 is formed, containing three quadruples of information sequential in time. In the middle of this segment is placed the next four delta samples to be processed at the moment, along the edges - the previous and the next (current) four. From the outputs of the shift registers 6, 7 and 8, information is fed to the address inputs of the delta-stream read-only memory unit 9, with the help of which the initial delta-stream is corrected at the receiver input.

Due to the sharp asymmetry (by an order of magnitude or more) of the short adaptation time of the quantization step of a real delta encoder with syllabic companding when the signal rises (1-2 ms) and the step decreases slowly when the level drops (16 ms), the established quantization step value is proportional to the peak (rather than effective) value of the steepness

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30 45 50

55 35

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us signal. This leads to worse tracking of the envelope of the two-frequency dialing signals, and as a result, to the suppression of the signal component with a lower slope at the output of the delta encoder in the presence of a signal component with a higher slope. A larger steady-state quantization step contributes to better voice quality by eliminating the overload of the delta encoder and associated non-linear speech distortion. At the same time, an oversized quantization step noticeably worsens the reception conditions of dual frequency dialing signals. In the delta stream, the bursts of delta samples of one sign are interrupted by single delta symbols of the opposite sign, even in the region of the greatest steepness of the signal when it passes through zero. In areas of lesser steepness, the silence mode prevails (type 101010), corresponding to zero correlation of the signal with the reference sine and cosine delta sequences of the processed frequencies recorded in the read-only memory block 10. As a result, in a digital filter (correlometer) built on blocks 10-17, approximately two times less code is accumulated (as computer simulation shows) during the analysis of this frequency compared to the possible code with an optimal, 2 times smaller quantization step. Accordingly, the signal-to-noise ratio is halved and the noise immunity of receiving two-frequency dialing numbers decreases sharply.

Correction of the delta stream entering the receiver of the multi-frequency code is necessary. The transformation of the flow should be aimed at restoring areas of great steepness when the signal passes through the zero level, i.e. lengthening packets of delta countdowns of one sign and eliminating interrupting packets of single characters of the opposite sign. Such a conversion, based on knowledge of the shape of the two-frequency signal, is equivalent to a relative decrease in the quantization step in the informative areas of a large signal steepness and maintaining a constant large step in uninformative areas of reduced steepness (flat tops, envelope minima) of the two-frequency signal. The ultimate goal of correcting a delta stream is to increase its cross-correlation with the reference sine and cosine functions. Qi recorded in ROM 10.

The correction of the shape of the delta stream is performed in the read-only memory unit 9.

a delta stream, to the address inputs of which a signal length of 12 delta characters is received. If the four delta samples currently being processed and located in the middle of a group of 12 symbols have two symbols of different signs in any combination, or all four symbols have the same signs, they are transmitted to the output of block 9 constant delta stream memory unchanged. If the processed four delta samples have three symbols of the same sign and one opposite, then it can be eliminated at the output of the block 9 of the constant memory of the delta stream by replacing it with the reverse one. Such a replacement is made provided that around this symbol in the original delta stream there are at least two (or three) symbols of the opposite sign. If this condition is not fulfilled, the processed four delta samples are transmitted without change to the output of block 9, from which the corrected delta stream is removed to the inputs of multiplier 11 by sine and multiplier 12 by cosine. After advancing at the fT 512 kHz clock frequency of the first 6, second 7 and third 8 shift registers, a new segment of the delta stream is set at the addresses of the read-only memory unit 9 with a shift of four samples.

In addition to increasing the correlation with the reference sine and cosine functions, an additional effect of the correction of the initial delta stream is a decrease in the frequency dependence of the reception thresholds. This conversion promotes the raising of low-frequency signals at the output. the digital correlometer almost does not affect high-frequency signals (Fc 1.7; 1.5; 1.3 kHz), for which the fics / Fc ratio is relatively small and the bursts of the same name in the areas of signal transition through zero are short. For low-frequency signals dialing with code 2 of 6 (Fc 0.7; 0.9; 1.1 kHz), as well as single-frequency AON type signals (Fc 0.5 kHz), Station response (Fc 0.425 kHz) Network monitoring (Fc 0 , 7 kHz) packets of delta symbols of the same sign after correction at the output of block 9 are long and the effect at the output of the digital correlometer increases noticeably (in th or more), the frequency dependence of thresholds weakening reception frequency due to rise of the lower layer increases the ratio of signal / noise ratio and increase the noise immunity of the reception signal lowpass signal at frequencies higher background.

From the output of the delta-stream memory block 9, the quadruple of information is multiplied over time t 2 μs

simultaneously to the four sines and four cosines of a given frequency recorded in the read-only memory block 10 at a given address, since the initial phase of the signal is unknown.

In the multiplier 11 is the sine and the multiplier. 12 to cosine on the elements EXCLUSIVE OR, there is a simultaneous multiplication of the signs of the delta samples with the signs of the fours of rectangular sines and

quadruples of rectangular cosines quantized with a frequency fkB 32 kHz.

The multiplication results are recorded in a parallel-serial register 13 of the sine component and register 14 of the cosine component. The registers convert parallel streams of quadruples of information with fT 512 kHz into consecutive one-bit delta streams of units and zeros fr 2048 kHz. The number of units in the sine and cosine sequences is counted respectively by the counter 15 of the sine component and by the counter 16 of the cosine component. Six high-order bits from the outputs of the counters 15 and 16 are supplied to the same address inputs of the computing unit 17 based on the ROM programmed to execute

operations of the form Z X2 + X 2, where X and Y are respectively binary codes of the sine and cosine components of the signal at the outputs of the counters 15 and 16, which are digital integrators as part of the sine and cosine sign correlometers.

The control (13th address) input of the ROM of the calculation unit 17 receives from the output of the generator unit 5 a sequence of the meander type f 4 kHz, which sets the AT processing intervals of this frequency - the first

half time AT / 2 125 μs and second half time AT / 2 125 μs. In this case, the weight of each bit of the code at the address inputs of the computing unit 17 in the second half of the time doubles

compared to the discharge weight in the first half of the processing time. This is necessary in order to reduce the bitness of the codes of the counters 15 and 16 in the second half of the processing time, since they are not reset at the end of the first half of the processing time.

The outputs of block 17 calculation

Represents code number 2

X2 + Y2 s

weights 8 (16), 16 (32), 32 (64), 64 (128) and 128 (256), respectively, in the first and second half of the processing time. The outputs of the computing unit 17, which are the code outputs of the digital correlometer, are fed to the first five address inputs of the ROM-based decision unit 18, which is used to form the initial and adaptive signal reception thresholds. Three subsequent inputs 1-2-4 of the decision block (18) are supplied with the aim of developing frequency-dependent reception thresholds of pulsed sequential frequency changes - meanders with periods of 0.5; 1 and 2 ms from the outputs of block 5 generators. These sequences specify the desired order of processing the frequencies of the next channel: 1700, 1500,, 1100,900,700,500 and 425 Hz. The remaining five address inputs of the decision block 18 receive through the feedback circuits from the outputs of the feedback register 20 information on the results of processing the previous signal frequencies in this channel.

Due to sequential sequential processing of all eight frequencies in a given channel, the receiver has an additional reserve for increasing noise immunity: it is possible to rotate the frequency processing sequence using information on previously received frequencies to optimally select the thresholds for receiving subsequent frequency components of the signal. Since the delta encoder contributes to the high-frequency boost due to signal differentiation, the reception thresholds and signal-to-noise ratio at higher dialing frequencies are maximized. In the presence of a low-frequency component, the high-frequency component of the signal is easily distinguished, and the converse is not true. Therefore, it is advisable to carry out sequential signal processing in the channel, starting with the highest frequency FI 1700 Hz and gradually lowering it to the lowest possible frequency Fe 425 Hz. The results of processing Fi 1700 Hz (receive - 1, receive - 0) are stored in the feedback register 20 and are used to selection threshold for receiving F2 1500 Hz. If the component FI is accepted, then for F2 a slightly lower reception threshold is set against the background of FI, otherwise the reception threshold of the component Fa is increased, because it is expected to be received in conjunction with a component from the Rz-Pb series 1300-700 Hz. The frequency P3 is received using the results of processing the signal components FI, Fa. This allows you to choose one of four options for reception thresholds depending on the presence (absence) of the components FI, F2 separately, both of them together. Reception of the F4 frequency can even be prohibited if all three preceding components are present (receiving the 3rd component of the two-frequency signal is not prohibited in order to detect a malfunction of the general equipment of code 2 of 6 on the transmitting side of the dialer). The processing of the Fe 700 Hz signal occurs when the situation is completely known about the reception of one of the five (or none) of the preceding components. The single-frequency reception of Fe corresponds to the highest threshold due to the good adaptation of the delta encoder to the sinusoidal signal. In the remaining variants of the two-frequency reception of Fe together with the component from the series Fi-Fs, the threshold decreases, and against the background of Fi-Pz, it is more

0 degrees, and against the background - to a lesser extent (but not less than twice as compared to the single-frequency reception of Fe).

Finally, the reception of F 500 Hz and FS 425 Hz occurs in a fully known prior situation and is only permitted in the absence of components 2 of 6 Fi-Fe code. The presence of at least one of them causes a ban on the reception of Fy and FS, thereby achieving protection against reception in the F7 500 filter

0 Hz at the 3rd harmonic, if the F2 signal of 1500 Hz was actually transmitted. The same can be said about protection against receiving Fa 425 ± 25 Hz at the 3rd harmonic in the presence of a signal Pz 1300 Hz.

5 The described frequency-adaptive selection of initial reception thresholds is carried out in decision block 18 using the information recorded in the feedback register 20. Depending on the value of the Z code, the address inputs of the decision block 18, the numbers of the processed frequency at its next three inputs and information in the register

5 20 feedback at the last five inputs, at the first five outputs of the decision block 18 in the middle of the interval L T / 2 125 μs, an adaptive threshold code is generated, which is stored in register 19

0 adaptive code until the end of the AT processing interval of a given frequency. If the code at the first five inputs of the decision block 18 is lower than a minimum for a given frequency initial threshold n0, at the first

5 five outputs of the decision block 18 and the adaptive code register 19 stores the maximum five-digit binary code 11111, which prohibits the reception of this frequency at the end of the processing interval D T. If the code Z is at the inputs of the decision block 18

pp

X + Y in the first five

higher I at the outputs of the decision block 18 is generated and in the register 19 of the adaptive code is stored in the middle of the analysis interval A T / 2 proportional adaptive code na K. P1 (K 1.2-1.6), the predictive level of the current code signal P2 at the end the second half of the analysis interval A T. Both codes (pa and P2) at this moment are compared with each other in the threshold code comparator 21, at the output of which (greater than or equal to), a high level of a logical unit arises if P2 S ha. Otherwise, at P2 Pa, a logic zero appears at the output of the threshold code comparator 21, indicating that the component of the signal of this frequency is not accepted either because the frequency-dependent minimum initial threshold n0 is not reached in the first half of the processing interval, or because the adaptive threshold to the end of the signal processing interval of a given frequency in the next channel,

Such a construction of the decision block 18 in combination with the adaptive code register 19 allows you to track the dynamics of the code growth in the digital correlometer at two time points - in the middle and at the end of the processing interval, and thereby provide protection against receiving false two-frequency signal pairs at random sign-changing intervals in Intervalless mode, when dialing messages follow each other without interruption.

The output of the threshold code comparator 21 goes simultaneously to the information ones. the inputs of the feedback register 20 and the output register 22 promoted by the clock frequency f 1 / AT 4 kHz from the clock output of the generator unit 5. By the end of the analysis of this AT 2 & ms channel, the accumulation of information on all eight possibilities is completed in the output register 22. frequency component of the signal. This information is output to the receiver via the first seven data buses, with information about frequencies of 500 and 425 Hz being combined in the OR element 24 and output to the first data bus. Information is received via the eighth data bus to the output of the receiver about the presence of two or more received frequency components of the signal of this channel in the dialing code 2 of 6, while a high level of logical units is transmitted via the 8th bus, Otherwise receiving a single frequency signal or not accepting any of the frequencies, a low logic zero level appears on the 8th bus.

To generate this information, two of the three free bits of the output word of the EPROM in the decision block 18 are used, which are fed to the logical block 23 in combination with information about the single-frequency signal FG 700 Hz from the second output bus of the receiver. The first of the free bits of the output word of the decision block 18, which arrives at the first input of the logic block 23, contains information about the reception of one or more frequency components of the signal. The second input of the logic block 23 receives information about the reception of two or more frequency components from the first five possible (except Fe 700 Hz, F 500 Hz and Fa 425 Hz), the Logical block 23 contains a series-connected AND element NOT in units of the first and to the third inputs, the output of which is supplied to one of the inputs of the OR-NOT element by zero meters, to its second, the input receives the second free bit of the output word of the decision block 18.

The eighth output of the decision block 18 contains information that the analysis of the first five frequency components of the signal out of 8 possible has ended - 1700-900 Hz. At the beginning of the processing of Fs. 700 Hz, the stop input of the feedback register 20 receives a low logic zero from the eighth output of the decision block 18, which prevents further advancement of the information in the feedback register 20. This makes it possible to record in it the results of processing the five previous frequency components and to receive the three remaining ones, taking into account previously accumulated information.

 The ninth output bus of the receiver receives a meander with a frequency of FT 500 Hz for changing the numbers of processed channels, and the tenth output bus receives a meander of a cyclic frequency of Hz § 62.5 Hz from the corresponding outputs of block 5 of the generators for clock and cycle synchronization of the device for pairing the receiver with a specialized microcomputers (not shown in FIG.),

Information on the first eight output bus lines of the receiver on the next channel appears at the moment the trailing edge of the FT pulse passes and is held during the processing time of the first frequency component of the subsequent AT channel 250 μs. Then, for the remaining time T 1 FT - AT 1.75 ms, until processing of the subsequent channel is completed, information on the first eight buses is not output.

The proposed adaptive digital group receiver of control signals and interactions with delta modulation is made on digital integrated circuits of TTLSh and CMOS structures. It contains 41 cases of microcircuits of the K1533 (K555), K561, K537 and K573 series. The current consumption from the power supply Ep + 5V + 5% does not exceed mA.

Claims (1)

SUMMARY OF THE INVENTION Adaptive digital group receiver of control and interaction signals with a delta modulation, comprising a first random access memory block, series-connected address switch and generator block, a read-only memory block, the outputs of which are connected to the address outputs of the generator block, and the outputs of the constant block the memory is connected to the first inputs of the multiplier by sine and the multiplier by cosine, and also containing the counter of the sine component, the counter of the cosine component and the threshold code comparator, excellent In that, in order to increase noise immunity, expand the dynamic range and simplify the device, a matching block, a second random access memory block, a first, second and third shift registers, a delta stream read-only memory block, a sine component register, a register are introduced cosine component, calculation unit, decision unit, adaptive code register, feedback register, output register, logic unit and OR element, while the first four data outputs of the matching unit are connected to the corresponding pairs to the combined data inputs of the first shift register and the first and second blocks of RAM, the fifth output of the matching block is connected to the combined clock inputs of the first, second and third shift registers, the register of the sine component, the register of the cosine component and the first input of the block of generators, inputs with the second to the ninth of which are connected to the corresponding outputs of the matching block, while the eighth input of the generator block is combined with the write-read input of the first random access memory block, the ninth input the generator lock is connected to the combined write-read inputs of the second RAM block and the control input of the address switch, the outputs of which are connected to the combined address inputs of the first and second RAM blocks, the outputs of the first shift register are connected to the information inputs of the second shift register and to the first inputs of the memory block of the delta stream, the second inputs of which are combined with the information inputs of the third register 0 shift and connected to the outputs of the second shift register, the outputs of the third shift register are connected to the third inputs of the read-only memory block of the delta stream, the outputs of which are connected to the combined first 5 inputs of the multiplier by sine and the multiplier by cosine, the outputs of each of which are connected to the corresponding the inputs of the register of the sine component and the register of the cosine component, the outputs of which are connected to the counting inputs of the corresponding counter of the sine component and the counter of the cosine component, the reset inputs of which x combined with adaptive clock inputs of register 5 codes, a feedback register, an output register are connected to the output of the generator block, the outputs of the sine component counter and the cosine counter are connected to the corresponding address inputs of the calculation unit, the control input of which is connected to the control output of the generator block, the code outputs of which are connected to the inputs of the same name of the decision block, the first address inputs of which are combined with the second inputs of the threshold code comparator and connected to the outputs of the same name of the calculation unit, the second address e inputs of the decision block are connected to 0 information outputs of the feedback register, the stop input of which is connected to the control output of the decision block, the first outputs of which are connected to the information inputs of the adaptive code register, the outputs of which are connected to the first inputs of the threshold code comparator, the output of which is connected to the combined data inputs feedback register and output register, the first two outputs of which are connected to the inputs of the OR element, the third output of the output register is connected to the third input of the logic block, the first and second inputs which are connected to the sixth and seventh outputs of the decisive 5 blocks.