RU1798720C - Device for tolerance detection of time intervals - Google Patents

Abstract

Application: the device relates to measuring equipment and is intended for use in warning and alarm systems. SUMMARY OF THE INVENTION: the device comprises a sensor of controlled time intervals, including a converter of a controlled parameter into a frequency and a counting trigger, four pulse counters, a block for correction of measured time intervals, which includes two elements of NOT, four D-flip-flops, three elements of NAND, element AND pulse counter, two limit value controllers of the parameter to be monitored, four code comparison blocks, a reference frequency generator, parameter control frequency multiplier, element I. four D-flip-flops, element m NOT and two delay elements with respective linkages. 1 C.p. f-ls, 4 ill.

Description

The invention relates to measuring equipment and is intended for use in warning, alarm and other types of signaling devices in which monitored parameters are converted by measuring means into electrical signals of a frequency-pulse form.

The purpose of the invention is to increase the reliability of the control in the region of the boundary values of the controlled parameter.

In FIG. 1 shows a functional electrical diagram of the device, FIG. 2-4 are timing diagrams explaining the principle of its action.

The device comprises a sensor 1 of controlled time intervals, including, for example, a converter 2 of a controlled parameter to frequency and a counting trigger 3. a first counter of 4 pulses, which is a counter of 1/2 periods

measuring cycle, block 5 for correction of measured time intervals, incorporating elements NOT b, 7. D-flip-flops 8 ... 11, elements I-NOT 12.13, 14, element I 15 and pulse counter 16, limiters 17.18 limit values of the monitored parameter, the first 19 and second 20 blocks of code comparison, the generator 21 of the reference frequency, the second - the fourth 22 ... 24 pulse counters, the dial 25 multiplier control parameter, the third 26 and fourth 27 blocks of code comparison, the element And 28, D-flip-flops 29 ... 32, the element is NOT 33 and the delay elements 34, 35, the first of which provides rzhku incorporation of a single signal, and its second deprotection. Pos. 36 and 37 indicate the outputs of the device.

The device operates as follows.

The codes are preliminarily recorded in the setters 17 and 18; equivalent to the number imX |

S

VI Yu O

pulses NFMBKC and NFMKH of the reference frequency fo read by the counter 22 for a time equal to the duration Tx of one period of the frequency signal Fx generated by the converter 2 when the controlled parameter reaches the maximum permissible values:

Nrmax Txfp p-- fo gmax

Nfmw

FMHH

fo

A code corresponding to the response rate of blocks 19 and 20 is entered into the setter 25 to confirm that the monitored parameter is out of range.

The capacity of the counter A is selected at a slightly larger code setting of the setter 25. It is equivalent to half the periods of the frequency signal Fx per measuring cycle. The overflow output of the counter 16 is organized in such a way that the time A T of its filling is within 1-3% of the duration of the time interval Tnom, for example, at a frequency

  1/2 (Rmax + gmin).

The delay elements 34, 35 are necessary for guaranteed switching of the triggers 29, 3.6 when the counter 22 is reset. Therefore, their setting should slightly exceed the response time of these triggers.

The circuit of the device operates cyclically. At the beginning of each measurement cycle (time to, in the diagram of Fig. 2), all counters are zeroed, and low-level signals (logic 0) are installed at the outputs of triggers 29 ... 32 and 11. and at the outputs of the remaining triggers 8 ... 10, AND-NOT 12 ... 14 elements, AND 15 element, inverters 33, and at the output of the first code comparison unit 19, there are high-level signals (logical 1). Element And 28 is closed. The low voltage at the output of block 19 appears in those cases when the NI code generated at the output of counter 22 exceeds the setpoint Npwakc value of setter 17 and the condition for generating a single signal at the output of the second code comparison block 20 is the inequality NI (Mmin.

The controlled parameter (angular velocity, pressure, volumetric flow rate of a liquid or gas, etc.) is converted by a sensor .2 into an electric signal of a frequency-pulse form, which is fed to the input of a counting trigger 3. Its frequency Fx is determined by

current values of the parameter being monitored. Using trigger 3, it is divided by 2 and converted into rectangular voltage pulses addressed to the information input of the correction unit 5, the first input of the And 28 element and to the counting input of the counter 4, The last is filled on the leading edges of these pulses (MSg4 in Fig. 2). Until

There are zero signals at the outputs of the D-flip-flops 29 and 30, the voltage at the outputs of the AND-NOT 12, 14 elements does not change regardless of the position of the D-flip-flops 8 ... 11 of block 5. Therefore, simultaneously switch the counter 4 to 4 time instants ti, 13, ts, etc. (Fig. 2) at the outputs of the elements 13, 15 active low level signals are set and the counter 22 begins to fill up with pulses of the reference frequency fo,

20 generated by the generator 21 (Ni in Fig. 2,3,4). If the monitored parameter is within the set tolerance field (Pmin Fx Pmax). then the contents of N.I counter 22 at the end of each period T

25 does not exceed the setpoint Mmin of the setter 18, but is larger than the Mrmax code at the output of block 19 at time ta, t4. te etc. low-level pulsed signals are excited, which are transmitted via delay element 34 to the D-input of trigger 29. After zeroing trigger 3 at the outputs of elements And 13, 15, single signals are reset, by which counter 22 is returned to its original state and produced

35 to overwrite the information in the memory of the triggers 29, 30. But since the low voltage is supplied to their D-inputs at this point in time, zero signals continue to remain at the outputs. Element And

40 28 does not open, counters 23 and 24 do not switch.

If the monitored parameter exceeds the permissible value (Fx Pmax), then for a time interval equal to the duration of the 45th measured period Tx, the counter 22 does not have time to fill up to the setting level No.max of the setpoint 17 and a single signal remains at the output of block 19. Therefore, when polling trigger 29 at time t (FIG. 3), it

50 will switch to a single state, prepare element And 28 for opening, and make the following changes to the logic of operation of unit 5:

55 - both inputs of the AND-NOT 12 element receive high-level signals, as a result of which its output is zeroed, and the output of the other AND-NOT 13 element forms 1. which keeps the And 15 element open

state until the trigger 9 is switched;

- on the leading edge of the next pulse signal generated by the counting trigger 3 (time tg). trigger 8 is zeroed and counter 16 begins to fill up with pulses of reference frequency f0;

- simultaneously with the formation of the impulse Tg3, the element And 28 opens and the first unit is written into the counter 23:

- a high level signal continues to arrive at the R-input of counter 22, not allowing it to be filled with impulses of reference frequency f0;

- upon the operation of the counter 16 at the time g3, an active low level signal is excited at the output of the element HE 7, according to which the trigger 8 returns to the single state, and the trigger 9 is reset, switching the AND-NOT 2, 13 elements;

- the element And 15 is closed, removing a single signal from the R-inputs of the counter 22, and the latter is involved in the work, providing by the time G4 accumulation of the output code equal to

Ni (Tx-AT) f0.

Its value is reduced by 1-3% with respect to the actual value corresponding to the product Tx fo, and if it is still smaller than the code setting Mrmax of the setter 17, then the trigger 29 will remain in a single state and the measurement of the duration of the next period will be performed similarly way, i.e. with a delay in turning on the counter 22 for the time AT.

If on the site m0-m the change in the duration of the period Tx to the level of the threshold setting 1 / Рмекс was random and at the moment of time Г4 was not confirmed, then trigger 29 will be returned to its initial (zero) state, and the next measurement of the time interval Тх will be made without correction of its actual duration.

As indicated above, the counter 23 is filled on the leading edges of the pulses and provided that the element And 28 is prepared for opening by the trigger 29. When its contents become equal to or exceeds the code setting of the setter 25, a single signal is set at the output of the comparison unit 26, which is pulse the overflow generated by the counter 4 at the end of the measurement cycle is written to the trigger 31 and the output 36 of the device appears.

nie. indicating n the controlled parameter exceeds the specified threshold mark.

In cases where current values

The 5 monitored parameters become less than the permissible level (Fx FM "H). the duration of the measurement periods becomes sufficient to fill the counter 22 to the code setting NFMHH of the detector 10 18. Unit 20 begins to generate voltage pulses addressed through the delay element 35 to the summing input of the counter 24 and the D-input of the trigger 30. With the arrival of the 1st pulse this the trigger is brought into a single state (for example, at time t in the diagram of Fig. 4), the operation of the device circuit is modified as follows:

- on the leading edge of the next impulse Tg, the trigger 11 switches to the single state due to the active low level signal from the inverter 6 output being supplied to its S-input;

- since both inputs of the I-25 element NOT 14 receive single signals, its output is zeroed, closing the And 15 element and thereby allowing the counter 22 to be filled with impulses of the reference frequency f0 (time point T2):

30 - on the trailing edge of the pulse Tg, trigger 10 is zeroed and starts counter 16 (time moments gz);

- upon filling the last one at the output of the element HE 7, a low level 35 signal is excited, according to which the trigger 10 returns to the single state, and the trigger 11 is reset, setting 1 at the output of the AND-NOT 14 element;

- And element 15 is opened, counter 22 is reset to 40, and the contents of the latter at this point in time will be

Ni (Tx + AT) f0. (4)

45 It is 1-3% more than the actual value determined by the product Tx fo. As a result of this, the operation of the code comparison unit 20 when the controlled parameter is slowly changed becomes more stable and reliable.

Since at the time of the polling of trigger 30 a single signal from the output of block 20 arrives at its D-input, its state does not change and the next measurement of the duration of the period Tx is carried out in a similar way, i.e. with a delay of zeroing of the counter 22 for the time of DT. If it is confirmed during the measurement cycle, the set response rate

unit 20, then the overflow pulse of counter 4 switches the trigger 32 R to the single state, generating an electrical signal at the output 37 of the device indicating a deviation of the controlled parameter below the permissible norm.

Thus, the proposed device captures the achievement of the controlled parameter maximum permissible values after p-times confirmation of this event in any measuring cycle, and after the first operation of the corresponding blocks comparing the codes of the duration of the measured time intervals Tx decrease or increase by 1-3% relative to their actual values, which makes the operation of the circuit elements of the device more stable and reliable and thereby increases the reliability of control in the field of small deviations of the generated NI code from the given settings of YрMax and NFMMH ... The technical and economic effect from the use of this proposal is to improve the technical characteristics of alarm and control devices, to reduce the time of detection of an emergency occurring in a controlled object, and to increase the reliability of the formation of control actions.

Claims (2)

SUMMARY OF THE INVENTION 1. A device for tolerance monitoring of time intervals, comprising a sensor for controlled time intervals, two pulse counters, an And element, two D-triggers and a reference frequency generator, which are further included in order to increase the reliability of the control in the region of the boundary values of the controlled parameter, a correction unit for the measured time intervals, two pulse counters, four code comparison blocks, two delay elements, two D-flip-flops, a NOT element, two limit value adjusters are introduced into it the parameter to be monitored and the multiplicity adjuster to control the parameter, the outputs of which are connected to the first inputs of the third and fourth code comparison blocks, the second inputs of which are connected respectively to the outputs of the third and. the fourth pulse counter, while the output of the sensor of controlled time intervals is connected to the information input of the correction unit for the measured time intervals, with the first input of the And element and the counting input of the first pulse counter, the overflow output of which is connected to its zero input, zeroing inputs third and fourth pulse counters, with synchronization (by them the inputs of the third and fourth D-flip-flops and through the HF element - with the installation inputs in O of the first and second D-flip-flops, the counting input of the third pulse counter is connected to the output of the And element, the output of the first block of code comparison through the first delay element is connected to the information input of the first D-trigger, the output of which is connected to the second input of the And element and the first control input of the correction block time intervals, the second control input of which is connected to the output of the second 5 D-flip-flop, the output of the second code comparison unit through the second delay element is connected to the information input of the second D-flip-flop and the counting input of the fourth counter, the output of the model of the frequency generator is connected to the counting input of the second pulse counter and to the input of the clock pulses of the block for the correction of the measured time intervals , the output of which is connected to the zeroing input of the second pulse counter and the synchronization inputs of the first and second D-flip-flops, the first groups of inputs of the first and second code comparison blocks are connected to the outputs of the second pulse counter, and their second input groups are connected respectively to the outputs of the first and second limiters of the limit values of the monitored parameter, the outputs of the third and fourth code comparison blocks are connected respectively 5 information inputs of the third and fourth D-flip-flops, the outputs of which are the outputs of the device, and the installation inputs О of these triggers are connected to the Reset bus. 0 2. The device according to claim 1, with the proviso that the block of correction of the measured time intervals contains four D-flip-flops, two elements NOT, three elements NAND, pulse counter and element And, the output of which is the output of the block for the correction of the measured time intervals, and its information input is connected to the synchronizing input of the first D-trigger, with the installation input of the second D-trigger, with the first input of the second AND-NOT element and through the first element NOT-with the synchronizing input of the third D-trigger and the installation input in 1 of the fourth D trigger, output of the first D trigger 5 is connected to the synchronizing input of the second D-trigger and the first zeroing input of the pulse counter, the second zeroing input of which is connected to the output of the third D-trigger and the synchronizing input of the fourth D-trigger, the first and second control inputs of the correction unit of the measured time intervals are connected respectively to the first inputs of the first and third elements AND NOT, and its sync pulse input with a summing pulse counter input, the output of which through the second element is NOT connected to the installation inputs in 1 of the first and third D-flip-flops, the outputs of the second and fourth D-flip-flops are connected respectively to the second inputs of the first and third elements AND NOT, the outputs of which are connected to the second input of the second element AND NOT and the first input of the element AND, respectively, the second input of which is connected to the output of the second element NAND, the information inputs of D-flip-flops are connected to the signal bus of the zero level. twenty and