RU1797160C - Phase shifter - Google Patents

Abstract

The invention relates to automation and computer engineering. In order to increase accuracy, an inverter 5, blocks of elements And 6-9, DACs 10, 11 are introduced into the phase shifter containing the power supply voltage, the sine-cosine sensor 12, the summing unit 13, and the power supply voltage is made up of a pulse generator T , counter 2, read-only memory devices 3, 4. The invention provides a two-step measurement. In the first, the sine and cosine supply voltages are supplied to the input windings of the ACS 12; in the second, the cosine and Sine supply voltages are supplied to the input windings of the ACS 12; and the elder category of the counter 2.2 ill.

Description

ate

with

The invention relates to automation and computer engineering and can be used in instrumentation, mechanical engineering, process control systems, etc.

An object of the invention is to increase the accuracy of a phase shifter.

In FIG. 1 shows a block diagram of a phase shifter; in FIG. 2 - time diagrams of his work.

The faeo rotator contains a pulse generator 1, a counter 2, read-only memory (ROM) 3, 4, an inverter 5, blocks of elements 6-9, digital-to-analog converters 1Q, 11 (DAC), a sine-to-sine sensor (ACS) 12, summing unit 13.

Phaser is as follows.

The pulse generator 1 generates stable frequency pulses, which are fed to the counting input of the counter 2. As a result, the code at the output of the counter is constantly increasing.

Due to the fact that the outputs of the counter are connected to the address inputs of the ROMs 3 and 4, code words will be generated at the outputs of the latter in accordance with the contents of the memory devices.

The resolution of counter 2 is n, and its capacity is 2. Within 2 pulses from the generator 1, a logic zero signal is set at the nth output of the highest order of counter 2, and then, during the same period of time, a logical unit.

Thus, in the first half of the measurement cycle, determined by the pulses of the generator 1, the logic unit signal is set at the output of the inverter 5, and during the second half of the measurement cycle.

about

vl

 about

determined by subsequent pulses, a logic zero signal will be set at the inverter 5 output.

Therefore, at the output of the DAC 10, during the first two clock cycles, the code words contained in ROM 3 will be supplied through block 6, and during subsequent clock cycles the code words contained in ROM 4 through block 7, while to the inputs DAC 11 during the first clock cycles of the device, the code words contained in ROM 3 will be supplied. DAC 10 and DAC 11 convert the code patterns arriving at them into corresponding voltage levels.

The outputs of the digital-to-analog converters are connected to the first and second inputs of the sine-cosine sensor 12, which, in turn, generates signals to the inputs of the summing unit.

In the first and second half-cycles of the measurement cycle, a value is generated at the output of block 11 that is equivalent to half the phase shifts of the first and second output windings, respectively

 and fw + a

where the first index corresponds to the output of the ACS 12, and the second index indicates a half-period of measurement. At the end of the measurement cycle, a signal value is generated at the output of block 11, which is equivalent to the half difference Ф1 And Ф}.

Claims (1)

SUMMARY OF THE INVENTION A phase shifter comprising a power supply, a sine-cosine sensor, the outputs of which are connected to a summing unit, characterized in that. in order to increase the accuracy of the phase shifter, an inverter, four blocks of AND elements, and two digital-to-analog converters are introduced into it, and the power supply voltage is made up of two constant memory devices, serially connected by a pulse generator, a counter, the outputs of which are connected to the address inputs of the first and the second read-only memory, the older bit of the counter of the power supply voltage, is directly connected to the control inputs of the first and The contents of memory devices 3 and 4 are such that the DACs 10 and 11, when the key circuits are described, generate signals whose envelopes are either sin 0) 1 or cos ω t, where ω is the circular frequency of the generated signals (see Fig. 2). Moreover, the moments chosen to stop generating one signal and start generating another time ti,, 2, ..., for which it is true: sin wt cosfi) t. Thus, the implementation of the proposed power circuit ACS 12 allows you to refuse to use in the composition phase shifter of analog switches, which means to send to the ACS signals more stable in amplitude and phase, reduce the error, and increase the accuracy of information conversion. in the prototype phase shifter with a tunable structure based on sine-cosine converters and electronic switches, an error arises due to the instability of the vapor last meters. The proposed devices are largely devoid of this drawback due to the fact that the voltages supplying the sine-cosine converter are formed by digital-to-analog converters and are not passed through analog switches. the second block of AND elements, the information inputs of which are connected to the outputs of the first constant storage device of the power supply voltage, the output of the high-order bit of the counter through an inverter is connected to the control inputs of the third and fourth blocks of AND elements, the information inputs of which are connected to the outputs of the second constant the storage device of the power supply voltage, the corresponding outputs of the first and third, second and fourth blocks of elements And are paired and connected to digital the input inputs, respectively, of the first and second digital-to-analog converters, the outputs of which are connected to the corresponding inputs of the sine-cosine sensor. And btri fatv „f4e in rtit“ t2 fufcf aftffptnofXt S Output