RU1795473C - Arithmetic device for executing quick transform of hartley-fourier - Google Patents

Abstract

The invention relates to computer technology and can be used in spectral analysis and signal synthesis apparatus. The purpose of the invention is to increase performance. The device comprises addition / subtraction units, a switch, and complex number multipliers. 1 tablet, 2 ill.

Description

The invention relates to the field of computer engineering and can be used in spectral analysis and signal synthesis equipment.

A fast real Hartley-Fourier transform device is known, comprising a synchronization unit, two address counters, a read-only memory block, four registers / two multipliers, an adder-subtractor, a read-only memory block and three switches. In this apparatus, the basic operation of the Hartley Fast Transform Algorithm (FHL) for base two is performed in three clock cycles. A disadvantage of the known device is the low speed.

The closest in technical essence to the invention is a device for performing fast Fourier transform, containing two groups of memory blocks, an adder, a subtractor and a multiplier of complex numbers, two delay elements, three switches, two counters, a decoder, a register, an element block And, a block read only memory and synchronization unit.

The device implements the FFT algorithm at base two with decimation in frequency. To perform an N-point FFT, it is necessary to perform N / 2log2N iterations. A disadvantage of the known device is the low speed.

The purpose of the invention is to increase speed. This goal is achieved by the fact that in the arithmetic device for performing fast Hartley-Fourier transform (FHF), containing two blocks of addition-subtraction, a switch and a multiplier of complex numbers, and the output of the first block of addition-subtraction is connected to the first input of the multiplier of complex numbers, additionally introduced four blocks of addition-subtraction and a second multiplier of complex numbers, the first and second inputs of the third, fourth, fifth and sixth blocks of addition-subtraction are connected to the inputs of the device with th to eighth, respectively, and their outputs are connected to the first device outputs the first through fourth, respectively, the outputs

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with

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which, from the fifth to the eighth, are connected to the first and second outputs of the first and second complex number multipliers, respectively, the second inputs of which are connected to the first outputs of the switch and the second addition-subtraction unit, respectively, and their third and fourth inputs are connected to the inputs of the phase factors of the device, the control input of the device is connected to the control input of the switch, the second output of which is connected to the first input of the second block of addition-subtraction, the first and second inputs of the switch are connected to the second E outputs of the first and second combining units -vychitani respectively, the first inputs of which are connected to the second output of the third and sixth, and the second input - to the second output of the fourth and fifth adder blocks -vychitani respectively.

When studying other variants of technical solutions in this technical field, features that distinguish the claimed device from the prototype were not detected, which ensures that it meets the criterion of significant differences.

A comparable analysis with the prototype shows that the claimed device is distinguished by the presence of new blocks: a complex number multiplier and four addition-subtraction blocks, as well as the presence of new bonds, which makes it consistent with the novelty criterion.

A diagram of an arithmetic apparatus for performing FHPC is shown in FIG. 1, FIG. Figure 2 shows a graph of the BPH algorithm for a split base of two to four with decimation in frequency based on the proposed basic operation.

The device contains information inputs 1-8, control input 9, phase factor input inputs 10-13, addition-subtraction blocks 14-19, switch 20, complex number multipliers 21.22, information outputs 23-30.

The inputs of the device 1, 3, 5, 7 are connected to the first inputs of the addition-subtracting blocks 14, 15, 16, 17, respectively, and the inputs 2, 4, 6, 8 are connected to the second inputs of the blocks 14, 15, 16, 17, the first the outputs of which are connected to the outputs 23, 24, 25, 26 of the device, respectively, the second outputs of the add-subtract blocks 14, 15 are connected respectively to the first and second inputs of the block 18, the second outputs of the blocks 17, 16 are connected respectively with the first and second inputs of the block 19, the first output of which is connected to the second input of the multiplier 22, the first input of which is connected to the output of the comm cutter 20, the inputs of which

connected to the second outputs of blocks 18, 19, and its second output is connected to the second input of the multiplier 21, the first input of which is connected to the first output of the block 18, the first and second outputs of the multipliers 21, 22 are connected respectively with the outputs 27,28, 29,30 devices, inputs 10,11,12, 13 of which are connected respectively to the third and fourth inputs of the miners 21, 22, the control input of the switch 20 is connected to the input 9 of the device.

The basic operation of the BPH and FFT algorithms on a split base two to four with decimation in frequency is described by the following system of equations:

A1 a + e; b1 b + f; d1 d + h; c1 s + g;

n (a - e) + (b - f); qi (a - e) - (b - f);

rz (d - h) - (c - g); qs (d - h) + (c - g);

. + CYqij-YKjJSN f1 nSNK- (Yqi + Yr3) CNK;

g1 (Yr3 + Yqi) CN3Rr + q3SN3K; h1

 (Yr3 + Yqi) SN-q3CN3, where a, b, c, d, e, f, g, h are the inputs of the device;

a, b, c, d, e, f, g, h are the outputs of the device ;.

Y is the signal value at the control input of the switch (Y. О, 1).

Here Smg cos (2 tgg / N), SNT sin (2 lg / N),

The device operates as follows.

At the information inputs 1-8, input numbers enter the device. Inputs 10–13 receive phase factors. In addition-subtract blocks 14-19, each of which contains an adder and a subtractor, addition and subtraction operations are performed in accordance with the expression:

40

 l + m; t

t

il

where I, t are the inputs of the block; I, t - block outputs.

The switch 20 passes the data arriving at its inputs directly or crosswise, depending on the value of the signal Y at the 5th input 9 of the device. If Y 0, then the data goes straight, if Y 1 - crosswise.

On multipliers 21.22 complex numbers, the operations of multiplying the numbers coming from blocks 18, 19 and the switch 0 20 by phase factors are performed in accordance with the expressions:

I1 1Sm + t5mk: I ICw3K + tZyzk:

T1 15mk - tSm; t ISN3K - tSmZK where I. rri - inputs of multipliers; 5 | t are the outputs of the multipliers;

Smg, Zmg - phase factors received at inputs 10-13.

The first expression is implemented on the multiplier 21, the second on the multiplier 22.

The execution order of the FFT and FFT algorithms based on the proposed basic operation is determined by the algorithm graph. In FIG. Figure 2 shows a graph of a split-base FHL algorithm of two to four with frequency decimation for N 32.

The basic operation on the graph is indicated by a rectangle inside which the first digit indicates the value of the control signal Y, the second and third in order from top to bottom determine the values of the parameters K and N, used to enter the phase factors Cr /, SNK, Sczk. SN.

For K 1, N / 8-1, these factors take the values CNK cos (2 lK / N), SNK sin (2jr K / N), SyZK C05 (2 ZK / N). 5kzh sl n (2 L: ZK / N), and for K 0 at N 8 (a third digit is equal to the conversion dimension N) OHH are respectively equal; 0, 1, - 2/2 and v2 / 2. In the final step of the conversion, zeros (0) are supplied to some inputs, and some outputs are not used. At this stage using the base

10

fifteen

twenty

four-point operations and pairs of two-point transformations are implemented. The first of them are designated by a triple of parameters 1,0, 4, and the second by O, O, 2, which are realized with phase factors equal to 1 for a four-point conversion, and 1/2 for two two-point conversion. The order of communications between inputs and outputs of basic operations is shown in FIG. 2.

 The speed of the proposed arithmetic device for performing FHF is defined as the sum of the time it takes to complete one, multiply complex numbers and two additions, which is only one addition operation more than in the prototype device, which is insignificant. The table shows the number of basic operations when performing the N - point (N 2m, n 5.12) BPH algorithm on the proposed device and the prototype device, as well as the performance gain. When performing the FFT algorithm, the performance gain is similar.

Claims (1)

Shadow image formula An arithmetic device for performing fast Hartley-Fourier transform, comprising the first and second addition-subtraction blocks, a switch and a complex number multiplier, the output of the first addition-subtraction block being connected to the first input of the complex number multiplier, characterized in that, in order to increase speed, the third to sixth addition-subtraction blocks and the second multiplier of complex numbers are additionally introduced into it, the first and second inputs of the third, fourth, fifth and sixth addition-subtraction blocks tani are connected to the inputs of the operands of the device from the first to eighth, respectively, and their outputs are connected to the outputs of the result of the device from the first to fourth, respectively, the outputs of which from fifth to eighth are connected to the first and second outputs of the first and second multipliers of complex numbers, respectively, the second the inputs of which are connected to the first output of the switch and the output of the sum of the second block of addition-subtraction, respectively, the third and fourth inputs of the first and second multipliers of complex numbers Nena respectively the first to fourth reference input of the phase multipliers device control input device connected to the control input of the switch vtoro§ whose output is connected to a first input of the second adding unit -vychitani, the first and second data inputs connected to the switch outputs of the first and difference. the second addition and subtraction blocks, respectively, whose first inputs are connected to the outputs of the difference of the third and sixth, and the second inputs are the outputs of the difference of the fourth and fifth addition and subtraction blocks, respectively. i 2 ft 3 4 tf Th Ј b L S / tf .14 .25 .26 J7 .IB go -22 TZ9 JO J TT fO // fl tf Fig f