RU1790786C - Device for matrix multiplication - Google Patents

Abstract

The device for matrix multiplication relates to automation and computer engineering and can be used in the construction of specialized, including systolic, devices designed to perform operations on matrices. An object of the invention is to increase speed. New in the device for matrix multiplication, containing the PCP of the computing modules of the first type 1 and the control unit 3, is the introduction of computing modules 2 of the second type and two switches 4, 5, which allows the organization of continuous processing of three matrices, due to which the speed increases by 2 times. 2 s.p. f-ly, 4 ill.

Description

The invention relates to automation and computer technology and can be used in the construction of specialized, including systolic, devices designed to perform operations on matrices.

The aim of the invention is to increase the speed of the device.

In FIG. 1 is a block diagram of a device for matrix multiplication; on Fig, 2 is a structural diagram of a computing module of the first type; in FIG. 3 is a structural diagram of a computing module of the second type; in FIG. 4 is a block diagram of a control unit, an embodiment,

The device for multiplying the matrices (Fig. 1) comprises PCP computing modules 1 of the first type, PCP computing modules 2 of the second type, a control unit 3, switches of the first 4 and second 5 groups.

The computing module of the first type (Fig. 2) contains the first registers 6, 7, a multiplier 8, an adder 9, a register 10, a trigger 11.

The computing module of the second type (Fig. 3) contains the first register 12, adder 13, multiplier 14, registers 15, 16.

The control unit 3 (Fig. 4) contains an OR element 17, a counter 1.8, a decoder 19, an element NOT 20, registers 21.

The device is designed to multiply the matrices AxBxC F, where A, B and C-matrices of dimension NxN, and can be implemented on the following formulas:

dij 2, aikbkj;

k 1

fis Ј dijCjs

where aik, bkj, CjS are elements of the matrices A, B and C; dij are the elements of the intermediate matrix; fis elements of a finite matrix F, consider the operation of the device. For simplicity of description and without loss of generality, we set N 3. We agree that information is received in all registers along the leading edge of the clock pulse, i.e., at the beginning of the clock cycle. We assume that before the commencement of calculations, all registers are set to the zero state. The start pulse is supplied to the first input of the control unit 3 (start input), through the OR element 17 it is supplied to the second input of the counter 18 (recording enable input, the counter 18). Counter 18 operates in a subtraction mode. Decoder

19 decrypts the state of zero. The first inputs of the computing modules of the first type of the first column receive the elements aik of the matrix A in rows, the second inputs - the elements bkj of the matrix B in the columns. Elements of the GJS matrix C arrive at the first inputs of the computing modules 2.1,1-2.p.1 in rows

twenty

The resulting matrix is obtained as follows;

5

0

fn dncii

f21 d22C21

fai dsacsi

fl2 dnci2 f22 d22C22 f32 d33C32

fis dnci3

f23 d22C23

f33 dsscss

+ d21C21 + + d32C31 +

+ di3cn +

+ d21C22 + + d32C32 + + dl3C12 + + d21C23 + + d32C33 +

+ di3Cis +

dsicsi; di2cn; d23C2i; d3iC32; di2ci2;

d23C22I

d3iC33;

dl2Cl3, d23C23.

5

0

5

0

5

Zero beat. The first and second inputs of the computing module 1.1.1 respectively receive the elements bc and an and are recorded in registers 6.1.1 and 7.1.1, respectively. The first and second inputs of computing module 1.2.1 respectively receive bi2 and 321 and are recorded in registers 6.2.1 and 7.2.1, respectively. The first and second inputs of the computing module 1.3.1 respectively receive bis and az1 and are recorded in registers 6.3.1 and 7.3.1, respectively.

In the first cycle, from the outputs of the registers 6.1.1 and 7.1.1, the elements bc and an arrive at the first and second outputs of the computing module 1.1.1 and at the first and second inputs of the multiplier 8.1.1, from the output of which the product bnaii goes to the adder 9.1.1 where it is added to zero and written to register 10.1.1. The following elements b21 and ai2 arrive at the inputs of the computing module 1,1,1 and are recorded in the registers 6.1,1 and 7.1.1. Elements bi2 and 321 arrive at the inputs of computing module 1.1.2 and are written to registers 6.1.2 and 7.1.2. The first input of adder 9.2.1 of computing module 1.2.1 receives the product 32ibi2, where it is added to zero and written to

register 10.2.1. In registers 6.2.1 and 7.2.1, respectively, b22 and 322 are written. B registers 6.2.2 and 7.2.2 of computing module 1.2.2 respectively write elements bis and an. The first input of the adder 9.3.1 of the computational module 1.3.1 receives the product aztmz and is added to zero, the result is written to register 10.3.1. The registers 6.3.2 and 7.3.2 of computing module 1.3.2 respectively record the elements bi2 and az1.

In the second clock, from the output of register 10.1.1 of the computing module 1.1.1, the product aiibn is received at the second input of adder 9.1.1, the first input of which from the output of the multiplier 8.1.1 receives 312021 and the result anbii + ai2bai is again written into register 10.1.1. In the registers 6.1.1 and 7.1.1, respectively, the entries bbt and ai3 are written. At the output of the adder 9.1.2 of the computing module 1.1.2, there will be the sum a2ibn + 0, which is written to register 10.1.2. L21 and 322 are written to the registers 6.1.2 and 7.1.2. Bis and 321 are written to the registers 6.1.3 and 7.1.3 of the computing module 1.1.3. The products aaibi2 are received at the inputs of the adder 9.2.1 of the computing module 1.2.1

And 322b22 AND Since its EXIT Sum 32lbl2 + 322b22

written to register 10.2.1. 323 and b2 are recorded in registers 6.2.1 and 7.2.1. At the output of the totalizer 9.2.2 of the computing module 1.2.2, the sum anbi3 + 0 appears and is recorded in register 10.2.2. In registers 7.2,2 and 6.2.2, 312 and D23 are recorded. In registers 7.2.3 and 6.2.3 of computational module 1.2.3, az1 and bc are written. The inputs of the adder 9.3.1 of the computational module 1.3.1 are supplied with the products aztb3 and az2b23, and the result 33ibi3 + 332b23 is recorded in register 10.3.1. In the registers 7.3.1 and 6.3.1, azz and b3 are written. From the output of the adder 9.3.2, the asibi2 + 0 of the computing module 1.3.2 is written to the register 10.3.2. Az2 and D22 are recorded in registers 7.3.2 and 6.3.2. In the registers 7.3.3 and 6.3.3 of the computational module 1.3.3, the elements an and bi2 are recorded, respectively. In the third clock in the adders 9.1.1-9.1.p of the computing modules 1.1.1-1.1.P we get the first elements dij of the intermediate matrix D. Thus, from the output of the adder 9.1.1 of the computing module 1.1.1, the anbii + ai2b2i + ai3b3i dn and is written to register 12.1.1 of computing module 12.1.1. The inputs of the registers 7.1.1 and 6.1.1 receive the elements an and bc of the new matrices A1 and B1. In the register 15.1.1 from the second input of the computing module 2.1.1, an element of the si matrix C is written. From the output of the adder 9.1.2 of the computing module 1,1.2 in

register 10,1.2 is written a2ibn + 322b2L In registers 7.1.2 and 6,1.2 respectively 323 and b3 are written from the output of the adder 9.1.3 of computing module 1.1.3 to register 10,1,3. 32ibi3 + 0 is recorded. A22 and 023 are written to the registers 7.1.3 and 6.1.3. In the adder 9.2.1 of the computational module 1.2.1, we get a2ib 12 + 822022 + 823032 d22 and the element d22 is written to the register 12.2.1

0 computing module 2.2.1. The inputs of the registers 7.2.1 and 6.2.1 receive elements of new matrices. In register 15.2.1, C21 is recorded. From the output of the adder 9.2.2 computing module 1.2.2 in the register 10.2.2

5, the sum of anbi3 + ai2b23 is recorded. In registers 7.2.2 and 6.2.2, the elements ai3 and b3 are written. From the output of the adder 9.2.3 of the computing module 1.2.3, az1b + 0 is written in the register 10.2.3. To registers 7.2.3 and

0 6.2.3, az2 and b21 are recorded. In adder 9.3.1 of computational module 1.3.1, we obtain az1b1z + az2b23 + az3b3b3s3 and the element dss is written to register 12.3.1 of computational module 2.3.1. To registers 7.3.1 and 6.3.1

5, elements of new matrices are recorded. In register 15.3.1, cs1 is written. The output of adder 9.3.1 of the computational module 1.3.2 is written in register 10.3.2 az1b12 + az2b22. In registers 7.3.2 and 6.3.2, azz and b2 are written. From the output of the adder 9.3.3 of the computing module 1.3.3, anbi2 + 0 is written to the register 10.3,3. To the registers 7.3.3. and 6.3.3 are written ai2 and. In the fourth cycle, in adder 9.1.2 of computational module 1.1.2, we obtain the sum 32ibn + a22b2i + a23b3i d2i and the element d2i is written to register 12.1.2 of computational module 2.1.2. C21 is written to register 15.1.2. From the output of the adder 9.1.3

0 computing module 1.1.3 enters a2ibi3 + a22D23 and is written to register 10.1.3. 323 and b3 are written to the registers 7.1.3 and 6.1.3. The inputs of the multiplier 14.1.1 of the computing module 2.1.1 are

5 the elements dn and si, where dncn multiplication occurs and the product goes to the adder 13.1.1, where it is added to zero and dncn + 0 is written in register 16.1.1. In the register 12.1.1 the element dn is written, and

0 element is transferred to computing module 2.2.2 and is recorded in register 15.2.2. In adder 9.2.2 of computational module 1.2.2, we obtain anbi3 + ai2b23 + ai3b33 dis and the element dis is recorded in register 5 of register 12.2.2. From the output of adder 9.2.3 of computational module 1.2.3, we obtain asibn + a32b22 and this sum is written to register 10.2.3. In registers 6.2.3 and 7.2.3, b3 and azz are written. In the adder 9.2.1 of the computing module 2.2.1 we get the sum

J22C21 + 0, which is written to register 10.2.1. In register 12.2.1, daa is written. In the adder 9.2.1. In register 12.2.1, d22 is written. In adder 9.3,2 of computational module 1.3.2, acib 12 + az2b22 + az3bz2 Oz2 is obtained and recorded in register 12.3.1 of computational module 2.3.2. Cs1 is written to register 15.3.2. From the output of the adder 9.3.3 of the computational module 1,3.3, anbi2 + ai2D22 is received and written to register 10.3,3. In registers 7.3.3 and 6.3.3, ac3 and b2 are written. From the output of the adder 13.3.1, the computational module 2,3.1 arrives from ssss1 + 0 and is recorded in register 16.3.1. Register 12.3.1 is written (J33.

In the fifth cycle, in adder 9.1.3 of computational module 1.1.3, we obtain 32ibi3 + a22b23 + a23b33 d23 and element d23 is written to register 12.1.3 of computational module 2.1.3. To the register 15.1. 3, C21 is recorded. From the output of the adder 13.1.2 of the computing module 2.1.2, diicn + d2iC2i is received and recorded in the register 16.1.2 of the computing module 2.1.2. An element dai is written to register 12.1.2. From the output of the adder 13.1.1 of the computing module 2.1.1, dnci2 + 0 is output and is written to the register 16.1.1. Register 12.1.1 records dn. In adder 9.2.3 of computational module 1.2.3, we obtain az1b + az2b22 + az3bz1 (J31 and the element dsi are written to register 10.2.3 of computational module 2.2.3, cb1 is written to register 15.2.3. From the output of adder 13.2.2 of computational module 2.2 .2 is issued dsscsi + discii and written to register 16.2.2. Dis is written to register 12.2.2. From the output of adder 13.2.1 of computing module 2.2.1, d22C22 + 0 is received and written to register 16.2.1. To register 15.2.1 In adder 9.3.3 of computational module 1.3.3 we get anbi2 + ai2b22 + ai3b32 di2 and element di2 is written in register 12.3.3 of computational about module 2.3.3. It is written in the register 15.3.3. From the output of the adder 13.3.2 of the computing module 2.3.2, d22C32 + 0 is entered and is written in the register 16.3.2. In the register 12.3,2 is written d32. From the output of the adder 13.3. Computing module 2.3.1 1 receives d33C32 + 0 and is recorded in register 16.3.1.

In the sixth cycle in the adder 13.1.3 of the computational module 2.1.3, we obtain the first final result d33C3i + di3Cn + d23C2i fai, which is recorded in register 14.1.3. In register 12.1.3, d23 is written. From the output of the adder

13.1,2 of computational module 2.1.2 enters dnci2 + d2iC22 and is recorded in register 16.1.2. In register 12.1.2, d2i is written. From the output of the adder 13.1.1 of the computing module 2.1.1, dnci3 is received and is recorded in register 16.1.1. In adder 13.2.3 of computational module 2.2.3, we obtain dncn + d2iC2i + d3iC3i fn and the result fn is written to register 16.2.3. To register

0 15.2.3 is recorded sz2. From the output of the adder 13.2.2 of the computing module 2.2.2, d33C32 + disci2 is received and recorded in register 16.2.2, C13 is written in register 15.2.2. From the output of the adder 13.2.1 of the computing module 2.2.1, d22C23 + 0 is received and is recorded in register 16.2.1. In adder 13.3.3 of computational module 2.3.3, we obtain d22C2i + d32C3i + di2Cn f2i, and the result is written to register 16.3.3. To register

0 12.3.3 is written di2. From the output of the adder 13.3.2 of the computing module 2.3.2, d22C22 + d32C33 is received and recorded in register 16.3.2. In register 12.3.2, d32 is written. From the output of the adder 13.3.1 of the computing module 2.3.1, ds3C33 + 0 is received and is recorded in register 16.3.1.

In the seventh cycle, in adder 13.1.3 of computational module 2.1.3, we obtain d33C32 + di3Ci2 + d23C22 GZZ and the result of TZZ0 is written to register 16.1.3, and its output to the output of the device is issued fsi. From the output of the adder 13.1.2 of the computational module 2.1.2, dnci3 + d2iC23 is received and written to register 16.1.2. In the adder 13.2.3 of the computational module 2.2.3, we obtain dnci2 + d2iC22 + d3iC32 fi2 and the result is written to the register 16.2.3, from the output of which fn is output to the output of the device. In register 12.2.3, dsi is written. From the output of the adder 13.2.2 of the computing module 2.2.2, d33C33 + di3Ci3 is received and recorded in register 16.2.2. In adder 13.3.3 of computational module 2.3.3, we obtain d22C22 + d32C32 + di2Ci2 f22 and the result is written into register 16.3.3, from the output of which f2i is output. In register 12,3.3, di2 is written. From the output of the adder 13.3.2 of the computational module 2.3.3, d22C23 + d32C33 is received and recorded in register 16.3.2.

0

In the eighth cycle, in adder 13.1.3 of computational module 2.1.3, we obtain d33C33 + disci3 + d23C23 f33 and the result T3 is written to register 16.1.3, from the output of which f32 is output. In adder 13,2.3 of computational module 2.2.3, we obtain dnci3 + d2iC23 + d2iC33 fi3 and the result is written to register 16.2.3, from the output of which fi2 is output. In the adder 13.3.3 of the computing module 2.3.3 we get

d22C23 + d32C33 + ai2Ci3 f23 and the result is written to register 14.3.3, the output of which is f22.

In the ninth cycle, the outputs of the computational modules 2.1.3, 2.2.3, and 2.3.3, respectively, give the final results

f33, f23, fl3 At this point, the operation of the device for calculating the matrix F AxBxC is completed.

Claims (3)

SUMMARY OF THE INVENTION 1. A device for matrix multiplication, comprising a first-type PC module of computational modules (n is the dimension of the matrices) and a control unit, the first, second, third and fourth inputs of which are connected respectively to the start input, reset input, counting input and recording input of the device, the first output of the control unit is connected to the write enable input (i, 1) -ro of the computing module of the first type (i 1, ..., p), the synchronization input of the device is connected to the synchronization inputs of each of the computing modules of the first type, distinguishing Especially because, in order to improve performance, (PCs) of the second type of computing modules and two groups of n switches each are introduced into it, the first and second information inputs (i, 1) -ro of the first type of computing module are connected respectively to the outputs ix switches of the first and second groups, the i-th information inputs of the first and second groups of the device are connected respectively to the first and second information inputs ix of the switches of the first and second groups, the control inputs of which are connected respectively to the second and third by the control unit moves, the ith information input of the third group and the logic zero input of the device are connected respectively to the second and first information inputs of the (M) -th computing module of the second type, the write enable output (i, j) -ro of the computing module of the first type 0 1 , ..., p) is connected to the write enable input of the (i, j + 1) -ro computing module of the first type and (ij) -ro computing module of the second type, the output (in) -ro of the computing module of the second type is connected to i- m output of the result of the device, the first information outputs (i, l) -x you illustrative modules of the first and second types (1 1, .... p-1) are connected respectively to the first information inputs of (i + 1, h) -x computing modules of the first and second types (where h j + 1 for (i + j ) - even or h j-1 for (i + j) - odd, and hj for j 1, j p), the second information inputs of (i, l) -x computing modules of the first and second types are connected respectively to the second information inputs ( i + 1, s) -x computing modules of the first and second types (where s j-1 with (i + j) - even or s j + 1 for (i + j) - odd, with sj for j 1, j p), the third information output (i, j) -ro of the computing module of the first type is connected to the third information input (i, j) -ro computational 0 module of the second type. 2. The device according to claim 1, characterized in that each computing module of the first type contains three registers, a multiplier, an adder and a trigger, wherein the information input of the first register is connected to the first information input of the module, the second information input of which is connected to the information input second register, first exit 0 register is connected to the first input of the multiplier and the first information output of the module, the second information output of which is connected to the output of the second register and the second input of the multiplier, the output 5 of which is connected to the input of the first term of the adder, the input of the second term of which is connected to the output of the third register, the information input of which is connected to the output of the adder and the third 0 to the information output of the module, the recording enable input of which is connected to the reset enable input of the third register and the trigger input, the output of which is connected to the write enable output of the module, input 5 synchronization which is connected to the sync inputs of all resistors. 3. The device pop. 1, characterized in that each computing module of the second type contains three registers, a multiplier and an adder, wherein the information input of the first register is connected to the third information input of the module, the first information input of which is connected to the input of the first term of the adder5, the input of the second term of which connected to the output of the multiplier, the first input of which is connected to the output of the first register, the second input of the multiplier is connected to the output of the second register and the second 0 information output of the module, the second information input of which is connected to the information input of the second register, the output of the adder is connected to the information input of the third register, the output 5 of which is connected to the first information output of the module, the recording enable input of which is connected to the recording input of the first register, the synchronization input of the module is connected to the sync inputs of all the registers. G l L. srig.ts