SU1737462A1 - Device for performing operations on matrices - Google Patents

Abstract

The invention relates to computing and can be used in specialized systems of digital information processing. The purpose of the invention is to expand the functionality by solving the problem of decomposing Cholesky symmetric matrices. The goal is achieved by introducing an additional nth computing unit into the device containing n memory blocks and (n - 1) computing blocks, which allow to perform division and extraction operations of the square root and organize the computational process in which at each iteration the matrix is presented in a factorized form. 1 hp f-ly, 5 ill.

Description

The invention relates to the field of computer technology and can be used in specialized digital information processing systems.

A number of devices implementing matrix operations are known, for example, a homogeneous parallel computing structure for calculating the product of a matrix by a vector matrix calculator; device for performing matrix operations.

These devices contain a two-dimensional matrix of operational blocks and tools for organizing the computational process (registers, triggers, synchronization blocks). All these devices allow to perform operations on matrices (multiplication of a matrix by a vector, etc.) and have the following disadvantages, high hardware costs in the implementation of two-dimensional matrices of operational blocks; difficulties

organization of multidimensional information input; inefficient use of computing resources when changing the dimension of the problem; inability to perform matrix decomposition.

Devices for LU matrix decomposition are known, for example, systolic processors for matrix calculations.

These devices also contain two-dimensional arrays of operational blocks and, therefore, have the indicated disadvantages. In addition, devices do not allow decomposition of matrices using the Cholesky algorithm.

A number of devices for performing matrix operations are known, for example, systolic processors for g / atrial operations.

These devices contain a line of operating units that allow more efficient VI.

WITH

VI

N and ND

It is useful to use a computational resource, but they do not allow the decomposition of Cholesky symmetric matrices.

Closest to this is a device containing two matrices of n memory cells and n computation cells, respectively, each memory cell being a dual buffer from a FIFO memory, and each computer cell contains registers, a multiplier and an adder.

The device provides efficient processing of multidimensional signals, in particular, spectral analysis. A disadvantage of this device is the limited functionality in problems of digital signal processing, which does not allow the execution of a number of algorithms associated with the decomposition of Cholesky symmetric matrices.

The aim of the invention is to enhance the functionality of the device by performing the decomposition of Cholesky symmetric matrices.

The goal is achieved by adding an additional computational cell with corresponding connections to the device, which allows performing square root and division operations, as well as new architectural solutions of the computational cells included in the matrix of computational cells.

To ensure the calculation of the Cholesky decomposition of symmetric matrices into the known device, an additional computational cell is introduced, which allows at each step of the iterative process to calculate one column vector of the lower triangular matrix in the Cholesky decomposition. In addition, new architectural solutions of computational cells allowed organizing the computational process in such a way that at each iteration the matrix A was represented in the factorized form Aw F, + iB {H% Vi, where F, + i is the Frobenius matrix, (i The + 1) th column of which coincides with the (i + 1) th column of the lower triangular mat in the Cholesky decomposition, and the matrix

-

-

B1 has the form

wg in 1 11 --- -0--, about 1)

FIG. 1 shows a functional diagram of the proposed device as an example of a specific implementation; in fig. 2 - functional diagram of the n-th computational cell; in fig. 3 - functional scheme

j-th computational cell Q 1, n 1); in fig. 4 - organization of information flows in computational cells; in fig. 5 - time diagram of the work of computational cells.

5 A device (Fig. 1) for decomposing Cholesky symmetric matrices contains information input 1, a matrix 2 of n memory cells (3) 3, information output 4, the n-th computational cell

10 (WL) 5, the matrix 6 of (, with the first input and output of the j-th 0 2, p) ANM connected to the first output and input, respectively, (j - 1) -WN7, and the first input and output of the first SNFZ connected to the first exit and entrance of the 15th nyazyi5; The second output of the jth Q THRDTNECT is connected to the second output of the (j + 1) -th PLNZ, the second output of the nth PLNZ is information output 4 of the device, and the second input of the first SNVZ is information input 20 of the device 1; The second and third outputs of the j-th (j 1, p-2) V7 are connected to the second and third inputs of Q + 1, respectively, on the V-7, and the second and third outputs of the n-th V7 connected to the second and third inputs of the first

25 VY7; fourth entrance j-th (j 1, p-2) ВЯ7

connected to the fourth output 0 + 1) VY7, and the fourth output of the first VYA7 connected to the second input of the n-th VYa5.

The computational cell with the number p co30 holds (Fig. 2) the first input 5.1, the first output 5.2, the third output 5.3, the second input 5.4, the second output 5.5, register 8, block 9 calculating the square root, multiplexer 10, block 11 calculating the reciprocal,

35 adder 12, register 13, multiplier 14, block 15 for changing the sign of the number, register 16, with input 5.1 connected to the first input of adder 12 and the input of block 9 for calculating the square root, the output of which is connected to input of block 11 for calculating

magnitude and the first input of the multiplexer 10; the second input of the multiplexer 10 is connected to the output of the adder 12, and the output of the multiplexer 10 is connected to the input of the register 8,

45, the output of which is the output of the 5.2 pth BS5; the output of the reverse magnitude calculating unit 11 is connected to the input of the register 13, the output of which is the output 5.5 of the nth VL5; the second input of the adder 12 is connected to

50 is an output of a multiplier 14, the first input of which is combined with the input of block 15 by changing the sign of the number and is the input 5.4 of the nth TS7, and the second input of multiplier 14 is connected to the output of block 15 by changing the sign of

55 and the input of register 16, the output of register 16 is output 5.3 of the nth VL5.

Computational cell 7 with number j (j 1, p-1) contains (Fig. 3) the third input 7.1, the first input 7.2, the first output 7.3, the third output 7.4, the fourth input 7.5, the second output 7.6, second input 7.7, fourth output 7.8, multiplexers 17-19, multiplier 20, adder 21, registers 22-25 and multiplexer 26, with input 7.2 connected to the first inputs of multiplexers 17-18, the outputs of which are connected to the first inputs of multiplier 20 and adder 21 The second input of multiplexer 17 is combined with the second input of multiplexer 26 and is input 7.5 V7, and the second input of multiplexer 18 is connected to the input of constants O. The first input of multiplexer 26 is connected to the output of the multiplier 20 and the second input of the adder 21, whose output is connected to the input of register 22. The output of register 22 is output VYA7 7.3. The output of multiplexer 26 is connected to the input of register 25, the output of which is the output of 7.8 BS7. The second input of the multiplier 20 is connected to the output of multiplexer 19, the first input of which is combined with the input of register 23 and is input 7.7 BS7, and the second input of multiplexer 19 is combined with the input of register 24 and is input 7.1 VA7. The outputs of registers 23-24 are respectively outputs 7.6 and 7.4 of the BS7.

The device works as follows.

Symmetric positive definite matrix can be the only way to factorize

A (°) L.LT

(D

where L is a lower triangular matrix.

The matrix L can be represented as

... .U

(2)

where Е + л j, E - is the identity matrix; R | - the unit vector, the vector fi is determined from the first column of the matrix which is formed as follows. If the matrix A ™, i 0, p-1 is in the form

Ar, 3,

L - -, IJJ

B; AT;

where Bj is a matrix of order (n-i-1), then matrix A of order (n-i-1) is formed in accordance with the expression

a-ir

but

.(four)

The elements of the ff vector are determined from the expression

fi (j)

j

 aj aJ: V / 2

(five)

0

five

0

five

0

five

0

where is the j-th element of the first column of the matrix A (I).

Thus, the columns of the matrix L coincide with the vectors ff, i.e. T ff where and is the i-th column of the matrix L. The formation of the matrix L is performed in n iterations. At each iteration, one column vector of the matrix L is formed, and at the ith iteration (I 1, n) the i-th vector column of the matrix L is formed. Since the i-th vector column of the matrix L contains (ni + 1) distinct from zero elements, then (ni + 1) computational cell WI is involved in the formation of the elements of the i-ro vector column of the matrix L. moreover, the i-th element of the column vector forms the cell Vir, and the element with the number i + j (j 1, n-i) forms the jV-cell. The organization of the data stream at the input of the VL cell array is shown in FIG. 5. Consider the organization of the computational process at one of the iterations, for example, the first, as a result of which the first column vector of the matrix L and the matrix is formed. The device implements the conveyor information processing principle. The formation of the first vector column begins with the insertion in the microtot to the cell of the EIT cell of the element a; g of the matrix. The first parameter. equal to ay, is the calculated value of the first coordinate of the vector column 1.1 and through multiplexer 10 and pe (o)

t 1/2

histrrrrrrrrrrr is passed to cell 4

participates in the formation of the remaining coordinates of the column vector 1.1 in accordance with. expression (5). This parameter with the help of register 13 cells J5 WNP and registers 23 0 cells 7 WN (j 1, n-1) spreads across the matrix 6 cells 7 VNCParameter a ;, in micro-cycle t (to 1, item 1) enters input 7.7 of the cells 7 WN and further through multiplexer 19 to the input of the multiplier 20 cells 7 WN, 5 to the second input of the multiplier 20 at this moment

a (°) / iotn1L111.1 d ° is taught element a

 g 1.

mi matrices - 2 through adder 21

and register 22 in the next microtack will be transferred to the cell 3 ЗЯ |. The multiplexer 18 in this micro-clock (ti) connects the O code to the second input of the adder 21. The same product through the multiplexer 26 enters the input of the register 25, Thus, in cell 7 of the VY in the micro-clock ti, the information flows are switched as follows:

Multiplexer output 19 input 7.7 Multiplexer output O Multiplexer output 26 multiplexer output 19 Multiplexer output 17 "input 7.2 In the remaining micro-tacts, the second multiplexer inputs are switched to the multiplexer outputs of the VY cell. In the VNP cell 5, the square root calculating unit 9 is connected to the output of the multiplexer 10 in the micro clock cycle to. Control multiplexer cells VYA | (I 1, p) is performed using the control bits that accompany the elements of the matrices A (i).

Thus, in the first n microtacs (IK, k 0, n-C), the elements of the column vector 1.1 are formed. The elements of the matrix A 1 are formed starting with the microtac ta in columns, and only the elements of the lower triangle and the main diagonal are formed, since matrix A is symmetric. The elements of the m-ro column vector of the matrix A begin to form from the microtact of t2 (m-i), and in the j-th (j 1,) cell 7 the (J + rn) -th element of the m-ro column vector of the matrix is formed. From the expression (5) we have

A, b {o) kj-l (1) kil (o) ji,, n-1, (6), 35

where 1k1 (k 1, p) is determined from (5);

tr ° kj - elements of the matrix in the cellular representation (3).

The elements of the vector-column 1.1 involved in the calculations by formula (6) are distributed along the matrix 6 of the computational cells 7 in two directions. The conveyor formed by multiplexers 26 and registers 25 is designed to transfer the elements of the column vector 1.1 from right to the left to the cell 5. Computing cell 5 using the block 15 changing the sign of the number multiplies each element of the column vector 1.1 by -1, and the column vector elements -1.1 are sent to the computational cells 7 via a pipeline formed by the register 16, the cells 5 and the registers 24 of the cells 7. In each computational cell 7, micro-tact is performed using the multiplier 20 and the adder 21 in the computational cell. em (6).

Elements r1 ji are fed to the input of multiplier 20 of each computational cell 7 from input 7.1 through multiplexer 19, and the elements from input 7.5 through multiplexer 17. At the adder 21 of each computational cell 7, an element a is formed, which is transmitted through register 22 to the corresponding storage cell 3 A timing diagram explaining the organization of the data streams in the matrix 6 of the computational cells 7 is shown in FIG. 5 for case 4. At the remaining iterations, the processor operates in the same way. The difference is that at each subsequent iteration, the number of computational cells per unit less than at the previous iteration is included in the work (the rights of the computational cell participating in this iteration do not take part in the next iteration).

Each storage cell 3 is a dual RAM buffer which, against the background decomposition of the current matrix, loads the next matrix via bus 1 into the matrix 2 of the storage cells 3. Simultaneously with the loading of the next matrix from the matrix 2 of the storage cells 3, the elements of the L matrix obtained as a result of decomposition of the previous matrix. The output is via output 4.

Thus, by introducing into the known device an additional computational cell, new architectural solutions of computational cells combined into a matrix, and a special organization of the computational process, the functionality is expanded by solving the problem of decomposing the Cholesky symmetric matrices.

Claims (3)

Claim {. A device for matrix operations containing n − 1 computing blocks (n is the dimension of the matrices being processed) and n memory blocks, the first information input and output of the j-ro memory block (j 2, n) are connected respectively to the first output and information input of the (j - 1) -th computing unit, the second output of the i-ro (i 1, n-1) memory block is connected to the second information input (1 + 1) of the memory block, the second information input the first and second output of the nth memory block are respectively the information input and output m of the device, the second j / i third outputs to-ro memory block (1, p-2) are connected respectively to the second and third information inputs of the (C + 1) th computing unit, characterized in that, in order to expand the functional capabilities due to decomposition of Cholesky matrices, the nth computing unit is entered into it, the first information input and output of which are connected respectively to the first output and information input of the first memory block, the second and third outputs of the nth computing block are connected respectively to the second and third in ormatsionnym inputs of the first computing unit, the fourth information input of the k-th calculating unit is connected to the fourth output (K + 1) -th calculating unit, fourth output of the first computing unit - to the second data input of the n-th calculating unit. 2. The device according to claim 1, characterized by the fact that the i-th computing unit contains a multiplier, adder, four registers and four multiplexers, the first information inputs of the first and second multiplexers combined and connected to the first information input of the computing unit and the outputs of the first and second multiplexers to the first inputs of the multiplier and adder, respectively, the second information input of the first multiplexer is connected to the second information input of the third multiplexer and is the fourth information input The second input of the second multiplexer is with the device input zero, the output of the third multiplexer is connected to the information input of the first register whose output is the fourth output of the computing unit, the first information input of the third multiplexer is connected to the output of the multiplier and the second input of the adder, the output which is connected to the information input of the second register, the output of which is the first output of the computing unit, the second R the multiplier input is connected to the fourth multiplexer output, the first and second information inputs of which are connected respectively to the information the inputs of the third and fourth registers, the outputs of which are, respectively, the second and third outputs of the computing unit, the second and third information inputs of which are informational inputs of the third and fourth registers, respectively. 3. The device according to claim 1, characterized in that the nth computing unit contains a square root computing unit, a node for calculating the reciprocal of a number, three registers, a multiplier, an adder, a multiplexer, a node for changing the sign of a number, the first information input of the computing unit being connected to the first the input of the adder and the input of the square root computation node whose output is connected to the input of the calculating node of the reciprocal of the number whose output is connected to the information input of the first register; informational inputs of which are connected respectively to the outputs of the square root computing unit and the adder, the second input of which is connected to the output of the multiplier, the first input of which pogo connected to the input of the node changing the sign of the number and the information input of the third register, the output of which is the third output of the nth computational unit, the second output of which is connected to the output of the first register, the second input of the nth computational block is connected to the input of the node changing the sign and the second input of the multiplier.  " 5.1 ЈY Fig 2. .7 / G8 1.g .E is - ° 1.6 W 15 Ol «R "-. dbf-i