RU1789939C - Device for measuring phase shift angle - Google Patents

Abstract

The invention relates to electrical engineering and can be used to measure the phase angle between the mains voltage and the load current of electric networks. The goal is to expand the functionality of the device. The device comprises a rectangular pulse shaper 5, a clock generator 15, a pulse counter 16, a frequency divider 17. Comparator 7, register 18, decoder 19, digital indicator 20. This is new to the device. that it is equipped with a voltage sensor 1 and a current sensor 2, between the output terminals of which are connected two series-connected resistors 3,4, a zero-organ 6, a second comparator 8, two D-flip-flops 5 and 6 and two sign indicators of registration 11, 12, respectively, inductive and capacitive load currents in electric. ternary network, the first 13 and second 14 patterns of matches. 2 ill.

Description

The invention relates to electrical engineering and can be used to measure the phase angle between the mains voltage and the load current of electrical networks.

A device for measuring the phase shift angle is known - comprising two forms of irrigating blocks, an UNIVERSITY element,; time selector, clock. pulse generator, first and second pulse counters, first and second registers, code division unit, digital indicator, third pulse counter, comparator, frequency divider, decoder.

The above device, having high speed and accuracy of measuring the phase angle of two periodic signals when measuring the phase angle between the network voltage and the load current of electric networks, does not display the sign of reactive power in the network.

An object of the invention is to expand the functionality of a device.

This goal is achieved in that the digital phase meter containing a rectangular pulse shaper, a clock pulse generator, pulse counter, frequency divider, comparator, register, decoder, digital indicator is equipped with a voltage sensor and a current sensor loaded with two resistors, a zero-element, the second comparator, two D-flip-flops and two iconic indicators for registering. respectively the inductive and capacitive load current in the electric network, the first and second coincidence circuit: while the inputs are formed bodies of rectangular pulses are connected to the outputs of the voltage sensor, the inputs of the comparators are connected to the outputs of the current sensor, which is loaded on two resistors, the middle point of which is connected to the common inputs of the current comparators and one of the inputs of the square-wave generator, the output of which is connected to the input of zero of the organ and the third inputs of the first and second coincidence circuits, the output of the zero-organ is connected to the input of the counter zero, the synchronization inputs of the D-triggers for registering the reactive power sign in the network and through the divider frequencies with a register enable enable input; D-inputs of D-flip-flops and first inputs of the first and second matching circuits are connected to the outputs (respectively) of the comparators of the inductive and capacitive channels, respectively; significant indicators are connected to direct outputs, and the second inputs of the first and second coincidence circuits are connected to the enable input E of the clock generator, the output of which is connected to the +1 input of the pulse counter, information inputs of the register

connected to binary outputs of the counter; An n-bit digital indicator is connected to the register output through a decoder.

Comparative analysis with the prototype showed the conformity of the claimed technical solution to the Novelty criterion.

Comparison of the claimed solution with other technical solutions in the given field of technology shows that the blocks are a rectangular pulse shaper,

5 a clock generator, a pulse counter, a frequency divider, a comparator, a register, a decoder, a digital indicator are known / However, when introducing the indicated connection with other elements of the circuit in

0 the claimed device, the above blocks exhibit new properties, which leads to the expansion of the device’s functionality, therefore, the claimed technical solution meets the criterion5 Significant differences.

Figure 1 shows a block diagram of the proposed device; Fig. 2 is a timing diagram for the example of sinusoidal mains voltage and load current, illustrating the operation of the device.

The device comprises a phase voltage sensor 1, a current sensor 2 of the same phase, loaded with two resistors R 3.4, a rectangular pulse shaper

5 5, zero-organ 6. fixing the beginning of the positive half-wave of the mains voltage, comparators 7 and 8 with triggers 9 and 10 and sign indicators 11 and 12 for recording inductive and capacitive load currents in the electric network, respectively, the first 13 and second 14 three-input circuits matches, clock generator 15. summing pulse counter 16, frequency divider 17, recording

5 information in the register 18, the decoder 19 converting the output binary number of states of the pulse counter 16 into the code of a three-digit digital indicator 20 that displays the current value of the angle

0 phase shift between mains voltage and load current. Moreover, the inputs of the rectangular pulse shaper 5 are connected to the outputs of the voltage sensor 1, the inputs of the comparators 7 and 8 are connected to the outputs

5 current sensors 2. loaded on two resistors R 3 and 4, the midpoint of which is connected to the common inputs of the current comparators 7 and 8 and one of the inputs of the square-wave driver 5. the output of which is connected to the input of the zero-organ 6 and the third

the inputs of the first 13 and second 14 matching schemes, the output of the zero-fire 6 is connected to the input of the zero counter pulse 16, the synchronization inputs of D-flip-flops 7 and

8 registering the sign of reactive power in the network and through a frequency divider 15 with a write enable input for register 16; The D-inputs of the D-flip-flops 9 and 10 and the first inputs of the first 13 and second 14 matching circuits are connected to the outputs of the comparators 7 and 8, respectively, the sign indicators 11 and 12 are connected to the direct outputs, and the second inputs of the first 13 and second 14 circuits coincidence - with the inverse outputs of D-flip-flops

9 and 10 of the inductive and capacitive channels, respectively, the outputs of the first 13 and second 14 matching circuits are connected to the enable input E of the clock 15, the output of which is connected to the summing input of the pulse counter 16; the information inputs of the register 18 are connected to the binary outputs of the counter 16; three-digit digital indicator 20 through the decoder 19 is connected to the output of the register 18 ..

The device operates as follows.

When voltage sensors 1 and current 2 are turned on, the output signal of current sensors 2, detected at the moment of the beginning of the positive half-wave of the mains voltage, passes through the zero value (Fig. 2 IM.Us.Ue). is the source of the presence and sign of the phase mismatch between the mains voltage and the load current: no mismatch - the signal at the output of the sensor is zero (Fig. 2, time instants t4, ts, te, tg): there is a shortage of reactive power in the power system ( inductive mismatch) - at the above moment of time there is a signal of logic unity at the input of comparator 7 (Fig. 2, time instants to, ta); with an excess of reactive power (capacitive mismatch) - there is a signal of a logical unit - at the input of the second comparator 8 (figure 2, time te); its value within the minimum sensitivity threshold of the comparators 7 and 8 is not significant. In this case, the pulse generated by the zero-organ 6, which coincides in phase with the beginning of the passage of the positive half-wave of the mains voltage through the zero value, is fed to the synchronization inputs of triggers 9 and 10, at the D-inputs of which there is a signal of a logical unit or a logical zero from the input of the corresponding comparator: in this case, at the input of one of the comparators 7 or 8, in the absence of reactive power balance in the network, there is a signal of a logical unit for switching the threshold of the comparator and the corresponding one. a sign indicator (11 or 12) will display 5 sign of reactive power in the electric network. At the same time, with the inductive nature of the load (Fig. 2, time instants to, t2), the resolving logic levels in in the TC at all three inputs of the first

0 coincidence circuit 13, as the output of its high logic level will allow the clock generator 15 to work, from the output of which, in turn, the pulses will begin to arrive at the counter summing input

5-16, increasing its binary state until the output signal from the comparator 7 is switched to the opposite, stopping the operation of the clock generator 15 (Fig. 2, time moments -.

0 nor ti, 13), while the difference of to-ti and t2-t3 (Fig. 2) between the front of the pulse K3 and the front of the pulse u5 (Fig. 2, time instants ti, 13) will determine the time during which the pulses from a clock generator 5 pulses 15 pass to the summing input of the counter 16, increasing its binary state from 0.00 to the actual mismatch in the electric network between the mains voltage and the load current; at

0 capacitive nature of the load, allowing logical levels in TS on all three inputs of the second logical coincidence circuit 14 (Fig. 2, time te), a high logical level from the output of the element

514 will allow the operation of the generator 15; further, the operation of the device occurs similarly to that described above for the inductive nature of the load; wherein the time difference te-t (figure 2) between the slice of the pulse Us

0 and the edge of the pulse Us determines the time during which the generator 13 will generate write pulses in the counter 16, increasing its binary state. WITH

5 by the time interval determined by the frequency divider 17, the output binary number of the counter 16 is written to the register 18, displaying through the decoder 19 on the digital indicator 20 the numerical value of the angle of shift between the mains voltage and the load current in the electric network. As indicated above, the sign of reactive power is then displayed by the corresponding sign indicator 11 and 12.

5

The use of this invention will expand the functionality of a digital phase meter while measuring the angle of shear between the voltage of the mains and the load current.

Claims (1)

SUMMARY OF THE INVENTION A device for measuring a phase angle, comprising a rectangular pulse shaper, a clock pulse generator, a pulse counter, a frequency divider, a comparator, a register, information inputs connected to the information outputs of a pulse counter, a decoder, a digital indicator, characterized in that, for the purpose of expanding the functionality of the device, it is equipped with a voltage sensor and a current sensor, between the output terminals of which are connected two series-connected resistors, by a zero-organ, a second comparator, two O-flip-flops and two significant indicators of registration of the inductive and capacitive load currents in the electric network, respectively, the first and second matching circuits, while the inputs of the square-pulse generator are connected to the outputs of the voltage sensor, the inputs of the comparators are connected to the outputs current sensor, which is loaded on two resistors, the midpoint of which is connected to the common inputs of the current comparators and one of the inputs of the square pulse generator, the output of which is connected to the input of the zero-organ and the first inputs of the first and second coincidence circuits, the output of the zero-organ is connected to the installation input in the O counter, synchronization inputs D -triggers for registering a sign of reactive power in the network and through a frequency divider - with a register enable input, D-inputs of D-triggers and second inputs of the first and second matching circuits are connected to the outputs of the comparators respectively active and capacitive channels, signed indicators are connected to direct outputs, and the third inputs of the first and second matching circuits are connected to the inverse outputs of the D-flip-flops of the inductive and capacitive channels, respectively, the outputs of the first and second matching circuits are connected to the enable input of the clock generator, the output of which connected to the input + T of the pulse counter, a n-bit digital indicator through a decoder connected to the output of the register. % / at A A A A A / / / g Y V / V Y L / 7 y g yr A / L -C - ЈЈ Figure 1 Compiled by V. Butko Editor G. Belska Tehred M. Morgenthal Proofreader M. Keretsman Order 348 Circulation Subscription VNIIIPI of the State Committee for Inventions and Discover at the State Committee for Science and Technology of the USSR 113035. Moscow, Zh-35, Rauska nab., 4/5 /  Г4 «о + У - - # У