RU1787818C - Clutch actuator - Google Patents

Abstract

Usage: relates to automotive engineering and can be used in systems designed to control clutches. SUMMARY OF THE INVENTION: when a clutch is turned off, initially a series of zero values of the sensor state enters the system, during further reading of information, an initial single impulse enters the system, which corresponds to the start of an on-cycle. In this case, the comparison unit gives a signal to control the right channel of the amplifier, which supplies the switching current to the corresponding solenoid of the modulator, and the inlet electro-pneumatic valve switches to the open state, air from the receiver enters the pressure regulator, from where it enters the actuator through the inlet electro-pneumatic valve, which corresponds to the process of engaging the clutch. At the next point in time, when reading the code corresponding to a single pulse from the sensor, the solenoids are de-energized, the air flow and the clutch engagement cycle are completed. During the engagement of the clutch, the engagement cycle is repeated many times. 5 ill.

Description

The invention relates to automotive tractor construction, road construction equipment and can be used in systems designed to control clutches.

A device for controlling the clutch of a vehicle is known, comprising an amplifier pneumatic cylinder, a control valve, an actuating hydraulic cylinder with a head, a cylinder and a pedal. The presence of two energy carriers in the form of the pneumatic and hydraulic parts of the drive, as well as the interface between them, determines the structural complexity of the drive.

Closer in technical performance is a vehicle clutch control pneumatic actuator comprising a pedal, links, auxiliary cylinder levers, a pneumatic actuator, pneumatic booster valve. The disadvantage of this actuator is the considerable length of mechanical remote control, which reduces the quality of control.

The aim of the invention is to increase the response time of the clutch actuator, facilitate clutch control, ensure smooth starting and smooth gear changes.

This goal is achieved by the fact that the clutch actuator is equipped with a pedal position sensor electrically connected to a digital switchgear, which, through two electric channels and a series-connected two-channel amplifier, is connected to electromagnets electrically XI 00 h C

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the inlet and outlet valve of the modulator, the output pneumatic channel of the inlet electro-pneumatic valve and the inlet pneumatic channel of the electro-pneumatic discharge valve are connected to each other and with the executive pneumatic cylinder, the pressure reducer is connected to the inlet pneumatic channel of the electro-pneumatic valve at the start-up, and the outlet pneumatic channel of the electro-pneumatic exhaust valve is connected dinen with atmosphere.

The actuator actuator - the modulator - is compact, which allows it to be installed directly from the top cover of the actuator cylinder, which increases the speed of the drive as a whole. The absence of mechanical rods and levers in the drive reduces the effort on the clutch control pedals, which facilitates clutch control, and by implementing the optimal control law, it is possible to significantly increase the smoothness of starting and shifting gears.

The operation of the digital switchgear is illustrated in the table.

In FIG. 1 shows a drive circuit of a clutch with modulators and a digital switchgear; in FIG. 2 is a diagram of the operation algorithm of a digital switchgear; in FIG. 3 - clutch control actuator; on Fig, 4 - diagram and characteristics of the signals at the output of the individual sides of the system; in FIG. 5 is a structural and functional diagram of a digital switchgear.

The clutch drive consists of a pedal 1, a pedal position sensor 2, a digital switchgear 3, a two-channel amplifier 4, a modulator 5, an actuator cylinder 6, and a pressure reducer 7,

The encoder pedal position sensor 2 is designed to convert the angle of rotation of the pedal 1 to a discrete encoded signal. It is possible to use the pedal position sensor 2 of an analog type together with an analog-digital converter, On the shaft 8, the angular movement of which is converted into a digital code and on which the axis of the pedal 1 is located, a coded disk 9 is rigidly fixed. This disk is a glass base on which is applied a code mask formed by a certain number of concentric code tracks with segments transparent and opaque to the light flux. The illuminator, consisting of a lamp 10 and a capacitor 11, is designed to form a luminous flux passing through the transparent segments of the code tracks of the disk and the diaphragm 12. In addition, it is intended to illuminate the photodetectors 13. As a result, each corner of the pedal 1 corresponds to a certain combination of units and zeros, which are the digital code of the given angle, and the angular speed of the pedal 1 is converted accordingly to the repetition rate of the encoded signal.

Block 14 is designed to read information from the position sensor of the pedal 2 and convert it to the appropriate number of pulses, and block 15 is designed to select from the memory the input converted information recorded in the previous step of the cycle. Logic block 16 is a unit for comparing the current and previous state of blocks 14 and 15. Control units

17 and 18 are used to supply an amplifier start signal, block 19 is used to disable the input signals of amplifier 4. Control units 17, 18, and 19 are connected at the input to comparison unit 16. Block 20 is used to record the current state of the input action and is connected to the outputs blocks 17,

18 and 19.

Modulator 5 consists of two two-position, two-line solenoid valves for intake and exhaust 21, 22, which are in the closed position with deenergized solenoids, and in the open state when the switching current is applied, and to reduce the inertia of the actuator, the throttling of valves 21 and 22 open position should be minimal.

The drive is mounted on a friction clutch 23 with a pneumatic actuator 1 cylinder b, a pressure reducer 7 and a receiver 24.

Block 3 consists of an input matching device 25, a central processor 26, an output matching device 27 of the left channel, an output matching device 28 of the right channel, a clock generator 29, a storage device 30.

The input matching device 26 is made in the form of a voltage divider with two resistances 31. The central processor 26 is a microprocessor single-chip, eight-bit LSI KP580VM80 (analog of Intel 8080A), made by p-MOS technology, the input and output signals correspond level of operation of TTL circuits and consists of an arithmetic logic device 32, an accumulator 33, a buffer of an accumulator 34, a buffer register 35, a register of attributes 36, an instruction register 37, an instruction decoder 38, general purpose registers 39, the device systematic way 40, input port 41, output port 42 of the left channel, the right channel output port 43, the data bus 44. The clock frequency of the digital switchboard 3 is 1 MHz.

The functional purpose of the elements of the central processor is as follows:

arithmetic logic device 32 is used to perform logical operations comparing the contents of the buffer of the accumulator 34 and the buffer register 35 under the influence of the control device 40;

the accumulator buffer is intended for storing a data word sent to it from the output port of the arithmetic logic unit 32. The accumulator buffer 34 stores the result of the operation of the alphanumeric device 32 at the current step or microcycle. Moreover, the result of the operation of the alphanumeric device 32 in the previous step or microcycle is erased;

feature register 36 has five bits: carry bit, additional carry tag, sign bit, zero bit bit, parity bit bit. The null flag bit is discarded if the result of the operations of the alphanumeric device 32 located in the battery buffer is zero. If the result is non-zero, the bit of the null flag is set to one. The remaining bits are used as an indicator for checking the operation of the arithmetic logic device 32;

input port 41 constantly contains the current code of sensor 2 regardless of the operation of the alphanumeric device 32;

a control device 40 is used to set the instruction register 37, the instruction decoder 38 (the instructions of which are previously read into the storage device 30) in the implementation mode of the algorithm;

data bus 44 is designed to provide forwarding, shifting the contents of registers.

The output matching device 27 of the left and right 28 channels are structurally made in one housing of the TTL K1501UD2A series microcircuit. The supply voltage of this microcircuit is + 15V and is intended for load balancing of the two-channel amplifier 4 and the output ports of the left channel 42, the output port of the right channel 43.

The clock generator 29 contains a master oscillator circuit, the frequency of the generated oscillations with an amplitude of 12 V, which is stabilized by a quartz resonator. It is possible to use adjustable quartz K531GP. The timing of the output clock pulses is 1/9 of the pulse repetition period of the master oscillator and is 1 µs. The clock generator is made on BIS KR580GF24.

The storage device 30 can be performed on a chip KR565RU2 having a capacity of 1024 bits. In order to increase the volume of the storage device 30, it is possible to use an additional address decoder. Previously, a program is implemented in the memory 30, which implements the step-by-step execution of the operation algorithm of the digital switchgear 3.

The clutch actuator operates as follows.

The pressure reducer 7 is adjusted to the pressure of the complete disengagement of the clutch. Digital switchgear 3 (Fig. 1) provides a start signal for the left or right channel of amplifier 4 depending on the digital input from the pedal position sensor

2 and is a procedural logical memory device, the operation of which can be described in the form of the algorithm shown in FIG. 2. Block 14 implements a push-pull reading of information from the position sensor of pedal 2 and converts it to the corresponding number of pulses, and block 15 selects from the memory the input converted information recorded in the previous step of the cycle. After that, the logical block 16 compares the current and previous state of the blocks 14 and 15 and, in the case of a positive increment, transfers control to the block 17, which supplies the start signal to the right channel of the amplifier 4, which is known, the negative signal to the block 18, the start signal is sent to the left channel. and if the increment is zero, control is given to block 19, which turns off the input signals of amplifier 4. The last step in the operation of digital switchgear 3 is to record the current state of the input effect by block 20.

Modulator 5 is an interface device that converts the electrical signal supplied from a two-channel amplifier 4 of a digital switchgear

3 at the expense of the working fluid, which in its

the turn determines the movement of the rod of the actuating cylinder 6 with a predetermined discreteness determined by the choice of parameters and the method of modulating the working fluid. Modulator 5 implements a control algorithm for digital switchgear 3.

This invention contemplates pulse frequency modulation, and compressed air as a working fluid.

From the sensor 2 is supplied to the input matching device 25 corresponding to a certain position of the pedal 1 code. At the output of the matching device 25, the level of the output signal is converted to the magnitude of the operation of the TTL circuits. Next, the digital code enters the input port 41. Thus, the input port 41 constantly reflects the information of the sensor 2.

The clock generator 29 supplies a pulse to the control device 40, which sets the instruction register 37 and the command decoder 38 to the program implementation mode of the first step of the algorithm previously read into the storage device 30: reading the information of the pedal position transmitter 2, loading the buffer register 35 using data bus 44 contents of input port 41,

The next pulse of the clock generator 29 is supplied to the control device 40, which sets the instruction register 37 and the command decoder 38 to the program implementation mode of the second step of the algorithm: selecting from the memory the input converted information recorded in the previous step of the cycle. Here, the contents of the battery 33 are shifted to the buffer of the battery 34.

Further operation of the clock generator 29 generates a pulse arriving at the control device 40, which sets the instruction register 37 and the instruction decoder 38 to the software implementation mode of the third step of the algorithm: comparing the current and previous steps of the algorithm. Here, the contents of the buffer register 35 and the buffer of the accumulator 34 are compared logically by an alphanumeric device 32. In this case, if the contents of the buffer register 35 and the buffer of accumulator 34 are the same (zero increment), the bit of the null flag of the sign register 36 is reset to zero, occurs with using the data bus 44, move the null-sign bit to general registers B and W 39, and then transfer the contents of general registers B and W 39 to the output port of the left channel 42 and the output port of the right channel 43. Including In the case, if the contents of the buffer register 35 are larger than the buffer of the accumulator 34 (positive increment), the bit of the zero sign of the register of signs 36 is set to one, occurs using the data bus 44 to move the bit of the zero sign to the general register W

0 39, followed by the transfer of the contents of the general register to the output port 43 of the right channel. If the contents of the buffer register 35 is less than the buffer of the accumulator 34 (negative

5 increment), the null sign bit of the sign register 36 is set to one, using the data bus 44, the null sign bit is transferred to the general purpose register B 39 and then the contents of the general register are transferred to the left channel output port 42. In all cases, the result of the operation of the alphanumeric device is placed in the buffer of the accumulator 34 at this step.

5 The subsequent pulse of the clock generator 29 is supplied to the control device 40, which sets the command register 37 and the command decoder 38 in the software implementation mode of the last step

0 algorithm: record the current state of the input action. The contents of the buffer register 35 are shifted to the accumulator 33 with the subsequent reset of the instruction register 37, the instruction decoder 38

5 to zero. This means that the next pulse of the clock will start the first step of the algorithm. In this case, the contents of the battery 33 in the previous step are erased.

0 Thus, the reading of information from the position sensor of the pedal 2 is carried out by loading the buffer register 35, the selection from the memory of the input converted information recorded

5 in the previous step of the cycle - for

by shifting the contents of the battery 33 in

accumulator buffer 34, current comparison

- and the previous steps of the algorithm - for

the operation of the alphanumeric device 32, the recording of the current state of the input action due to the shift of the containing buffer register 35 into the accumulator 33.

The digital switchgear 5 in 3 transfers the control port of the output of the right channel 43 and the output matching matching device 28 of the right channel with a positive increment of the input information, with a negative increment - the output port of the left channel 42 and

the left channel output matching device 27, and if the increment is zero, it resets the output channel of the right channel 43 and the output port of the left channel 42 to zero and de-energizes the output matching device 27 of the left channel and the output matching device 28 of the right channel (see table) ,

At any position of the pedal 1, information is read from the sensor 2 at times determined by the frequency fg of the clock of the digital switchgear 3. Moreover, the frequency of the clock generator is selected sufficiently large and its value should ensure the transition from one state of the output channels of the digital switchgear 3 to the other only through zero, or through unity, thereby determining the difference between the read and previous values, either zero or one at maximum second moving speed pedal 1.

When the clutch pedal 1 is completely released, the sensor housing 2 and the shaft 8 are relative to each other so that in this position of the pedal 1 the number of sensor 2 codes is zero. Since the previous recorded value of the number of pulses is also equal to zero, the comparison unit 16 does not give signals to the amplifier channel inputs. The solenoids of the modulator 5 are in a de-energized state, which corresponds to the initial position of the actuating cylinder 6, i.e. clutch 23 is fully engaged.

When pedal 1 is pressed, initially in the time interval ti ... t3 a series of zero values of the state of sensor 2 are received, and their number is determined by the ratio of the speed of pressing the pedal 1 and the frequency fr of the clock generator (at maximum speed of pedal 1, the series consists of from one zero value).

In the process of further reading of information at the pedal position, for example, OA at time t.4, the system starts with an initial unit pulse NI, which corresponds to the start of the shutdown cycle. Moreover, since the previous value of the sensor state was zero, the comparison unit 16 provides a signal for controlling the right channel of the amplifier, which in turn supplies the switching current to the corresponding solenoid of the modulator 5. The state of the solenoid of the intake valve 22 is 1. In this case air from receiver 24 enters pressure regulator 7. from where through

inlet electropneumatic valve 22, which switches to the open position, into the actuating cylinder 6, the rod of which begins to move, which corresponds

the process of turning off the coupling 23. At the next time ts, when reading the code corresponding to a single pulse from the pedal position sensor 2 in accordance with the operation of the digital switchgear 3 algorithm, the solenoids are de-energized (the state of electromagnet electromagnet valves 21 and 22 - O), the air flow rate, and therefore, the movement of the rod of the actuator cylinder 5 is stopped. At this point, the clutch disengagement cycle 23 ends. During the continuous movement of the pedal 1, the shutdown cycle is repeated many times.

0 Thus, the movement of the pedal 1 even at a high speed of movement is perceived by the digital switchgear 3 as the alternation of a set of zeros and ones on the output channels,

5 which in turn for the modulator 5 corresponds to the deenergized and switched-on states of the solenoids.

When pedal 1 is released, a negative increment of pulses is created, according to the operation of the algorithm, a start-up cycle is started, a turn-on current is supplied to the solenoid of the electro-pneumatic valve of exhaust 21. In the rest, the process of engaging the clutch 5 is carried out similarly to the turn-off process.

When the pedal 1 is stopped in some intermediate or extreme position with constant beat reading in

0 the system receives a series of the same number of codes, then converted to the corresponding number of pulses having a zero increment, which corresponds to the de-energized state of the solenoids 5 of the modulator 5, i.e. the rod of the actuating cylinder 6 remains stationary in some kind of intermediate or. extreme position.

Thus, the drive of the clutch 23 performs the following action with respect to the position and speed of changing the position of the pedal 1, while in accordance with FIG. 5 a certain amount of displacement S (t) for a certain period of time t of the pedal

5 1 corresponds to a certain number of codes N (t), the digital switchgear 3 in turn generates a certain number of cycles of the state of the left gpl (t) inlet and the right mn (t) (outlet) of channels that are implemented by the modulator

5 to the corresponding flow rate of the working fluid Q (t), which corresponds to a certain stroke of the rod h (t) of the actuating cylinder 6 for the same period of time.

It is advisable to use this drive in clutch control systems in the case of installing a switchgear near the driver’s pedal, while reducing the length of the supply and power lines, thereby increasing speed, facilitating clutch control, and ensuring smooth starting and shifting gears.

The drive under consideration was tested using BOSCH valves and showed satisfactory performance. Work on its improvement is underway.

Claims (1)

Claims Clutch actuator comprising pedal, pressure reducer, pneumatic actuator, electric 5 0 electro-pneumatic valve strings, a digital switchgear, characterized in that, in order to increase the response of the clutch actuator, to ensure smooth starting and smooth gear shifting, the clutch actuator is equipped with a pedal position sensor electrically connected to the digital switchgear; which, through two electric channels and a two-channel amplifier connected in series with it, is connected to the electromagnet electromagnetics inlet and outlet electromagnet electromagnets, the output pneumatic duct of the inlet electropneumatic valve and the pneumatic inlet channel of the exhaust electropneumatic valve connected to each other and to the actuating pneumatic cylinder, the pressure reducer is connected the inlet pneumatic channel of the inlet electro-pneumatic valve, and the output pneumatic channel of the outlet electro-pneumatic valve is connected to the atmosphere. "./. F fffrr tl 9 h