RU1786669C - Device for transmission and receiving discrete messages - Google Patents

Abstract

The invention relates to communication technology and can be used to transmit discrete messages in wired, radio, radio relay and space communication lines. The purpose of the invention is to improve the noise immunity of communication. The system for transmitting and receiving discrete messages comprises, on the transmitting side, an information source 1, a shift register 2. a channel modulator 3, a transmitter. synchronization unit 5, sequence generator 6, switch 7, adder 8 modulo two, key 9, and on the receiving side, receiver 10, demodulator 11, character generator 12, switch 13, error detection and correction unit 14, which includes an input t shift register 15, adder 16 modulo two and key 17, channel demodulator 18, first character generator 19, first drive 20, subtracter 21, second character generator 22, second drive 23, clock 24, driver 25 clock pulses, first delay line 26. per first minimum selection unit 27. The key 28, a storage unit 29, decoder 30, the second delay line 31, the second minimum selection unit 32, a delay element 33. The communication link 34 2 yl. ate with

Description

The invention relates to electrical and radio communications and can be used in wired, radio, radio relay and space communication lines.

A device is known for transmitting and receiving discrete messages, comprising on the transmitting side a series-connected information source, a channel modulator, a transmitter, a sync block and a sequence generator, and on the receiving side, a series-connected receiver, a channel demodulator and a channel symbol former and a sync block; The transmitting and receiving sides of the device are connected via a communication line.

However, such a device does not allow the transmission of additional information and has a low noise immunity of communication.

Closest to the claimed device is a device for transmitting and receiving discrete messages, including on the front side a series-connected information source, a channel modulator, a transmitter, a sync block, a sequence generator and a switch, and an information source whose output is connected with the control input of the switch, the first output of the sync block is connected to the input of the information source, and the second is connected to the input of the information source and the sync input of the transmitter, and on the receiving side, the last The receiver, the first channel demodulator and the character generator, the switch, the second channel demodulator and the character generator connected in series, the first drive, the subtracting device and the third character driver, the output of which is connected to the control input of the switch, the second drive, connected in series a sync block and a shaper of clock pulses, connected in series with a shaper of characters, the first shift register, and sequentially with the second shaper of characters - the second shift register, and the clock inputs of both registers are combined with the clock inputs of the channel demodulators, drives and connected to the outputs of the driver of the clock pulses, the outputs of the first and second registers are connected to the corresponding signal input of the switch, the input of the second channel demodulator is connected to the output the receiver, and its output is connected to the input of the second drive, the output of which is connected to the second signal

the input of the subtractor, the output of the first channel demodulator is connected to the input of the first drive, the input of the sync block is connected to the clock output of the receiver, and 5 its output is connected to the sync input of the subtractor; The receiving and transmitting sides of the device are interconnected via a communication line.

However, such a device has a low

10 noise immunity of communication.

The purpose of the invention is to improve the noise immunity of communication.

In order to achieve this goal, a shift register, an adder modulo two, and a key are introduced into the device for transmitting and receiving discrete messages on the transmitting side, the input of the shift register being connected to the output of the information source, and its

0 output - with the information input of the channel modulator, the key output is connected to the control input of the switch, the clock inputs of the shift register and key are connected respectively to the first and second

5. The outputs of the sync block, and on the receiving side, a series-connected adder modulo two and a second key are introduced, combined with a shift register in an error detection and correction unit, wherein the first group of inputs of the second key is connected to the inverse outputs of the first bits of the register, the second group its inputs combined;) with the first information inputs of the adder modulo

5 two and with direct outputs To the first bits of the register, and its outputs connected to the installation inputs To the first bits of the register, the input of the register, its clock input, (K + 1) -th information input of the adder modulo two and its control the input input and the signal inputs of the second key are, respectively, the first information, clock, second information, control and signal inputs of the error detection and correction unit, and the information of the shift register is the output of the device, serially connected first lines delays, the first block selects a minimum of 0, the first key, a memory and a decoder, a second delay line and a block for selecting a minimum, and a delay element, and the outputs of the first and second channel demodulators are connected5 respectively to the inputs of the first and second delay lines, the outputs of which connected respectively to the inputs of the first and second symbol formers, the outputs of the second minimum selection block are connected to the second group of inputs of the first

the key, the outputs of the first and second symbol formers are connected to the corresponding signal inputs of the switch, the output of which is connected to the first information input of the error detection and correction unit, the output of the delay element is connected to the control input of the error detection and correction unit, the signal inputs of which are connected to the outputs of the decoder, and the second information input is combined with the control input of the first key and connected to the output of the third character generator, clock inputs of the memory, the first and second lines and delay units choosing the minimum delay element and the block error detection and correction are connected to the output of the clock, the delay element input coupled to the output of a sync.

The main distinguishing features of the proposed device in comparison with the prototype is the presence of a shift register, an adder modulo two, and a key with corresponding communications on the transmitting side and two delay lines, minimum selection blocks and keys. Memory a decoder, an adder modulo two, and a delay element with corresponding communications on the receiving side.

The use of these units with appropriate communications to improve the noise immunity of communications is not a known technical solution. Thus, the proposed technical solution satisfies the criterion of significant differences.

The invention is illustrated in FIG. 1 and 2.

In FIG. 1 is a structural electrical diagram of a device for transmitting and receiving discrete messages.

The device for transmitting and receiving discrete messages contains on the transmitting side a series-connected information source 1, shift register 2, channel modulator 3. transmitter 4. sync block 5, sequence generator 6 and switch 7, the outputs of which are connected to the signal inputs of the channel modulator 3, series-connected adder 8 modulo two, the inputs of which are connected to the outputs of block 2. and a key 5, the output of which is connected to the control input of the switch 7. clock inputs of the information source 1 and register 2 the shift connected to the first output of the sync block 5, the second output of which is connected to the clock inputs of the key 9 and the transmitter 4, and on the receiving side contains a receiver 10. the first channel demodulator 11. sequentially

connected by the first character driver 12, the switch 13 and the error detection and correction unit 14, consisting of a shift register 15, an adder 1 b modulo

two and a second key 17, and the first group of inputs of the second key 17 is connected to the inverse outputs K of the first bits of the shift register 15, the second group of its inputs is combined with the K first information inputs of the adder 16 modulo two and with direct outputs of the first bits register 15, and its outputs are connected to the installation inputs K of the first bits, the input of register 15, its clock input, (K + 1)

5, the information input of block 16 and its control input, and the signal inputs of the second key 17 are, respectively, the first information, clock, second information, control, and signal inputs of the error detection and correction flea 14, and the information output of register 15 is the output of the device, a second channel demodulator 18, a second character driver 19, sequentially connected a first drive 20, a subtractor 21 and a third character driver 22, a second drive 23, connected in series with the hroblock 24 and the driver 25 sync pulses, serially connected to the first delay line 26, the first block 27 minimum selection, the first key 28, a storage device (memory) 29 and a decoder 30 connected in series to the second

5, the delay line 31 and the minimum selection unit 32, the outputs of which are connected to the second group of inputs of the key 28, and the delay element 33, the information output of the receiver 10 being connected to the inputs of the first

0 and the second channel demodulators 11 and 18, and its sync output is with the input of the sync block 24, the outputs of the channel demodulators 11 and 18 are connected respectively to the inputs of drives 20 and 23 and to the inputs of lines 26 and 31

5 delays, the outputs of which are connected respectively to the inputs of the first and second shapers 12 and 19 characters, the output of the shaper 19 characters connected to the second signal input of the switch 13,

0, the signal inputs of the error detection and correction unit 14 are connected to the outputs of the decoder 30, its control input is connected to the output of the delay element 33, the clock is connected to the output of the driver 25 syn5 clock pulses, and the second information signal is connected to the output of the third driver 22 symbols, the clock inputs of the first and second channel demodulators 11 and 18, delay lines 26 and 31, minimum selection blocks 27 and 32, drives 20 and 23. (memory) 29 and delay element 33 are connected to the output of the clock driver 25, the output of the clock 24 is connected to the clock input itayuschego device 21 and input to the delay element 33, a third output for- tors, 22 symbols connected kuprav- l yuschim inputs of switch 13 and the first key 28; the receiving and transmitting sides of the device are connected via a communication line 34.

A device for transmitting and receiving discrete messages operates as follows.

On the transmitting side, information symbols of the binary source 1 of information of duration T (Fig. 2a), determined by the repetition period of the output pulses of frequency F, acting on the first output of the sync block 5 (Fig. 26) and obtained by dividing the carrier frequency of the transmitter 4, are presented in the form of packets consisting of K symbols (K., for example, of symbols (Fig. 2a), and are transmitted to a “-bit register 2 of shift, and after a delay in it (Fig. 2c), to the input of the channel modulator 3. The output symbols of the adder 8, the inputs of which are connected to the outputs of the bit Register 2, at times determined by pulses with a frequency F / K acting on the second output of the sync block 5 (Fig. 2d), are transmitted to the input of the switch 7 by the key 9 (Fig. 2e). Depending on the value of the symbol at the input one of two pairs of opposite (orthogonal, etc.) sequences transmitted to its inputs from generator 6 is transmitted to its output switch. In channel modulator 3, depending on the value of the input information symbol, one of this pair is transmitted to its output signals, which then goes to transmitter input 4. Ei as a result, information on transmitted symbols of source 1 with frequency F and additional information on the evenness or oddness of the number of symbols 1 in the symbol packet with frequency F / K are entered into the output signal of block 3 (Fig. 2d). In transmitter 4, the signal is amplified, converted to the desired frequency range, mixed with synchronization signals, and transmitted over communication line 35.

On the receiving side, after general filtering in the receiver 10, the signal is fed to the inputs of two channel demodulators 11 and 18, matched with different ensembles (pairs) of signals used during transmission, in each of which at the moments of action of short pulses generated in the driver clock pulses 25, which have a period T and coincide in

time with the moments of the end of the information symbols at reception (Fig. 26), signals of certain levels and polarities are formed (Fig. 2e). These signals are delayed in blocks 26 and 31 (analog or discrete-analog delay lines) for the time interval 3T (Fig. 2g) and are fed to the inputs of the drivers 12 and 19 of the symbol, in which the symbol 1 or O is generated independently for each channel ( Fig. 2h). Symbols obtained on a time interval equal to KT. in the absence of interference, they coincide with those transmitted from source 1 only at the output of one of blocks 12 or 19. This depends on the value of the additional information symbol transmitted on the same time interval. In order to extract this information, the absolute values of the output signals of blocks 11 and 18 are multiplied at time instants that are multiples of the interval T in accumulators 20 and 23. Based on the results of comparing the signal levels obtained at the outputs of blocks 20 and 23 at time instants KT; which are determined by the short output pulses of the sync block 24, in block 21 decisions are made to receive additional information symbols, and in block 22, their values are 1 or O (Fig. 2i). Depending on this, the output symbols of block 12 or 19 are transmitted to the output of the switch.

Blocks 14, as well as 26-33, are designed to analyze, detect, and correct single errors arising from the action of interference at the output of switch 13.

The analysis, detection and correction of errors is carried out as follows. The output symbols of the switch 13 are supplied to the (K + 1) -bit shift register 15. The direct outputs of its first K bits are connected to the corresponding information inputs of the adder 15 modulo two, the last (K-I) -th information input of which receives a symbol of additional information from the output of block 22. If the number of characters is 1 on all its inputs at the moment the action of the negative edge of the pulse at the output of block 33 (Fig. 2k) is odd, then a pulse is generated at its output (input of key 17), indicating that there is an error in demodulating a burst consisting of K symbols. At the time of each clock pulse (Fig. 26), the minimum selection block 27 (32) selects the smallest (in absolute level) of the K signals operating at adjacent clock intervals (for example, i-ro signal,, 2, .. .TO). room

this signal is stored for a time equal to 3T (Fig. 2l), and a signal is generated in the decoder on one of the total number of K outputs, which, through the key 17 containing K channels, changes the state of the i-bit of register 14 to the opposite one. On the bus register 15 - a key 17 containing K channels, the first group of inputs of the key 17 receives information from the inverse outputs of the first bits of the register, and the second group of inputs of the key 17 receives information from the direct outputs of the same bits of the register 15. Received at the output of register 15, the symbols (Fig. 2m) are the output signal of the device.

Thus, the use of the proposed device for transmitting and receiving discrete messages can improve the noise immunity of communication.

Claims (1)

SUMMARY OF THE INVENTION A device for transmitting and receiving discrete messages, comprising, on a transmitting side, an information source, a channel modulator and a transmitter connected in series, the output of which is connected to an input of a clock unit, the first output of which is connected to the clock inputs of an information source and a sequence generator, the outputs of which are connected to the corresponding inputs of the switch, the second output of the sync block is connected to the corresponding input of the transmitter, and on the receiving side it is connected in series e receiver and a first channel demodulator, the input of which is connected to the input of the second channel demodulator, the first and second character mappers, a switch, the clock output of the receiver through a series-connected sync block and a clock generator is connected to the inputs of the first and second channel demodulators, and the first and second drives, the inputs of which are connected respectively to the outputs of the first and second channel demodulators, and the outputs of the first and second drives through series-connected the subtracting unit and the third character generator are connected to the control input of the switch, and the output of the sync block is connected to the clock input of the subtracting unit, characterized in that, in order to increase noise immunity, the shift register is connected in series between the output of the information source and the control input of the switch , an adder modulo two and a key, to the other input of which is connected the second output of the sync block, the first output of which is connected to the clock input of the shift register, and at the receiving station Rhone the first delay line, the first minimum selection block, the key, the storage unit and the decoder, the second delay line and the second block connected in series are introduced the minimum selection, as well as the delay element and the unit for detecting and correcting errors, while the outputs of the first and second channel demodulators are connected respectively to the first and second shapers of characters through the corresponding first and second delay lines, the outputs of the second minimum selection block are connected to the corresponding inputs of the key, the outputs of the first and second symbol formers are connected through the switch to the first information input of the error detection and correction unit, the control input of which is connected to the output ohm of the delay element, the signal inputs of the error detection and correction unit are connected to the corresponding outputs of the decoder, and the second information input of the error detection and correction unit is connected to the control input the key and the output of the third character driver, the output of the driver is connected to the clock inputs of the storage unit, the first and second delay lines, the first and second selection blocks a minimum, an error detection and correction unit, and a delay element, to the other input of which a sync block output is connected. I and about t "Mr. JULJLJLJ1 JI. D And II If II P IT I II.  Gt a | 4 | 5 | 6 I 7 I a | 9 | 10 Otc 12 545 670 9 40 o and n n ooii o. by 1 234 567  - P -flOPIP P - at  ii ii ii n 1 FIG. 2 P | 2 | 5 | T516T