RU1782336C - Duplex data transmission system with time-division multiplex - Google Patents

Abstract

The invention relates to time division data transmission systems and can be used in telecommunications. Summary of the invention: the system consists of a main terminal, consisting of a generator 1, containing an output register 2, a switch 3 and the first and second I Lr№Jr | and, with 9 Fig. 1, request signal generators 4 and 5, synchronization unit 6, interface unit 7, response signal detection unit 8 and signal selector 9, containing trigger 10 and input register 11. and a peripheral terminal containing interface unit 12, unit distinguishing the request signals 13, a synchronization unit 14, consisting of three single vibrators 15, 16 and 17, a cyclical signal extraction unit 18, a generator 19, consisting of an output register 20, a resolution block 21 and a response signal generator 22, and a signal selector 23; consisting of a discrimination unit request signals 24, delay unit 25 and two registers 26 and 27. 1-7-8-9,1-6-8,2-3-4-5,8-9, 12-19-14-23,12- 13-15-23, 20-21-22, 15-16-17. 24-25-26-27. 8 ill. Ё 00 hO 00 с о CJ

Description

The invention relates to electrical communication technology and can be used for two-way data transmission via a two-wire line, for example, for transmitting control information between a switching center and subscriber units.

Duplex signaling devices are known. However, these devices are characterized by insufficient noise immunity.

The closest in technical essence is a device, taken as a prototype, containing a main terminal consisting of a signal generator, a synchronization unit, a transceiver (interface unit), a prohibition and discriminator unit, as well as a peripheral terminal consisting of a transceiver ( interfacing unit), prohibition unit, discriminator, synchronizing pulse extraction unit, synchronization unit and generator, and is intended for two-way duplex communication. The signal from the peripheral terminal is controlled by a clock signal extracted from the signal sent from the main terminal. This device also has a low noise immunity. Protection from line interference is not sufficient if the line is long enough and data is transmitted by low-level pulses. In addition, insufficient protection against failures caused by transients in the peripheral terminal during the formation of response pulses.

The aim of the invention is to increase the noise immunity.

The essence of the invention lies in the fact that in a time-division duplex data transmission system comprising a main terminal consisting of a generator, a discriminator, a synchronization unit, an interface unit, a response signal detection unit, the generator output being connected to the input of the interface unit, the output of which is connected to the communication line, and the output of the interface unit is connected to the first input of the response signal detection unit, the first output of the synchronization unit is connected to its second input, and the output of the detection unit the response signal is connected to the first input of the discriminator, the second input of which is connected to the second output of the synchronization unit, the third output of which is connected to the generator, and a peripheral terminal consisting of a generator, discriminator, synchronization unit, and the interface unit;

a request signal detecting unit, the generator output being connected to the input of the interface unit, the output of which is connected to the communication line, and the output to the first

input of the request signal detection unit, the first output of the synchronization unit is connected to the first input of the generator, in the main terminal the generator contains an output register, a switch, two generators of request signals, the discriminator contains a RS-trigger and an input register connected in series, the response signal detection unit contains a series-connected detector,

5 a drive and a comparator and a key, a loop signal extraction unit is inserted in the peripheral terminal, the generator contains a series-connected output register, a permission unit and a generator

0 response signals, the discriminator contains a series-connected unit for distinguishing request signals, a delay line, two input registers, the synchronization unit is made in series

5 of three connected one-shots, the request signal detection unit is configured in the same way as the response signal detection unit. In the main terminal, the output register input is connected to the third output

0 synchronization unit, the output of the output register is connected to the first input of the switch, the second and third inputs of which are connected respectively to the outputs of the first and second generators of 5 interrogating signals, the inputs of which are connected respectively to the fourth output of the synchronization unit, and the output of the switch is connected to the input of the circuit pairing, the first input of the RS-flip-flop is connected to the output of the response signal detection unit, the second input is connected to the first output of the synchronization unit, and the clock input of the input register is connected to the second by the output of the synchronization block, in the block for detecting the response signal, the key output is connected to the second input of the drive, the input of the detector is connected to the output of the interface unit, the output of the comparator is connected to the first input of the RS trigger, and the key input is connected to the first output of the synchronization block, key outputs and drive connected to ground. In the peripheral terminal, the output of the response signal generator is connected to the input of the interface unit, the clock input of the first discriminator register 5 is connected to the second input of the request signal discrimination unit, the first input of which is connected to the output of the interface unit, the output of the loop signal extraction unit is connected to the gate input of the second input register and with the gate input of the output register. The output of the last one-shot of the synchronization unit is connected to the second input of the resolution unit, and the output of the first one-shot is connected to the second input of the request signal discrimination unit, with the input of the loop signal extraction unit, with the clock input of the output register, with the second input of the request signal detection unit, the output of which is connected to the input of the first one-shot.

The difference of the proposed system is in the form of executing generators and discriminators in both terminals, a response signal detecting unit in the main one, a synchronization unit and a request signal detecting unit in peripheral terminals and introducing a loop signal extraction unit into the last one, which together provides interconnected and consistent operation of the terminals and reduces the likelihood of false reception and transmission of signals from generators. When conducting patent research, the applicant did not find systems having similar distinctive features of the claimed device. All this allows us to judge the significance of the differences in the proposed system.

In FIG. 1 shows a structural diagram of the proposed device; in FIG. 2 - time charts; Figs. 3-8 show embodiments of individual blocks: Figs. 3 - synchronization unit of the main terminal, FIG. 4

request signal generator, FIG. 5 is a response signal detecting unit; FIG. 6

mating unit, fig. 7 is a block for distinguishing query signals; FIG. 8 is a cyclic signal extraction unit.

The time-division duplex data transmission system in the main terminal comprises a generator consisting of an output register 1, a switch 2, and request signal generators 3, 4, a synchronization unit 5, an interface unit 6, a response signal detection unit 7, and a discriminator having connected RS-trigger 8 and input register 9. The output of register 1 is connected to the control input of switch 2, the two signal inputs of which are connected to the outputs of the generators 3,4, and the output is connected to the input of block 6. The signal output of block 6 is connected n with a line, and the output with the first input of block 7, the output of which is connected to the first input of trigger 8, the second input of which is connected to the second (control) input of block 7 and the first output of synchronization block 5. The second output of block 5 is connected to

register 9, the third output with the input of register 1, and the fourth with the combined inputs of the generators 3 and 4. In the peripheral terminal, the system contains a pairing unit 10, a unit for detecting request signals 11, a synchronization unit consisting of serially connected single-vibration tori 12, 13, 14, a block for extracting a cyclic signal 15, a generator consisting of serially connected output register 16, a resolution block 17 and a response generator 18, and a discriminator consisting of series-connected block discriminating request the signals 19, the delay line 20 and the two input registers 1. 22. The signal output of the interface unit 10 is connected to the line. The input of circuit 10 is connected to the output of the generator 18, and the output is connected to the combined first inputs of block 11 and block 19. The second combined inputs of block 11 and block 19 are connected to the clock inputs of the registers 16, 21, the output of the one-shot 12 and the input of block 15. The output of block 15 connected to the gate inputs of the registers 16 and 22. The output of the single-shot 14 is connected to a permission block 17.

An embodiment of the synchronization unit 5 of the main terminal (Fig. 3) is made in the form of a series-connected clock generator 23, an n-bit counter 24, a combinational circuit 25 and a buffer register 26, the clock input of which is connected to the output of the generator 23. In this case, the switch 24 and information is recorded in the register 26 on different fronts of the clock pulses. The outputs of the synchronization unit 5 are formed by the outputs of the register 26.

The request signal generators 3, 4 and response signal 18 (Fig. 4) are made in the form of a series-connected generator o 27, a permission block 28 and a band-pass filter 29. In this case, the second input of the block 28 and the output of the filter 29 form respectively the control input and output of the generator 3 (4, 18).

The response terminal 7 of the main terminal (Fig. 5) is made in the form of a series-connected amplitude detector 30, a drive 31, the second input of which is connected to the key 32, and a comparator 33. The input of the detector 30. the control input of the key 32 and the output of the comparator 33 form accordingly, the inputs and outputs of block 7, the Block 11 request signal detection of the peripheral terminal is made in a similar way. Only a comparator with hysteresis is used.

Block 6 (10) of the interface with the line (Fig. 6) consists of isolation resistors 34,

one end connected to the first and second inputs of the differential amplifier 35, insensitive to common mode noise, and matching circuit 36, for example, a transformer. The second ends of the resistors 34, the output of the amplifier 35 and the output of the circuit 36 form respectively the input, output and output of block 6 (10).

The request signal discrimination unit 19 (Fig. 7) consists of an input signal separation circuit 37, the first and second outputs of which are connected to parallel LC circuits 38 and 39, tuned to the frequency of the generators 4 and 3, and, in addition, to the first inputs circuits 40 and 41, the outputs of which are in turn connected to the direct and inverse inputs of the comparison circuit 42. The second inputs of the circuits 40, 41 are combined. In this case, each of the circuits 40 and 41 is formed in accordance with FIG. 5 from elements similar to 30, 31 and 32. The first and second inputs and output of block 19 coincide with the input of circuit 37, the second inputs of circuits 40 and 41, and the output of the circuit, respectively

42. Block 15 extraction of the cyclical signal

(Fig. 8) consists of an integrating RS-circuit

43 connected to the key element 44 and the input of the comparator 45. The inputs of the block 15 coincide respectively with the control input of the key element. 44 and the output of the comparator 45.

In a specific embodiment, the system is implemented on microcircuits of the 140,1401,564 and 590 series. Radio pulses with the following parameters are used as interrogation and response signals:, 5ms (n is equal to the signal duration at the fourth output of block 5, and r g is equal to the signal duration at the output single-vibrator 14), the frequency of filling the request pulses Ф Т02 and 113.7 kHz and response pulses - 108 kHz, the amplitude of “200 mV. The interrogation period ms, the length of the information word and the duration of the transmission cycle are 128 ms. Cycle synchronization is carried out by the absence of a request signal at the position. The request and response signal detecting units 11 and 7 and the request signal discriminating unit 19, by processing the input mixture of the useful signal and the noise, increase the noise immunity of data transmission. An increase in noise immunity is also facilitated by the RS-flip-flop 8, delay line 20 and the method of connecting the single-vibrators 12, 13 and 14 with each other and with the rest of the peripheral terminal circuit. In this case, the single-vibrators 12 and 14 are started on the trailing edges, and 13 on the leading edges, and the inequality

T-G 1 G4 G2 + TK,

where m and T are the duration and repetition period of the interrogation signals of the main terminal;

T2, tziG4-pulse durations at the outputs of single-vibrators, respectively 14, 13 and 12 (tz 1.25 ms, GA "2.5 ms). The system operates as follows: On the leading edge of the clock signal U2 from the synchronization unit 5 (Fig. 2), the information bit to be transmitted is set at the output of register 1, by connecting the inputs of block 6 to the output of the generator 3 or 4 through the switch 2, depending on the output of register 1 is a logical zero or one. By the signal b3 from the synchronization unit 5, radio pulses (interrogation signals) are generated at the outputs of the generators 3 and 4 with a different frequency. The signal LU from the synchronization unit 5. overlapping 1) s, the RS 7 trigger 8 is set to the initial state of the unit The signal of the generator 3 or 4 from the output of the switch 2 Ui, through the block 6 Uis, LUNIA and block 10 is supplied to the first inputs of the detection unit 11 and block 19 Ui. A video pulse U is generated at the output of block 11, and a logical level Uis corresponding to the state of switch 2 (transmitted bit of information) is generated at the output of block 19, the delay in the appearance of which relative to the request signal Ui is caused by its (Ui) processing in order to increase the signal ratio /noise. An additional delay of the signal Ue relative to the UIB, introduced by the delay line 20, ensures a guaranteed recording of the received logical level Uis in the register 21 along the leading edge of the output pulse Us of the one-shot 12. The single-shot 12, triggered along the trailing edge of the pulse U, forms a guard interval of duration 4 during which the initial state of block 11 and blocks 15 and 19 is ensured. A single vibrator 13 is triggered along the leading edge of the pulse Ua (along the rear U). In turn, the single vibrator 14 is triggered by the rear window nt output pulse of a single-vibrator 13 (after time tz). An output pulse Ug of duration r 2 of a single-shot 14 is supplied to the second input of block 17 and, provided that the logic unit level is present at the output of register 16, it starts the response signal generator 18 (generates a response signal). Otherwise, if there is a logic zero level at the output of register 16, the formation of a response signal does not occur. The output pulse Us of the one-shot 12, blocking the pulse Ug, eliminates the possibility of malfunctions in the peripheral terminal due to transients associated with the edges of the request and response signals, and, in addition, increases the noise immunity of the reception due to the temporary selection of the input signal. The response signal Un of the generator 18 through block 10, line and block 6 of U16 is supplied to the first input of block 7. At the output of block 7, a video pulse Ui2 is generated, the delay in which of which relative to the response signal Un is caused by its (Un) processing in order to increase the signal ratio /noise. Said video pulse Ui2 includes a trigger 8 (if there is a response signal), the output signal Ui3 of which is recorded on the leading edge of the signal Us of block 5 in register 9 immediately before the initialization of block 7 and trigger 8 (by signal Щ). The presence of trigger 8 allows one not to impose strict requirements on the temporary position of the response signal Un and on the characteristics (by the delay of the output signal) of block 7, which, as a result, increases the noise immunity of the response signal npvi. Increasing the noise immunity of receiving the indicated signal is also facilitated by the time selection provided by the signal U4 of block 5. At the trailing edge of the pulse Us of the one-shot 12, the information to be transmitted in the next system operation cycle is established at the output of the register 16. The signal Uy at the output of circuit 15 appears only when the interval between the interrogated signals Ui increases to a certain value, for example, when one (32nd) pulse is skipped. By the Uio signal, information is recorded and received in parallel code in the registers 22 and 16, respectively, i.e. loop synchronization is provided. The clock signals UaUs of block 5 are generated (see Fig. 3) by isolating the state of the n-bit counter 24 by the combinational circuit 25. The output signals of the latter, to eliminate interference, are gated by writing to register 26. Switching the counter 24 and after - writing to the register 26 occurs on different fronts of the clock pulses of the generator 23. The request signal is informed when there is an enable signal Us at the second input of block 28 (see Fig. 4). Wherein

the filter 29 extracts the first harmonic of the output signal of the generator 27. In block 7 (see Fig. 5), the response signal after passing through the detector 30 and the drive 31, provided that the key 32 is open, triggers the comparator 33. Installing block 7 in the initial state is provided by the signal U4 at the control input of the key 32 (when the latter is closed). A comparator 33 with hysteresis in the block 11 of the peripheral terminal eliminates the crushing of its output pulses. The request signal Ui (see Fig. 6) through the resistors 34 is fed to the first and second inputs (differential input) of the amplifier 35, to the inputs of the circuit 36 and then to the line U15. The response signal Uis through the circuit 36 is fed to the differential input of the amplifier 35 and then to its output Uie. The input impedance of blocks 6 and 10 at the terminals connected to the line is determined by resistors 34, input impedance of amplifier 35, and circuit characteristics 36. Moreover, in the frequency range of the data signal, this impedance should be equal to the wave impedance of the line. Satisfying this condition ensures undistorted transmission of interrogation and response signals. The interrogation signal through circuit U17 (see Fig. 7) is supplied through the circuit 37 to the first inputs of the circuits 40 and 41 and, at the same time, to the circuits 38 and 39. In this case, the signal amplitude established on them depends on the frequency of filling of the interrogation pulses. The radio pulses generated by the generator 3, provide a greater amplitude of the signal on the circuit 39 than 38, and the generated by the generator 4 - on the contrary (on the circuit 38 more than 39). The output voltages of the circuits 40 and 41, which are proportional (in the absence of a Us signal) to the indicated amplitudes, are fed to the direct and inverse inputs of the comparison circuit 42 and provide the corresponding logic level U18. The unit 19 is initialized by the Us signal. arriving at the second inputs of circuits 40 and 41. With an increase in the interval between pulses Us. associated with the interval between the interrogation signals and the increase in the time spent for the key element 44 in the open state, the capacitor of the circuit 43 (see Fig. 8) manages to charge until the comparator 45 operates. In other cases, the capacitor of the circuit 43 to the indicated value there is no time to keep up and the signal U u does not appear.

The proposed duplex communication system improves the noise immunity

more than 20 dB data transfer compared to the prototype

Claims (1)

SUMMARY OF THE INVENTION A time-division duplex data transmission system comprising a main terminal consisting of a generator, a signal selector, a synchronization unit, a coupler, and a response detection unit, the generator output being connected to the input of the coupler, first output which is connected to the communication line, and the second output of the interface unit is connected to the first input of the response signal detection unit, with the second input of which is connected the first output of the synization blocking SN, the output of the detection unit from the input signal is connected to the first input of the signal selector, the second input of which is connected to the second output of the synchronization unit, the third output of which is connected to the generator, and a peripheral terminal consisting of a generator, a signal selector, a synchronization unit, an interface unit, and a request detection unit signals, the output of the generator being connected to the input of the interface unit, the first output of which is connected to the communication line, and the second output is connected to the first input of the request signal detection unit, the first output of the synchronization unit The generator is connected to the first input of the generator, which means that in the main terminal the generator contains an output register, a switch, the first and second generators are request signals, the input of the output register being connected to the third output of the synchronization unit, the output of the output register is connected to the first input of the switch, the second and third inputs of which are connected to the outputs of the first and second request signal generators, respectively, whose inputs are connected to the fourth output of the synchronization unit, and the output of the switch is The output of the generator, the signal selector contains a serially connected trigger and an input register, and the first input of the trigger is connected to the output of the response detection unit signal, the second trigger input is connected to the first output of the synchronization unit, and the clock input of the input register is connected to the second output of the synchronization unit, the response signal detection unit contains a detector, a drive and a comparator in series, as well as a key whose output is connected to the second drive input, moreover, the input of the detector is connected to the output of the interface unit, the output of the comparator is connected to the first input of the trigger, and the input of the key is connected to the first output of the synchronization unit, additional outputs are the key and the drive are combined and connected to the zero bus, a loop signal extraction unit is introduced in the peripheral terminal, and the generator contains a series-connected output register, a resolution block and a response signal generator, the output of the response signal generator being connected to the input of the interface unit, the signal selector contains series-connected block distinguishing request signals, delay unit, first and second input registers, the clock input of the first of which is connected to the second input of the request discriminating unit of signals, the first--, the input of which is connected to the second output of the interface unit, the output of the loop signal extraction unit is connected to the gate input of the second input register and to the gate input of the output register, the synchronization unit consists of three serially connected one-shots, the output of the last which is connected to the second enable input, and the output of the first one-shot is connected to the first input of the request signal discrimination unit, to the input of the loop signal extraction unit, to the clock input of the output reg and to the second input of the request signal detecting unit, the output of which is connected to the input of the first one-shot, the request signal detecting unit containing a detector, a drive and a comparator connected in series, as well as a key whose output is connected to the second drive input. FIG. 2 R .. | ftz. 3 2 (18} 1 27 2B L .J # s ftz. 4 Uf6 L. U /. FI26 29th L UK Jf "Gg T I and R 31 38 Uf7 I J willow Phage 7 /5 40 4 Uis