RU1775874C - Polyfrequency signal receiver - Google Patents

Abstract

The invention relates to telecommunications and can be used in telemechanics, data transmission and telephone communication systems for receiving multi-frequency dialing. The purpose of the invention is to improve the noise immunity of receiving multi-frequency code signals. The device contains: 1 input amplifier (1), N + 1 bandpass filters (2i-2N + i); N detectors (31-Zy); 1 sync pulse extraction and shaping device (4); 1 unit for monitoring the number of received frequencies (5); 1 signal duration analysis unit (6); 1 block of buffer elements (7). The device is characterized in that the input information on all channels is simultaneously analyzed for the entire significant time interval, short-term interference is filtered in the remaining frequency channels. 1 s.p. f-ly, 3 ill.

Description

Figure 1

The invention relates to the field of telecommunications and can be used in telemechanics and data transmission systems.

A known multi-frequency signal receiver comprising an input amplifier, the output of which is connected to N frequency channels having a series-pass bandpass filter, an envelope detector and a gate, an OR element, to the inputs of which the inputs of the envelope detectors are connected, and their signal duration analyzer, the input of which is connected to the output element OR, and the output to the control inputs of the gates of N frequency channels. A disadvantage of this device is the low noise immunity of the input speech signal and the MF code signal.

The closest to the technical essence of the present invention is a multi-frequency signal receiver containing an input amplifier, the output of which is connected to N parallel frequency channels, each of which contains a series-pass bandpass filter, an envelope detector and an AND element, and the outputs of the detectors are connected to the inputs of the OR element , the output of the latter is connected to the input of the unit for monitoring the number of received frequencies and the unit for analyzing the signal duration, the outputs of which are connected to the inputs of the And element, in stroke element and is connected to the remaining inputs of the AND N frequency channels.

However, this receiver has low noise immunity. In the prototype receiver, the start of the signal duration analysis unit and the control unit for the number of received frequencies occurs when a positive pulse appears at the output of the OR circuit common to all N frequency channels. A signal at the output of an OR appears when positive polarity signals are generated at the output of one or more envelope detectors. After the appearance of a pulse at the output of the OR element, the number of pulses arriving at its input from envelope detectors can change, and the signal at the output of the OR element will remain unchanged. This will result in a restart of the signal duration analysis unit, which will result in the passage of erroneously received signals, as well as the prohibition of passing the correct combination to the output. In addition, when sequentially polling N frequency channels by the control unit for the number of received frequencies, it is possible that a change in the signal o, ..., channel that occurs after polling this channel is not recorded,

which will lead to the reception of false information.

The purpose of the invention is to increase the noise immunity of receiving multi-frequency code signals.

This goal is achieved in that in the present invention, in contrast to the prototype, the input information for all channels is simultaneously analyzed during the entire significant time interval, for which a system containing an input amplifier, to the output of which IM parallel frequency channels are connected, each of which contains sequentially 5 connected band-pass filter, envelope detector, outputs of the frequency channels are connected to the corresponding inputs of the control unit of the number of received frequencies, the corresponding outputs of which connected to the inputs of the signal duration analysis unit, additionally contains the N + 1-th bandpass filter, a device for selecting and generating clock pulses and a block of buffer elements, the input N + 1-ro of a 5-band filter connected to the input of the device for selecting and generating clocks, outputs which are connected to the corresponding inputs of the control unit of the number of received frequencies and the unit

0 analysis of the signal duration, the remaining outputs of the control unit for the number of received frequencies are connected to the inputs of the block of buffer elements, to the remaining input of which the output of the analysis unit is connected

5 signal duration. Moreover, the control unit for the number of received frequencies contains a decoder, a register, an And element, a comparison circuit, a trigger, a one-shot oscillator, a clock pulse generator and a delay line,

0 and the information inputs of the control unit for the number of received frequencies are parallel connected corresponding inputs of the storage device, register and comparison circuit, the outputs of the register are connected to the corresponding inputs of the comparison circuit, the output of the decoder is connected to the input of the one-shot, to the remaining inputs of which the trigger output is connected, the input of which connected to the corresponding output of the single-shot, the remaining output of the single-shot connected to the corresponding inputs of the register, the clock input of the register is connected to the output of the clock generator, to the remaining

5, the input of the register is connected to the output of the delay line, the communication input of the control unit for the number of received frequencies with the device for selecting and generating clock pulses is the corresponding trigger input and the input of the delay line, the inputs of the elements And are connected to the outputs of the comparison circuit and the clock generator, the output of the number control unit of the received frequencies associated with the signal duration analysis unit is the output of the And element, the information outputs of the control unit for the number of received frequencies are the outputs of the register . The signal duration analysis unit comprises a counter and a comparison circuit connected in series, wherein the input of the signal duration analysis unit is the counter input and the output is the output of the comparison circuit.

In FIG. 1 is a structural diagram of the claimed device; in FIG. 2 shows a functional block diagram of the control unit for the number of received frequencies; in FIG. 3 is a functional block diagram of the analysis of the duration of the signals.

The receiver contains an input amplifier

1, N + 1 bandpass filters 2.1 2.N, N

detectors 3.1, .... 3.N, a device for isolating and generating a clock pulse 4, a unit for monitoring the number of received frequencies 5, a unit for analyzing the signal duration 6 and a block of buffer elements 7, the output of the input amplifier being connected to the inputs of all bandpass filters 2.12.N, the outputs of the bandpass filters 2.12.N are connected to the inputs of the respective detectors 3.1, ..., 3.N, the output of the bandpass filter 2 is connected to the input of the device for selecting and generating clock pulses, the outputs of the detectors 3.13.N are connected to the information inputs of the control unit of the number of received frequency 5, the output of which is connected to the input of the signal duration analysis unit 6, the remaining outputs of the number control unit 5, the received frequencies are connected to the inputs of the buffer elements unit 7, the output of the allocation unit is connected to the remaining inputs of the control unit for the number of received frequencies 5 and the signal duration analysis unit 6 and generating clock pulses 4, the outputs of the device are the outputs of the block of buffer elements 7.

In FIG. 2 is a functional diagram of a unit for monitoring the number of received frequencies 5, which contains a decoder 8, a register 9, a comparison circuit 10, a trigger A, a single vibrator 12, a clock generator 13, a delay line 14, an element 15, and the inputs of a unit for monitoring the number of received frequencies 5 are parallel connected to the corresponding inputs of the decoder 8, register 9 and comparison circuit 10, the output of trigger 11 is connected to the input of one-shot 12, the corresponding output of which is connected to the input of trigger 11, to the remaining input of one-shot 12 the output of the decoder 8, the remaining output of the one-shot a 12 is connected to the corresponding input of the register 9, the outputs of which are connected to the remaining inputs of the comparison circuit 10, the output of the clock generator 13 is connected to the corresponding input of the register 9, the output of the delay line 14 is connected to the remaining input of the register 9, the inputs of the element And 15 are connected to the output of the comparison circuit 10 and the clock generator 13, the synchronization input of the control unit of the number of received frequencies 5 are the connected input of the delay line 14 and the remaining input t rigger 11, outputs a control information block of received frequencies are 5 outputs the register 9, the remaining output of the unit 5 is the output of AND 15.

The elements of the block 5 for monitoring the number of received frequencies shown in FIG. 2 can be implemented as follows.

The functions of the decoder 8 can be performed by the chip 541РТ1,

Register 9 can be performed on the chip K155IR13.

Comparison scheme 10 can be performed on two K531SP1 microcircuits.

The trigger 11 can be implemented on the chip K555TM2.

The one-shot 12 may be represented by the K155AG1 chip.

The clock generator 3 is made according to one of the schemes shown in the Kols-Mbet EA Timers. - M .: Radio and communication, 1983.-p. 35-64.

The delay line functions can be performed by the K555AGZ chip.

Element And 15 is made on a chip K555LI4.

The functional block diagram of the signal duration analysis unit b is shown in FIG. 3 and includes a counter 16 and a comparison circuit 17, wherein the input of block b associated with block 5 is the input of the counter 16. With block 7, block 6 is connected to the remaining inputs of the counter 16, and the outputs of the counter 16 are connected to the inputs of the comparison circuit 17. the corresponding output Which is the output of the signal duration analysis unit 6.

As the counter 16, you can use the chip K155IE2.

The functions of the comparison circuit 17 may be performed by the K531SP1 chip.

The device operates as follows.

The input signals amplified by the input amplifier 1 are fed to bandpass filters 2.1, ... 2.N + 1, whereby 2.M + 1st bandpass filter selects the clock frequency. After the envelopes of the output signals 2.1 ... 2.N are extracted using the detectors 3.1 ... Z.P, analysis of the input information begins.

If, after the start of the clock (after the arrival of the clock), the number of frequencies matches the specified one, this combination of frequencies is stored in block 5 for monitoring the number of received frequencies. Then, during the clock interval, the combination stored in the memory (register 9) is compared with the current one. When they coincide, a signal is issued to the analysis unit for signal duration 6, which gives an enable signal to the block of buffer elements 7 if the coincidence signal is present at the output of the circuit for at least tp, which is less than the time interval tk, during which is the transmission of one code combination.

If a code combination is received during the clock period and it is present for t..k, then a decision will be made that the signal is correct and at the moment of arrival of the clock pulse, i.e., at the end of the clock interval, a signal will be output on block 7 of buffer elements, according to which information from the storage device of block 5 is transferred to the block of buffer elements 7 and transmitted to the output.

Due to various interferences, the signals allocated by the bandpass filters 2.1, ..., 2.N may have distortions in the form of short-term loss of signals. Then at the output of the control unit the number of received frequencies 5 will be a signal of the corresponding form. Moreover, if t. .p + t, p and t.p..p t.k ,,

where t.p.min is the minimum allowable transmission time of the code combination at which signal recognition is still possible;

p and t.p are the duration of the signals at the output of the comparison circuit 10;

then block b generates a recording enable signal and upon arrival of the clock pulse, information is recorded in block 7 and transmitted to the output.

If, as a result of the action, noise signals appear in any other channels, i.e. when signals appear in three or more channels, the circuit operates in the same way as in the case of a short-term loss of a useful signal.

In the case when the interference becomes such that the code combination will be present for the time t..p.min, then this is perceived as a failure, analysis unit

the duration of signal b does not provide an enable signal to block 7 of the buffer elements, and upon arrival of the clock from block 7, the previous information is erased.

The decoder 8 is organized in such a way that at its output a logical 1 signal appears when the number of signals at its input corresponds to a given number of frequencies. Otherwise, the output is a logic level of 0.

5 When a sync pulse occurs, a write pulse generating circuit including a decoder 8, a single vibrator 12, and a trigger 11 is ready. When a logical 1 occurs at the output

0 of decoder 8, the circuit generates a short pulse of information recording in register 9, subsequent changes at the information input during this clock interval do not cause formation

5 pulse recording. When a write pulse appears in the register 9, the input information is stored. At the end of the write pulse, the register 9 goes into the information storage mode and the recorded combination appears at the output of the register 9. This combination is fed to the inputs of the comparison circuit 10, and the combination of the outputs of the detectors 3.1, ..., 3.N, i.e. current information. If these combinations are equal, the output of the comparison circuit 10 is a high-level signal, which allows the passage through the circuit And 15 pulses from the generator 13 to the counter 16. Thus

In a way, the number of pulses arriving at counter 16 characterizes the duration of the reception of the correct code combination. In other words, the code at the output of the counter 16 is uniquely associated with a time t.p accurate to a sampling period. This code is compared with the fixed code. comparison circuit 17. Code Selected to ensure proper reception when present

0 of the useful signal for at least 70% of the time interval of the t.k.

The signal that the code on the counter 16 is larger than the specified code is supplied to the control circuit of the buffer element 4, which

5, upon arrival of the clock pulse, it allows information to be written to the buffer element 4 from register 9. If, at the time of the arrival of the clock pulse, there was no more signal at the output of the comparison circuit 17, a reset signal is generated in the buffer element 4 by

All inputs are written O (a failure has occurred).

At the end of the clock pulse, a delay pulse appears at the output of the delay line 14, which erases the information in register 9 and prepares a circuit for generating a write pulse 4 for analysis of the next code pattern.

Claims (2)

SUMMARY OF THE INVENTION 1. A multi-frequency signal receiver comprising an input amplifier, to the output of which N parallel communication channels are connected, each of which consists of a series-connected bandpass filter and a detector, the outputs of N detectors connected to the first N inputs of the control unit for the number of received frequencies, the first the output of which is connected to the first input of the signal duration analysis unit, characterized in that, in order to increase noise immunity, a (N + 1) -u bandpass filter is introduced into the receiver, the device is highlighted and forming a clock pulse and a block of buffer elements, wherein the input (NM) -ro of the bandpass filter is connected to the output of the input amplifier, and the output (N + 1) -ro of the bandpass filter is connected to the input of the device for extracting and forming the clock, the first output of which is connected to the second the input of the control unit for the number of received frequencies, and the second output is connected to the second input of the signal duration analysis unit, the output of which is connected to the first input of the buffer element block, the second input of which is connected to the second output of the control unit and received frequencies, the third N outputs of which are connected to the N inputs of the third block buffer elements, whose N outputs are the outputs of the receiver. - 2. The receiver according to claim 1, with the proviso that the control unit for the number of received frequencies comprises a decoder, a register, an AND element, a comparison unit, a trigger, a one-shot oscillator, a clock generator and a delay element, moreover, in parallel connected information inputs of the decoder, register and the first eight the input of the comparison unit is connected to the outputs of the detectors, and eight outputs of the register are connected to the second eight inputs of the comparison unit, the first and second outputs of which are connected respectively to the first and second inputs of the element And, the third input of which is connected to the output of the clock generator and to the clock input of the register whose control inputs are connected to the direct output of a single-shot, whose inverse output is connected to the R-input of the trigger, the S-input of which is connected to the input of the delay element, which is the second input of the block number of frequencies of the received warning light, wherein the delay elemeita output coupled to the reset input of the register, the decoder output connected to the input synchronization odnovib- Rathore, and element outputs D and clock generator are the first to the second control unit outputs the frequency number received respectively. R & ta S | R I Editor Compiled by V. Getman Tehred M. Morgenthal Block 6 I Figure 3 Proofreader L. Fil