RU1774298C - Phase-to-code converter verifier - Google Patents

Abstract

The invention can be used to test phase-to-code converters operating as part of phase angle converters. The device comprises a clock pulse generator 1, a frequency divider 2, frequency decoder 3, a pulse shaper 4, a counter b, switching blocks 7 and 8, controlled phase shifters 9, 10 and 16, a pulse switch 11, a gated pulse shaper 12, a source 13 logic signal, switches 5, 14, 15, 17, frequency converter 18, subtraction unit 21, registration unit 25. By introducing the second and third controlled phase shifters 10 and 16, the pulse switch 11, the gated pulse driver 12 and the second switching unit 7, the device's functionality is expanded by simulating the push-pull operation mode of the verified converter and determining the error in dynamic mode, as well as increasing the reliability of the test . 3 s.p. f-ly, 5 ill. sl C v | vj ju y 00

Description

The invention relates to measurement techniques and can be used to test phase-to-code converters.

A device for checking digital devices is known, which can also be used for checking phase-to-code converters, containing a reference signal source, a modulator, terminals for connecting a verified device, a code subtracting unit, a recording unit, a clock generator, a reversible pulse counter, a decoder , a reverse trigger, the first and second AND elements, a controlled frequency divider, a synchronous frequency divider, a logical signal source, and three switches.

However, the known device does not provide reliable verification of phase-to-code converters in all real modes of their operation, and the use of discrete or digital code-controlled phase shifters as a modulator in this device leads in the first case to the difficulty of obtaining reproducible phase shift with high accuracy and stability, and in the second case, to a malfunction of the verified phase-to-code converter, when the value of the reproduced phase shift passes through 0 °. In addition, the known device provides either the calculation of the error of measurement of the phase shift of the verified transducer in static mode, or the calculation of the error of measurement of the rate of change of phase during the verification of phase-to-code converters that additionally measure this parameter in the dynamic mode. The known device does not provide calculation of the error in measuring the phase shift in dynamic mode.

The closest in technical essence to the invention is a device for checking digital devices, which contains a frequency converter, a modulator, terminals for connecting a device to be verified, a code subtracting unit, a registration unit, a clock pulse generator, a reversible pulse counter, a decoder, a reverse trigger, the first and second AND elements, a controlled frequency divider, a synchronous frequency divider, a logical signal source, three switches, a switching unit, and two short pulse shapers. In this device, the input of the registration unit is connected to the output of the code subtraction unit, the first input of which is connected to the terminals for connecting the output of the device under verification, the terminal for connecting the input of which is connected to

the output of the modulator, the input of which is connected to the output of the frequency converter, to the terminal for connecting the reference input of the device to be verified and through the first short-pulse generator to the control input of the switching unit. The output of the reversible pulse counter is connected to the input of the switching unit, the input of the decoder and through the first switch with

0 by the first input of the reverse trigger, the second input of which is connected to the decoder output and through the second short-pulse shaper with the installation inputs of the frequency converter, controlled frequency divider and synchronous frequency divider, the direct output - with the first input of the first element And, and the inverse output - with the first input of the second element I. The second inputs of the elements And through the second switch, a synchronous frequency divider and a controlled frequency divider are connected to the output of the clock generator and the input of the converter Frequency, and the outputs to the inputs of summing and subtracting a reverse pulse counter, respectively. The output of the logical signal source through the third switch is connected to the second input of the code subtraction unit. The output of the switching unit is connected to the control 0 input of the modulator.

However, this device also does not provide reliable verification of the phase-to-code converter in all real modes of their operation as part of phase angle converters, disrupts the operation of verified converters when the decreasing phase of the signal passes through zero in the dynamic mode of operation, and does not provide calculation of the measurement error

0 phase shift in the dynamic mode of the device.

The aim of the invention is to expand the functionality and increase the reliability of verification due to

5 simulations of the push-pull (calibration - measurement) operating mode of the phase-to-code converter included in the phase angle converter, determination of the error in the dynamic mode of operation

0 and eliminate the malfunction of the verified phase-to-code converter when the value of the reproduced decreasing phase shift in dynamic mode passes through 0 °.

5 The goal is achieved by the fact that in a known device for testing converters phase-code containing a clock generator, a controlled frequency divider, the input of which is connected to the output of the clock generator,

decoder, first controlled phase shifter, counter, first switching unit, subtraction unit, registration unit, the input of which is connected to the output of the subtracting unit, first, second and third switches, a logical signal source, the output of which is connected to the input of the second switch, short pulse shaper, the input and output of which are connected respectively to the output of the decoder and the installation input of the controlled frequency divider, the output of which through the first switch is connected to the clock input of the counter, the output of the counter connected to the input of the decoder and the input of the first switching unit, the first output of which is connected to the control input of the first controlled phase shifter, the frequency converter, the output of which is connected to the first terminal to connect the verified converter, and the clock and installation inputs are connected respectively to the output of the clock and the output of the short-pulse generator, second terminals for connecting the verified converter, bitwise connected to the first input of the subtraction unit, the third terminals for connecting a verifiable converter, a second and third controlled phase shifters, a tunable pulse shaper, a second switching unit, the fourth and fifth terminals for connecting a verifiable converter, a pulse switch, the control input and output of which are connected to the fourth and third terminals for connecting the verified converter, the fifth terminal for connecting the verified converter is connected to the gate input of the second switching unit, the first input of which is connected connected to the output of the counter, the second input of the second switching unit is connected to the outputs of the second switch, and the output is connected to the second input of the subtraction unit, the output of the second controlled phase shifter is connected to the control input of the first switching unit, the inputs of the first and third controlled phase shifters, and the gate input a gated pulse driver, the code input of which is connected to the decoder input, and the clock input and output are connected respectively to the output of the clock generator and the third pulse input the switch, the clock inputs of the first, second, third controlled phase shifter and the frequency converter are combined, the outputs of the first and third controlled phase shifters are connected to the second and first inputs of the pulse switch, the control input of the third controlled phase shifter is connected to the second output of the first switching unit, the output the source of the logical signal is connected through the fourth switch to the installation input of the counter and through the third switch with the control input of the second control phase shifter, the input of which is connected to the output of the frequency converter.

The second switching unit contains N D-flip-flops, the D-inputs of which are connected to the first input of the second switching unit,

5 a C-inputs - to the gate input of the second switching unit, N AND-OR elements, in which the outputs are connected to the output of the second switching unit, the first inputs - with the outputs of D-flip-flops, the second inputs - with

0 by the second input of the second switching unit, the third inputs are combined and connected to the normally closed contact of the switch, and the fourth inputs are combined and connected to the normally open

5 to the contact of the switch, the movable contact of which is connected to a source of logical zero.

The pulse switch contains an AND-OR element, the first, second, and third inputs of which are connected respectively to the first, second, and third inputs of the pulse switch and an element NOT whose output is connected to the fourth input of the AND-OR element, and the input to the control

5 to the input of the pulse switch and to the fifth and sixth inputs of the AND-OR element, the output of which is connected to the output of the pulse switch.

The impulse driver being generated contains an AND element, the inputs of which are connected to the code input of the pulse generator being driven, and the output is connected to the input of the first trigger, the second trigger, whose C-echo is connected to the gate

5 by a gate of the gated pulse shaper, D-input - with the output of the first trigger, a counter whose C-input is connected to the clock input of the gated pulse shaper, R-input - to the output

0 of the second trigger and the output of the gated pulse former, and the output is combined with the R-inputs of the first and second triggers.

In FIG. 1 shows a block diagram of a device for checking phase-to-code converters; figure 2 is a functional diagram of the second used switching current; in Fig.3 is a functional diagram of a pulse switch; Fig. 4 is a functional diagram of a gated pulse shaper;

on fmg.5 - time diagrams explaining the operation of the device.

A device for checking phase-to-code converters (Fig. 1) contains a clock generator 1, a controlled divider

2 frequencies, the input of which is connected to the output of the clock generator 1, the decoder 3, the shaper 4 of short pulses, the input and output of which are connected respectively to the output of the decoder

3 and the installation input of the controlled frequency divider 2, the output of the latter through the first switch 5 is connected to the clock input of the counter 6, the outputs of the counter b are connected to the input of the decoder 3, to the first input of the second switching unit 7 and to the input of the first switching unit 8, the outputs of which connected to the control input of the first controlled phase shifter 9

and to the control input of the third control phase shifter 10, the outputs of the first and third controlled phase shifters 9 and 10 are connected respectively to the second and first ramps of the pulse switch 11, a gated pulse shaper 12, the code input of which is connected to the input of the decoder 3, and the clock input and the output are connected respectively to the output of the clock generator 1 and the third input of the pulse switch 11, the source: 13 is a logical signal, the output of which through the second switch 14 is connected to the second input of the second of the switching unit 7, through the third switch 15 with the control input of the second control phase shifter 16, and through the fourth switch 17 with the setting input of counter b, the output of the second controlled phase shifter 16 is connected to the control input of the first switching block 8, the gate input of the gated driver 12 pulses and the input of the first and third controlled phase shifters 9 and 10, a frequency converter 18, the output of which is connected to the input of the second controlled phase shifter 16 and with the first terminal 19 for connecting transducer, and the clock and installation inputs are connected respectively to the output of the clock generator 1 and the output of the shaper 12 short pulses, the clock inputs of the first, second, third controlled phase shifters 9, 10, 16 and the frequency converter 18 are combined, the second terminals 20 for connecting the transducers being verified are bitwise connected to the first input of the subtraction unit 21, the third and fourth terminals 22, 23 are connected respectively to the control input and output

pulse switch 11, the fifth terminal 24 for connecting the verifiable converter is connected to the gate input of the second switching unit 7, the output of which is connected to the second input of the subtracting unit 21, the recording unit 25, the input of which is connected to the output of the subtracting unit 21.

In order to obtain a sinusoidal reference and phase-varying signals at the output of the device, filters 26 and 27 can be connected to the outputs of the frequency converter 18 and the pulse switch 11.

The second switching unit 7 (Fig. 2) contains N D-flip-flops 28, the D-inputs of which are the first input of the second switching unit 7, and the C-inputs are combined and are the gate input of the second switching unit 7, N AND-OR 29 elements in which the outputs are the output of the second switching unit 7, the first inputs are connected to the outputs of the D-flip-flops 28, the second inputs are the second input of the second switching unit 7, the third inputs are combined and connected to the normally closed contact of the switch 30, and the fourth inputs are combined and connected to normally open that contact of the switch 30, the movable contact of which is connected to a source of logical zero.

The pulse switch 11 (Fig. 3) contains an AND-OR element 31, the first, second and third inputs of which are the first, second and third inputs of the pulse switch 11, respectively, and the output is connected to the output of the pulse switch 11 and the element is NOT 32, the output of which connected to the fourth input of the AND-OR element 31, the input being the control input of the pulse switch 11 is connected to the fifth and sixth inputs of the AND-OR element 31.

The gated pulse shaper 12 (Fig. 4) contains an AND 33 element, the input of which is the code input of the gated pulse shaper 12, and the output is connected to the C-input of the first trigger 34, the second trigger 35, the C-input of which is the gating input of the gated shaper 12 pulses, and the D-input is connected to the output of the first trigger 34, the counter 36, the C-input of which is the clock input of the gated pulse former 12, the R-input is connected to the output of the second trigger 35 and is the output of the gated 12 pulse owls, and the output is combined with the R-inputs of the first and second triggers 34, 35,

As a clock pulse generator 1, a rectangular pulse generator can be used, the frequency of which is stabilized with a quartz resonator.

The controlled frequency divider 2 is designed to change the repetition period of the control code generated by the counter 6 in dynamic mode and can be implemented on microcircuits, for example 155IE8, the division ratio of which is changed by external control commands generated, for example, by switch.

The decoder 3 is designed to provide a signal at the time of resetting the counter 6 and is a multi-input AND element (AND-NOT).

Shaper 4 pulses provides zeroing of the frequency converter 18, the controlled frequency divider 2 according to the signal of decoder 3, which appears at the time of resetting counter 6. Synchronization of the controlled frequency divider 2 and frequency converter 18 with each other using 4 shorter pulses eliminates the possibility of mismatch the channel for forming the control code of the first and third controlled phase shifters 9, 10 relative to the channel for forming the reference voltage in the dynamic mode. Shaper 4 short pulses can be made in the form of a single vibrator.

The counter 6 can be performed on the chips 533IE10. In order to verify phase-to-code converters in static mode, it is necessary to apply voltage log.1 to the pre-enable inputs of chips 533IE10, and a logic code corresponding to a certain phase value to parallel information inputs. To work in dynamic mode, the log 0 level must be present at the pre-recording enable inputs.

The first switching unit 8 is a set of D-flip-flops, the outputs of which are also the output of the first switching unit 8, the D-inputs are its input, and the clock inputs are combined and are the control input of the first switching unit 8. In this case, the control code is not only transmitted to the inputs of the first and third controlled phase shifters 9, 10, but is also stored at the output of the first switching unit 8 until the next pulse arrives from the frequency converter 18.

The second switching unit 7 serves for. selecting an exemplary code supplied to the second input of the code subtracting unit 21, and to eliminate the dynamic error of calculating the error in measuring the phase shift in the dynamic mode.

As the first, second, and third controlled phase shifters 9, 10, and 16, a controlled pulse delay device based on autoswitch can be used. Mg 573865. To do this, it is enough to submit a code corresponding to the value of the required signal delay to the control inputs of the first counter of the controlled pulse delay device, and a code corresponding to the value of the half-period of the delayed signal to the control inputs of the other counter of the controlled pulse delay device, and exclude two the valve of the controlled pulse delay device with its connections.

The pulse switch 11 serves to select a signal supplied to the input of the phase-code converter with a positive or negative (increasing or decreasing in dynamic mode) phase shift according to the control signal specified by this converter.

The gated pulse shaper 12 is designed to generate a single pulse with a duration equal to half the signal period at the output of the third controlled phase shifter 10, at the moment of the arrival of a gated leading edge of the pulse from the output of the second controlled phase shifter 16 under the additional condition that at its code input it time all units are present.

The source 13 of the logical signal generates at its output a constant voltage with a level of log. Oh and the log. 1.

As switches 5, 14, one common switch for N positions and two directions can be used.

As the switches 15 and 17, N toggle switches for two positions can be used.

The frequency converter 18 is designed to generate a reference signal from the pulse voltage at the output of the generator 1 and, depending on the ratio of the required frequencies at the output of the generator 1 and the frequency converter 18, contains either a divider or a frequency multiplier. If a frequency divider is used as a frequency converter 18, it can be implemented on chips 533IE10 with a switch (if necessary, change the frequency of the reference voltage). If a frequency multiplier is used as the frequency converter 18, then it can be a voltage-controlled multivibrator, the output

which is the exit

a multiplier connected to a counting input of a frequency divider, the output of which is connected to the input of a pulse detector, the second input of which is connected to the output of a clock pulse generator 1, and the output through an integrating RC circuit with a multivibrator control input.

The code subtracting unit 21 is designed to subtract the code corresponding to the error value of the verified converter, and can be implemented on elements 533IM6, 533LAZ, 533LE1, etc.

Block 25 registration contains a decoder and digital indicators. The registration unit 25 may be a digital printing device or a computer interface unit.

A device for checking phase-to-code converters operates as follows.

The clock generator 1 generates a continuous sequence of rectangular pulses (Fig. 5, a), which, through the frequency converter 18 (Fig. 5, g), enters the input of the second controlled phase shifter 16, as well as through the controlled frequency divider 2 and the first switch 5 to the clock input of the counter 6 pulses operating in the counting (dynamic) mode.

When the device for checking phase-to-code converters is in dynamic mode, a cyclic sequence of control codes (Figs. 5, b, c, d) is generated by the first and third controlled phase shifters 9, 10.

The control code (Fig. 5, b, c, d) is transmitted to the inputs of the first and third controlled phase shifters 9 and 10 through the first switching unit 8 (Fig. 5, k, l, m) only along the leading edge of the pulses coming from the output the second controlled phase shifter 16 (Fig. 5, h), moreover, for the simultaneous reproduction of two signals, increasing and decreasing in phase, it is necessary to feed the inputs of one of the control phase shifters (for example, 9) direct, and to the control inputs of another controlled phase shifter (e.g. 10) inverse control codes.

The second controllable phase shifter 16 is designed to reproduce an additional phase incursion (Fig. 5, h) relative to the phase of the signal (Fig. 5, g), the value of which is set using the third switch 15.

The output signals of the first and third controlled phase shifters 9 and-10 (Fig. 5, n, o) with increasing decreasing phases

fed to the pulse switch 11. (Fig. 5 also shows the dependences p (i) of the phase shift at the outputs of the phase shifters 9 and 10). Depending on the

control signal of the pulse switch 11 to the third terminal 22 for connecting the verified converter pulses are supplied with increasing (Fig. 5, o) or decreasing (Fig. 5, n) phase relative to the signal (Fig. 5, g).

Gated pulse shaper 12 provides the formation of an insert pulse (Fig. 5, i) at the time of a pause, a longer period when crossing through zero

signal decreasing in phase (Fig. 5, n).

Gated pulse shaper 12 (figure 4) works as follows.

In the initial state, triggers 34 and 35

are not in the O state and prohibit operation of the counter 36 in the counting mode. At the moment of the appearance at the code input of the gated driver 12, the pulse of all units at the output of the element And 33 there is a difference

from O to 1, which sets the first trigger 34 to state 1. With the arrival of the leading edge of the pulse supplied to the gating input of the gated pulse former 12, the second trigger 35

it is also set to state 1, allowing counter 36 to operate. When level 1 appears at the output of counter 36, triggers 34 and 35 are set to state O and prohibit its operation in counting mode. AT

as a result, a single pulse appears at the output of the gated pulse driver 12, the duration of which depends on the conversion factor of the counter 36 and is equal to half the signal period by

the output of the third controlled phase shifter 10 (Fig. 5, i).

The phase-delayed (FIG. 5, n or FIG. 5, o) and reference (FIG. 5, g) pulse sequences are fed to the corresponding inputs of the transducer being verified.

At the output of the verified phase-to-code converter, we have the result of measuring the phase of the signal, which, through the second

terminals 20 in the form of a code are supplied to the first input of the code subtracting unit 21. To the other input of the block 21 subtracting from the output of the pulse counter 6 through the second switching unit 7 (when the contact of the switch 30 is in the upper position, as shown in Fig. 2), a code is supplied whose value corresponds to the exemplary phase value of the signal reproduced at the output of the pulse switch 11 . Moreover, since when operating in dynamic mode, the measurement result of the transducer must be correlated in time in block 21 of the code subtraction with the exemplary phase value specified exactly at the time the measurement was started, to the second 2 with the lock switching fifth terminals 24 for connecting the power metal fed by the converter and the gated signal at the rising edge of which recording is effected exemplary code phase values output from the counter used for D-flip-flops 28 of the second switching unit 7,

The difference between the measured and reproduced values and the phase of the signal corresponding to the error of the verified transducer, from the output of the code subtracting unit 21, enters the registration unit 25.

If the verified converter in addition to measuring the phase of the signal also allows measuring its rate of change, then to determine the error of measuring the speed of the phase change in the verified phase-to-phase converter to the second input of the code subtracting unit 21 from the output of the logical signal source 13 using the second switch 14, an exemplary value code corresponding to the rate of change of the phase of the signal at the output of the pulse switch 11 is supplied. The second switching unit 7 is switched to the specified mode by transferring the contact the switch 30 in the circuit of FIG. 2 to the lower position.

When the device for checking phase-code converters is in static mode (for which the 6 pulse counter is switched to the recording mode of information from the preset inputs by supplying a log level. O to the pre-recording enable input), a constant control code of the first and third controllable phase shifters 9 and 10, defined as the installation input using the fourth switch 17.

The phase shifts of the signals at the outputs of the first and third controlled phase shifters 9 and 10 in this case are also constant (one positive, one negative) and change simultaneously only when the position of the fourth switch 17 changes.

Otherwise, the operation of the device for checking phase-to-code converters in static mode coincides with its operation in dynamic mode. The determination of the error in the measurement of the phase shift by the verified phase-to-code converter in static mode is carried out at

Claims (4)

finding contact switch about the top according to the scheme of FIG. 2, the position of the Invention 1 A device for checking phase-to-code converters containing generator j clock pulses, a controlled frequency mux, the input of which is connected to m of the clock generator, p - i torus, first controllable phase transformer,. telg, counter, first switchgear unit, power supply control unit, registration unit “One of the first, second and third switches is connected to the output of the subtraction unit by a logic signal source, the output of which is connected to the input of the second nenet channel. shaper short impl vsog; i OUTPUT OF WHICH CONNECT1 COOT81C, c. But to the output of the decoder and the installation the input of the controlled frequency divider r, whose input is through the first. The circuit is connected to the clock Vlod, and if the counter is connected, it is connected to the Vls; cr ati ra and the entrance of the feather; block i jM -i -Tann the first output of which is connected (to the direct input of the first controlled one with f, it is a repeater, which is preoboobesovat. frequency whose output is connected to the subdirectory of the verifiable oect j.i , and TZKTORI and era toei-in and och are connected respectively i u or clock pulse generator in i, vot.Mi is a short-circuit breaker and pulossch terminals for connection nobec ifHjro, | рл educator ° connected by ricp v, the RF house of the read block, which is 11 i the connection is more faithful. PSOOS i o: yyy, from which s t ave, in addition to i of the Fuchmdischet extension n - aw enhancements and enhancements to the second and third phase and the second and third phase shifters, which make it possible to integrate the form factor and integrate the total switching, quad and IT. n i icv.b v. Connections Verify i Chreo. s, pva LA, IMPULSE KOMMU1ETSR 1 oaVPT CHI P the input and output of which is connected to -CL L ccf paired with the fourth one. lsg-t-t DG 1 connecting the goverremsgo pr rtr, the fifth terminal dp kg) ° convertible 1 g gel LOCL II -.l her With a gate input for VO mutations, the first IT input to the counter output is the fourth input with i tit switch, about switching between with РЫ odz i switch, l the second input and the second input of the rni input, or the input controlled by the input to the input oh oh g Y tion, inputs of the first i nppt, re phase shifters and the gating input of the gated pulse shaper, the code input of which is connected to the output of the decoder, and the clock input and output are connected respectively to the output of the clock pulse generator and the third input of the pulse switch, the clock inputs of the first, second, third controlled phase shifters and the frequency converter are combined, the outputs of the first and third controlled phase shifters are connected respectively to the second and first inputs of the pulse switch, the control input of the third control The phase shifter is connected to the second output of the first switching unit, the output of the logical signal source is connected through the fourth switch to the installation input of the counter and through the third switch with the control input of the second controlled phase shifter, the input of which is connected to the output of the frequency converter. 2. Device pop. 1, characterized in that the second switching unit contains N D-flip-flops, the D-inputs of which form the first input of the second switching unit, and the C-inputs are connected to the gate input of the second switching unit, N elements And -OR, the outputs of which form the output of the second switching unit, the first inputs of the AND-OR elements are connected separately to the outputs of the D-flip-flops, the second inputs of the elements AND-OR form the second input of the second switching unit, the third inputs of the elements AND-OR combined BMO / They are connected to the normally closed contact of the switch, the fourth inputs of the AND-OR elements are combined and connected to the normally open contact of the switch, the movable contact of which is connected to the source of logic zero. 3. Device pop. 1, characterized in that the pulse switch contains an AND-OR element, the first, second and third inputs of which are the first, second and third inputs of the pulse switch, and the output is the output of the pulse switch, element NOT, the output of which is connected to the fourth input of the AND-OR element, and the input, which is the control input of the pulse switch, is connected to the fifth and sixth inputs of the AND-OR element. 4. Device pop. 1, characterized in that the gated pulse shaper contains an element And, the inputs of which form the code input of the gated pulse shaper, and the output is connected to the C-input of the first trigger, the second trigger, the C-input of which is a gating input the gate driver, and the D-input is connected to the output of the first trigger, the counter, the C-input of which is the clock input of the gate driver, the R-input is connected to the output of the second trigger, which is the output of the gate rovatel pulses and combined with the counter output R-inputs of the first and second flip-flops. Ј-- C-prs KcccbfcJ & r. foKtr ol yu fa cig 3 t ipooui j O (fir M -V -a -u 4J -yJ R g vi -u